CN1588989A - Method and its device for keeping display synchronization in video frequency decoding system - Google Patents
Method and its device for keeping display synchronization in video frequency decoding system Download PDFInfo
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Abstract
A method for keeping synchronous display in a video decode system increases flag bits from program reference information and displayed times stamp information picked up from the audio/video transmission stream and judges if the program clock reference information is continuous, if not, the value is latched and it begins counting and turn-over the flag bit and also that of the times stamp and transfers the program clock reference and timestamp information to the display control device comparing the flag bits, the control module continues the current data process if the same, or it informs the clock reference process module if not and the value of the latch is added to the counter to be transferred to the control device to synchronize the video display.
Description
Technical field
The present invention relates to a kind of encoding and decoding technique of digital picture, the method and the device thereof of the audio video synchronization in especially a kind of video decoding system.
Background technology
In the MPEG Video transmission system, video that one or more is original and audio frequency and other data by compound be a single suitable data flow transmitted, be called audio frequency and video transport stream (TS stream).At first be packaged into primary flow packet (PES bag) for the ease of this compound, original video and voice data, a plurality of PES claddings are closed the back and are formed TS stream, and TS stream is suitable for long-distance transmissions.
Audio frequency and video need precise synchronization when showing, otherwise can influence the effect that the user watches.In Video transmission system, audio frequency and video be to be used by program clock reference (PCR) and audio frequency and video displaying timestamp (PTS) separately to realize synchronously.Explain the working mechanism of audio-visual synchronization below in conjunction with accompanying drawing.
As shown in Figure 1, be structure and the PCR and the position of PTS in code stream of audio frequency and video transport stream (TS stream), PCR is arranged in the adaptation field in TS packet header, and its effect is to keep decoder clocks and encoder clock precise synchronization; Introduced in the components of system as directed of MPEG-2 and to have utilized phase-locked loop (PLL) and from code stream, to analyze the PCR recovery system clock method obtain, as shown in Figure 2, PLL is poor with the PCR and the value of system clock counter of input, resulting difference through after the low-pass filtering as the input of voltage-controlled oscillator, voltage control oscillator is according to the speed of the value Adjustment System clock frequency of input, thereby realization decoder and encoder clock is synchronous; PTS is arranged in the packet header of audio frequency and video PES bag, it has stipulated the first frame audio frequency of beginning in this PES bag or the displaying time of video, and it is to be benchmark with the system clock that recovers from PCR.
As shown in Figure 3, be the correlation between program clock reference (PCR), system clock and the displaying timestamp (PTS).Transverse axis among the figure is a system clock time corresponding axle, and 1,2 and 3 is respectively the moment that different PCR arrives, and arrives this constantly at PCR, the value of PCR can be used for the recovery system clock and encoder-side synchronous; 4,5 and 6 is respectively the PTS of video or audio frequency correspondence, and the value of PTS has been determined it in the time shaft moment corresponding, and this is exactly the frame of video of this PTS correspondence or the time that audio frame must be showed constantly.
In the transport stream of reality, carry out the switching of program sometimes, replacement as commercial breaks or program, two programs before and after this switching may adopt different time references to encode, and will cause the discontinuity of PCR like this, and the discontinuous meeting of PCR mark in TS stream comes out.The components of system as directed regulation of MPEG-2, when the discontinuous situation of PCR took place, the PTS before this PCR was corresponding to the time reference before switching, and PTS afterwards is corresponding to new time reference.When the moment that discontinuous PCR arrives, may also not decode corresponding to the video of old time reference and finish or demonstration as yet, may cause the video of benchmark between the old times to show mistake if directly new PCR is applied to the recovery system clock, perhaps can't show at all, can influence the result of broadcast of video like this, and demand urgently further being improved.
Summary of the invention
Technical problem to be solved by this invention is to provide synchronous method and the device thereof of displaying in a kind of video decoding system, and when the discontinuous situation of program clock reference takes place, playing audio-video glibly still.
Technical problem to be solved by this invention is achieved by the following technical solution:
Keep the method for display synchronization in a kind of video decoding system, it may further comprise the steps:
Step 1, program clock reference processing unit extract program clock reference information from the audio frequency and video transport stream, show that the timestamp processing unit extracts the displaying timestamp information from the audio frequency and video transport stream;
Step 2, program clock reference processing unit are analyzed program clock reference information and are obtained the program clock reference value, and the program clock reference value is increased flag bit; Judge simultaneously whether program clock reference information is continuous:, forward step 4 to if program clock reference information is continuous; If program clock reference information is discontinuous, continue step 3; Show that simultaneously the timestamp processing unit will show that timestamp information increases flag bit;
Step 3, program clock reference processing unit are latched in program clock reference with discontinuous program clock reference value and latch in the counter, and begin to count, the flag bit that overturns simultaneously, and notice shows that the timestamp processing unit overturns to the flag bit of follow-up displaying timestamp; Wait for the feedback signal of display control module, forward step 7 to;
Step 4, program clock reference processing unit are sent to the program clock reference value in the phase-locked loop in real time, with the system clock counter jointly as the input of phase-locked loop, phase-locked loop is program clock reference value and system clock relatively, and its difference is used for the corrective system clock frequency returns to the system clock counter, simultaneously the flag bit of program clock reference value is passed to the system clock counter; Show that simultaneously the output of timestamp processing unit has the displaying timestamp information of flag bit to showing in the timestamp formation;
Step 5, the output of system clock counter have the system clock of flag bit and give display control unit; Show that simultaneously the timestamp formation will have the principle of the displaying timestamp information of flag bit by first in first out, sequential delivery is to display control unit;
Step 6, display control unit will show that the flag bit of timestamp information and the flag bit of system clock make comparisons, if identical, display control module then continues current data processing; If different, display control module is given the program clock reference processing unit with feedback information;
Step 7, program clock reference processing unit are received feedback signal, and the currency of program clock reference latch is loaded in the system clock counter;
Step 8, the output of system clock counter have the system clock of flag bit and give display control unit, make the video display synchronization.
In order to guarantee the displaying timestamp of the new and old time reference correspondence of differentiation that real control device can be correct, in showing timestamp and program clock reference, increased flag bit, this flag bit overturns automatically when the discontinuous incident of program clock reference takes place, when display control unit is found current displaying timestamp and system clock flag bit separately not simultaneously, then the discontinuous incident of program clock reference has taken place in explanation, the correct demonstration of the video of benchmark correspondence when between the old times, notice program clock reference processing unit loads new system clock.
The device that keeps display synchronization in a kind of video decoding system, it comprises the program clock reference processing unit, shows timestamp processing unit and display control unit;
Described program clock reference processing unit is connected with phase-locked loop, and the program clock reference message transmission that will extract from the audio frequency and video transport stream is to phase-locked loop; Described phase-locked loop is connected with the system clock counter, obtains system clock, analyzes the difference of itself and program clock reference value, according to this difference corrective system clock frequency, and passes the system clock counter back; Described system clock counter connects display control unit, and the system clock after will proofreading and correct passes to display control unit;
Described displaying timestamp processing unit is connected with shows the timestamp formation, and will be transferred to and show in the timestamp formation from the displaying timestamp information of audio frequency and video transport stream extraction; The formation of described displaying timestamp is connected with display control unit, will show that by the principle order of first in first out timestamp information is transferred to display control unit;
Be respectively equipped with the flag bit controller in described program clock reference processing unit and the displaying timestamp processing unit, described flag bit controller is with program clock reference information and show that timestamp information adds flag bit; Described program clock reference processing unit comprises that also program clock reference latchs counter, and this program clock reference latchs counter connected system clock counter; Described display control unit also connects the program clock reference processing unit, the flag bit of the displaying timestamp information that this display control unit is relatively received in real time and the flag bit of system clock, if the flag bit difference is given the program clock reference processing unit with feedback information.Described program clock reference processing unit is latched in program clock reference with discontinuous program clock reference value and latchs in the counter, and begin to count, the flag bit that overturns simultaneously, and notice shows that the timestamp processing unit overturns to the flag bit of follow-up displaying timestamp; When the program clock reference processing unit is received feedback signal, the currency of program clock reference latch is loaded in the system clock counter, system clock counter corrective system clock and output have the system clock of flag bit and give display control unit, make the video display synchronization.
The present invention can correctly show for the video that guarantees benchmark between the old times, in display control unit, provide feedback signal for the program clock reference processing unit, after the correct demonstration of the video of benchmark between the old times finished, notice program clock reference processing unit loaded new system clock.Make playback equipment when the discontinuous situation of program clock reference takes place, still playing audio-video glibly.When the discontinuous incident of program clock reference took place, old video flowing still can normal decoder and demonstration, made being stitched together that new, old video can be seamless; Data to be decoded such as need not to empty, also need not video decoder is resetted; Controlling mechanism is simple, and cost is low, is easy to realize.
Description of drawings
Fig. 1 is an audio frequency and video transport stream structure schematic diagram;
Fig. 2 is principle of PLL figure;
Fig. 3 is that system clock, program clock reference and displaying timestamp concern schematic diagram;
Fig. 4 is the schematic flow sheet of method embodiment of the present invention;
Fig. 5 is the structural representation of device embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is further specified:
As shown in Figure 4, be the schematic flow sheet of method embodiment of the present invention, it may further comprise the steps:
Step 1, program clock reference (PCR) processing unit extract program clock reference information from audio frequency and video transport stream (TS stream), show that timestamp (PTS) processing unit extracts the displaying timestamp information from audio frequency and video transport stream (TS stream);
Step 2, PCR processing unit are analyzed PCR information and are obtained the PCR reference value, and the PCR reference value is increased flag bit; Judge simultaneously whether PCR information is continuous:, forward step 4 to if PCR information is continuous; If PCR information is discontinuous, continue step 3; The PTS processing unit increases flag bit with PTS information simultaneously;
Step 3, PCR processing unit are latched in PCR with discontinuous PCR value and latch in the counter, and begin counting, the flag bit that overturns simultaneously, and notify the PTS processing unit that the flag bit of follow-up PTS is overturn; Wait for the feedback signal of display control module, forward step 7 to;
Step 4, PCR processing unit are sent to the PCR value in the phase-locked loop pll in real time, with the system clock counter jointly as the input of phase-locked loop pll, phase-locked loop pll is PCR value and system clock relatively, and its difference is used for the corrective system clock frequency returns to the system clock counter, simultaneously the flag bit of PCR is passed to the system clock counter; PTS processing unit output simultaneously has the PTS information of flag bit in the PTS formation;
Step 5, the output of system clock counter have the system clock of flag bit and give display control unit; PTS formation simultaneously will have the principle of the PTS information of flag bit by first in first out, and sequential delivery is to display control unit;
Show that wherein timestamp information by the read-write mode of the principle of first in first out is: it comprises a read pointer and a write pointer; Described read pointer provides the position that display control unit reads from formation, whenever read data, and the degree pointer moves once backward; Described write pointer provides the position of showing timestamp processing unit write queue, whenever writes data, and write pointer moves once backward.Or be that data directly write to the register of current pointer indication when the formation write data, and depth needle is added 1; During reading of data, read formation register foremost, the value of the register of back is composed successively to previous register, and queue depth is subtracted 1.
Step 6, display control unit are made comparisons the flag bit of PTS information and the flag bit of system clock, if identical, display control module then continues current data processing; If different, display control module is given the PCR processing unit with feedback information;
Step 7, PCR processing unit are received feedback signal, and the currency of PCR latch is loaded in the system clock counter;
Step 8, the output of system clock counter have the system clock of flag bit and give display control unit, make the video display synchronization.
For the video that guarantees benchmark between the old times can correctly show, in display control unit, provide feedback signal for program clock reference (PCR) processing unit, after the correct demonstration of the video of benchmark between the old times finished, notice program clock reference (PCR) processing unit loaded new system clock.
As shown in Figure 5, be the structural representation of device embodiment of the present invention, the inventive system comprises PCR processing unit, PTS processing unit and display control unit;
The PCR processing unit is connected with phase-locked loop pll, will flow the PCR message transmission of extraction to phase-locked loop pll from TS; Phase-locked loop pll is connected with the system clock counter, obtains system clock, analyzes the difference of itself and PCR value, according to this difference corrective system clock frequency, and passes the system clock counter back; The system clock counter connects display control unit, and the system clock after proofreading and correct is passed to display control unit;
The PTS processing unit is connected with the PTS formation, and will be transferred in the PTS formation from the PTS information of TS stream extraction; The PTS formation is a cyclic buffer, comprises a read pointer and a write pointer; Read pointer has provided the position that display control unit reads from formation, whenever read data, and read pointer moves once backward; Write pointer has provided the position of PTS processing unit write queue, whenever writes data, and write pointer moves once backward; The difference of write pointer and read pointer is represented the degree of depth of data in the formation; Perhaps the PTS formation is the first-in first-out register group, comprises queue depth's pointer; Queue depth's pointer has been pointed out current queue depth, and when needs during to the formation write data, data directly write to the register of current pointer indication, and this pointer is added 1; When reading of data, read formation register foremost, the value of the register of back is composed successively to previous register, and queue depth is subtracted 1; The PTS formation is connected with display control unit, and the principle order of pressing first in first out arrives display control unit with the PTS message transmission;
Be respectively equipped with the flag bit controller in PCR processing unit and the PTS processing unit, the flag bit controller adds flag bit with PCR information and PTS information; The PCR processing unit comprises that also PCR latchs counter, and this PCR latchs counter connected system clock counter; Display control unit also connects the PCR processing unit, and the flag bit of the PTS information that this display control unit is relatively received in real time and the flag bit of system clock are if the flag bit difference is given the PCR processing unit with feedback information.The PCR processing unit is latched in PCR with discontinuous PCR value and latchs in the counter, and begins counting, the flag bit that overturns simultaneously, and notify the PTS processing unit that the flag bit of follow-up PTS is overturn; When the PCR processing unit is received feedback signal, the currency of PCR latch is loaded in the system clock counter, system clock counter corrective system clock and output have the system clock of flag bit and give display control unit, make the video display synchronization.
The present invention can realize in the AVS decoding chip, has constituted the major part of this chip transmission process module.The PCR processing unit is the independently submodule of transmission process module, is responsible for parsing PCR in real time from the TS stream that receives, and guarantees that PCR uses constant delay from receiving; The PTS processing unit then lays respectively in voice data processing sub and the Video processing submodule, the audio, video data processing sub is responsible for analyzing the audio, video data bag, therefrom extract PTS information and audio frequency and video initial data, the audio frequency and video initial data that obtains is written to respectively in the audio frequency and video buffering area separately, and PTS information then outputs in the audio frequency and video PTS formation separately; Video decode is totally controlled by a CPU, and display control unit then is a submodule of CPU run time version, the demonstration that CPU dispatches each frame according to the PTS and the system clock of input; PLL and system clock counter bit are in the system clock generation module of decoding chip, and this module is responsible for the generation of the system clock of entire chip, and guarantee the system clock of decoding chip and the system clock precise synchronization of encoder.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1, keep the method for display synchronization in a kind of video decoding system, it is characterized in that it may further comprise the steps:
Step 1, program clock reference processing unit extract program clock reference information from the audio frequency and video transport stream, show that the timestamp processing unit extracts the displaying timestamp information from the audio frequency and video transport stream;
Step 2, program clock reference processing unit are analyzed program clock reference information and are obtained the program clock reference value, and the program clock reference value is increased flag bit; Judge simultaneously whether program clock reference information is continuous:, forward step 4 to if program clock reference information is continuous; If program clock reference information is discontinuous, continue step 3; Show that simultaneously the timestamp processing unit will show that timestamp information increases flag bit;
Step 3, program clock reference processing unit are latched in program clock reference with discontinuous program clock reference value and latch in the counter, and begin to count, the flag bit that overturns simultaneously, and notice shows that the timestamp processing unit overturns to the flag bit of follow-up displaying timestamp; Wait for the feedback signal of display control module, forward step 7 to;
Step 4, program clock reference processing unit are passed to the system clock counter with program clock reference value and flag bit thereof; Show that simultaneously the output of timestamp processing unit has the displaying timestamp information of flag bit to showing in the timestamp formation;
Step 5, the output of system clock counter have the system clock of flag bit and give display control unit; Show that simultaneously the displaying timestamp information that the timestamp formation will have a flag bit is transferred to display control unit;
Step 6, display control unit will show that the flag bit of timestamp information and the flag bit of system clock make comparisons, if identical, display control module then continues current data processing; If different, display control module is given the program clock reference processing unit with feedback information;
Step 7, program clock reference processing unit are received feedback signal, and the currency of program clock reference latch is loaded in the system clock counter;
Step 8, the output of system clock counter have the system clock of flag bit and give display control unit, make the video display synchronization.
2, the method that keeps display synchronization in the video decoding system according to claim 1, it is characterized in that: described step 4 is specially: the program clock reference processing unit is sent to the program clock reference value in the phase-locked loop in real time, with the system clock counter jointly as the input of phase-locked loop, phase-locked loop is program clock reference value and system clock relatively, and its difference is used for the corrective system clock frequency returns to the system clock counter, simultaneously the flag bit of program clock reference value is passed to the system clock counter; Show that simultaneously the output of timestamp processing unit has the displaying timestamp information of flag bit to showing in the timestamp formation.
3, keep the method for display synchronization in the video decoding system according to claim 1 and 2, it is characterized in that: described step 5 is specially: the output of system clock counter has the system clock of flag bit and gives display control unit; Show that simultaneously the timestamp formation will have flag bit, sequential delivery is to display control unit.
4, keep the method for display synchronization in the video decoding system according to claim 3, it is characterized in that: described displaying timestamp information by the read-write mode of the principle of first in first out is: it comprises a read pointer and a write pointer; Described read pointer provides the position that display control unit reads from formation, whenever read data, and the degree pointer moves once backward; Described write pointer provides the position of showing timestamp processing unit write queue, whenever writes data, and write pointer moves once backward.
5, the method that keeps display synchronization in the video decoding system according to claim 3, it is characterized in that: described displaying timestamp information by the read-write mode of the principle of first in first out is: when the formation write data, data directly write to the register of current pointer indication, and depth needle is added 1; During reading of data, read formation register foremost, the value of the register of back is composed successively to previous register, and queue depth is subtracted 1.
6, the device that keeps display synchronization in a kind of video decoding system, it comprises the program clock reference processing unit, shows timestamp processing unit and display control unit;
Described program clock reference processing unit is connected with the system clock counter, and the program clock reference message transmission that will extract from the audio frequency and video transport stream is to the system clock counter; Described system clock counter connects display control unit, and the system clock after will proofreading and correct passes to display control unit;
Described displaying timestamp processing unit is connected with shows the timestamp formation, and will be transferred to and show in the timestamp formation from the displaying timestamp information of audio frequency and video transport stream extraction; The formation of described displaying timestamp is connected with display control unit, will show that timestamp information is transferred to display control unit;
It is characterized in that: be respectively equipped with the flag bit controller in described program clock reference processing unit and the displaying timestamp processing unit, described flag bit controller is with program clock reference information and show that timestamp information adds flag bit; Flag bit controller in the described program clock reference processing unit is connected with showing the interior flag bit controller of timestamp processing unit, when the flag bit controller in program clock reference processing unit upset flag bit, notice is showed in the timestamp processing unit flag bit controller flag bit that overturns simultaneously;
Described program clock reference processing unit comprises that also program clock reference latchs counter, and this program clock reference latchs counter connected system clock counter; Described display control unit also connects the program clock reference processing unit, the flag bit of the displaying timestamp information that this display control unit is relatively received in real time and the flag bit of system clock, if the flag bit difference is given the program clock reference processing unit with feedback information.
7, the device that keeps display synchronization in the video decoding system according to claim 6, it is characterized in that: also be connected with phase-locked loop between described program clock reference processing unit and the system clock counter, the program clock reference message transmission that the program clock reference processing unit will extract from the audio frequency and video transport stream is to phase-locked loop; Described phase-locked loop obtains system clock, analyzes the difference of itself and program clock reference value, is used for the corrective system clock frequency, and returns to the system clock counter.
8, according to the device that keeps display synchronization in claim 6 or the 7 described video decoding systems, it is characterized in that: the formation of described displaying timestamp is a fifo queue.
9, keep the device of display synchronization in the video decoding system according to claim 8, it is characterized in that: the formation of described displaying timestamp is the first in first out cyclic buffer, and it comprises a read pointer and a write pointer; Described read pointer has provided the position that display control unit reads from formation, whenever read data, and the degree pointer moves once backward; Described write pointer has provided the position of showing timestamp processing unit write queue, whenever writes data, and write pointer moves once backward; The difference of described write pointer and read pointer is represented the degree of depth of data in the formation.
10, keep the device of display synchronization in the video decoding system according to claim 8, it is characterized in that: the formation of described displaying timestamp is the first-in first-out register group, and it comprises queue depth's pointer; This queue depth's pointer has been pointed out current queue depth, and when to the formation write data, data directly write to the register of current pointer indication, and this pointer is added 1; When reading of data, read formation register foremost, the value of the register of back is composed successively to previous register, and queue depth is subtracted 1.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426844C (en) * | 2005-05-23 | 2008-10-15 | 索尼株式会社 | Image processing apparatus, image capture apparatus and image processing method |
| CN101179718B (en) * | 2006-11-10 | 2010-06-16 | 上海奇码数字信息有限公司 | Code stream time base discontinuous processing method and code stream receiving apparatus |
| CN102075767A (en) * | 2010-11-29 | 2011-05-25 | 大连捷成实业发展有限公司 | Video and audio automatic synchronization processing method |
| CN101437150B (en) * | 2007-11-16 | 2011-11-09 | 华为技术有限公司 | Apparatus and method for providing association information |
| CN101901193B (en) * | 2009-05-27 | 2012-07-18 | 北京启明星辰信息技术股份有限公司 | Data buffer method and device |
| CN103269221A (en) * | 2013-04-23 | 2013-08-28 | 深圳雅图数字视频技术有限公司 | Play circuit and play system based on multiple players |
| CN111601180A (en) * | 2020-05-14 | 2020-08-28 | 上海济丽信息技术有限公司 | Distributed spliced large-screen video stream cluster synchronous display system based on PTS |
| US11146611B2 (en) | 2017-03-23 | 2021-10-12 | Huawei Technologies Co., Ltd. | Lip synchronization of audio and video signals for broadcast transmission |
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2004
- 2004-08-05 CN CN 200410070027 patent/CN1286314C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426844C (en) * | 2005-05-23 | 2008-10-15 | 索尼株式会社 | Image processing apparatus, image capture apparatus and image processing method |
| CN101179718B (en) * | 2006-11-10 | 2010-06-16 | 上海奇码数字信息有限公司 | Code stream time base discontinuous processing method and code stream receiving apparatus |
| CN101437150B (en) * | 2007-11-16 | 2011-11-09 | 华为技术有限公司 | Apparatus and method for providing association information |
| CN101901193B (en) * | 2009-05-27 | 2012-07-18 | 北京启明星辰信息技术股份有限公司 | Data buffer method and device |
| CN102075767A (en) * | 2010-11-29 | 2011-05-25 | 大连捷成实业发展有限公司 | Video and audio automatic synchronization processing method |
| CN102075767B (en) * | 2010-11-29 | 2012-12-12 | 大连捷成实业发展有限公司 | Video and audio automatic synchronization processing method |
| CN103269221A (en) * | 2013-04-23 | 2013-08-28 | 深圳雅图数字视频技术有限公司 | Play circuit and play system based on multiple players |
| US11146611B2 (en) | 2017-03-23 | 2021-10-12 | Huawei Technologies Co., Ltd. | Lip synchronization of audio and video signals for broadcast transmission |
| CN111601180A (en) * | 2020-05-14 | 2020-08-28 | 上海济丽信息技术有限公司 | Distributed spliced large-screen video stream cluster synchronous display system based on PTS |
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|---|---|
| CN1286314C (en) | 2006-11-22 |
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