CN111093335B

CN111093335B - Electronic equipment, circuit board and preparation method thereof

Info

Publication number: CN111093335B
Application number: CN201911330953.3A
Authority: CN
Inventors: 庞凤春; 李月; 曹雪
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Sensor Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Sensor Technology Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2022-03-01
Anticipated expiration: 2039-12-20
Also published as: US20210195738A1; CN111093335A

Abstract

The disclosure provides electronic equipment, a circuit board and a preparation method thereof, and belongs to the technical field of circuit boards. The preparation method of the circuit board comprises the following steps: providing a substrate base plate; forming a layer 1 circuit on one side of the substrate base plate; the 1 st circuit stacking operation to the Nth circuit stacking operation are sequentially performed. Wherein the nth circuit stacking operation comprises: forming an nth layer of dielectric layer on one side of the nth layer of circuit, which is far away from the substrate base plate, wherein the nth layer of dielectric layer is provided with at least one nth layer of through hole for exposing the nth layer of circuit; forming an n +1 layer of circuit on one side of the n layer of dielectric layer far away from the substrate base plate, wherein the n +1 layer of circuit is electrically connected with the n layer of circuit through the n layer of via hole; wherein N is a positive integer greater than 1; n is more than or equal to 1 and less than or equal to N, and N is an integer. The preparation method of the circuit board can improve the yield of the circuit board.

Description

Electronic equipment, circuit board and preparation method thereof

Technical Field

The present disclosure relates to the field of circuit board technologies, and in particular, to an electronic device, a circuit board, and a manufacturing method thereof.

Background

A Printed Circuit Board (PCB) is generally formed by pressing a copper clad laminate, and is a carrier and a connector of a plurality of electronic devices. Under the push of the factors such as the demand for the short, small and light PCB, the improvement of the chip integration level, the increase of the number of pins, and the introduction of advanced packaging, the HDI (High Density interconnect) type PCB is rapidly developed. HDI board replaces traditional PCB's through-hole with laser beam drilling, and the exposure machine of collocation higher accuracy realizes advancing line density by a wide margin.

However, the yield of high-end PCBs such as any-level HDI boards is very low, which is mainly limited by the conventional process, and each additional laser drilling step requires one more pressing step, and the expansion and contraction caused by the pressing step may lower the yield of the finished product.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides an electronic device, a circuit board and a method for manufacturing the same, which can improve the yield of the circuit board.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, there is provided a method of manufacturing a circuit board, including:

providing a substrate base plate;

forming a layer 1 circuit on one side of the substrate base plate;

sequentially performing a 1 st circuit stacking operation to an Nth circuit stacking operation, wherein the Nth circuit stacking operation comprises:

forming an nth layer of dielectric layer on one side of the nth layer of circuit, which is far away from the substrate base plate, wherein the nth layer of dielectric layer is provided with at least one nth layer of through hole for exposing the nth layer of circuit;

forming an n +1 layer of circuit on one side of the n layer of dielectric layer far away from the substrate base plate, wherein the n +1 layer of circuit is electrically connected with the n layer of circuit through the n layer of via hole;

wherein N is a positive integer greater than 1; n is more than or equal to 1 and less than or equal to N, and N is an integer.

In one exemplary embodiment of the present disclosure, forming the n +1 th layer circuit includes:

forming an n +1 th metal film layer on one side of the n-th dielectric layer far away from the substrate;

thickening the n +1 th metal film layer to a desired thickness by an electroplating process to obtain an n +1 th metal layer;

and patterning the n +1 th metal layer to obtain the n +1 th circuit.

In an exemplary embodiment of the present disclosure, the desired thickness is in a range of 10-20 microns.

In one exemplary embodiment of the present disclosure, forming the nth dielectric layer includes:

coating resin on the side of the nth layer of circuit, which is far away from the substrate base plate, and forming an nth layer of resin material layer;

and patterning the nth resin material layer to obtain an nth via hole exposing the nth circuit layer.

In an exemplary embodiment of the present disclosure, the resin is a resin for a photoresist;

patterning the nth resin material layer includes:

exposing an nth preset area of the nth resin material layer;

and developing to remove part or all of the resin in the preset region of the nth layer.

In an exemplary embodiment of the present disclosure, the method of manufacturing a circuit board further includes:

forming a base buffer layer on one side of the substrate base plate;

forming a layer 1 circuit on one side of the substrate includes:

and forming the layer 1 circuit on the surface of the base buffer layer, which is far away from the substrate base plate.

In one exemplary embodiment of the present disclosure, forming the nth dielectric layer further includes:

before the nth resin material layer is formed, forming an nth first buffer material layer on the side of the nth circuit far away from the substrate base plate;

the step of coating resin on the side of the nth layer of circuit far away from the substrate base plate comprises the following steps:

coating resin on the surface of the nth layer of the first buffer material layer away from the substrate base plate to form an nth layer of resin material layer;

after the patterning is performed on the nth resin material layer, the method for manufacturing the circuit board further comprises the following steps:

and patterning the nth layer of first buffer material layer to obtain an nth layer of via holes for exposing the nth layer of circuit.

after the nth resin material layer is formed, forming an nth second buffer material layer on the surface of the nth resin material layer away from the substrate;

before patterning the nth resin material layer, the method for manufacturing a circuit board further includes:

and patterning the nth second buffer material layer to expose a part to be patterned of the nth resin material layer.

In an exemplary embodiment of the present disclosure, before forming the layer 1 circuit, the method of manufacturing a circuit board further includes:

forming at least one connection hole on the substrate base plate;

filling the connecting hole with a conductive material;

forming a back side circuit on one side of the substrate base plate, and enabling the back side circuit and the layer 1 circuit to be respectively positioned on two sides of the substrate base plate which are oppositely arranged; the backside circuit is electrically connected with the conductive material in the connecting hole;

forming a layer 1 circuit on one side of the substrate includes:

and forming a layer 1 circuit on one side of the substrate base plate, wherein the layer 1 circuit is electrically connected with the conductive material in the connecting hole.

According to a second aspect of the present disclosure, there is provided a circuit board including a substrate base plate, a 1 st layer circuit, a 1 st stacked layer to an nth stacked layer, which are sequentially stacked, wherein the nth pair of layers includes:

the nth layer of dielectric layer is arranged on one side of the nth layer of circuit far away from the substrate; the nth layer of dielectric layer is provided with at least one nth layer of via hole for exposing the nth layer of circuit; wherein the material of the n-th dielectric layer comprises a resin for photoresist;

the n +1 layer of circuit is arranged on one side, far away from the substrate base plate, of the n layer of dielectric layer, and the n +1 layer of circuit is electrically connected with the n layer of circuit through the n layer of through hole;

In one exemplary embodiment of the present disclosure, the nth dielectric layer includes an nth resin layer, and further includes an nth first buffer layer and/or an nth second buffer layer; wherein,

the nth resin layer is arranged on one side of the nth circuit layer far away from the substrate base plate;

the nth layer of first buffer layer is arranged on one side, far away from the substrate base plate, of the nth layer of circuit and is arranged on the surface, close to the substrate base plate, of the nth layer of resin layer;

the nth layer of second buffer layer is arranged on the surface of the nth layer of resin layer far away from the substrate base plate.

In an exemplary embodiment of the present disclosure, the substrate base plate is provided with at least one connection hole, and the connection hole is filled with a conductive material;

the circuit board further includes:

and the back side circuit is arranged on one side of the substrate base plate, which is far away from the layer 1 circuit, and the back side circuit is electrically connected with the layer 1 circuit through the conductive material in the connecting hole.

According to a third aspect of the present disclosure, there is provided an electronic device including the circuit board described above.

According to the electronic device, the circuit board and the preparation method thereof provided by the disclosure, each layer of circuit and each layer of dielectric layer can be formed by stacking in sequence from the substrate in the preparation process, and further an N-level circuit board can be formed. Because each layer of circuit and each layer of dielectric layer are arranged on the same side of the substrate, the circuit board does not need to form each layer of circuit and each layer of dielectric layer on two sides of the substrate through pressing, thereby avoiding structural change caused by expansion and contraction of each layer of material and structure in the pressing process, and particularly avoiding internal short circuit, hole deviation, layer deviation and other defects caused by pressing.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of forming a layer 1 metal thin film layer according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of forming a layer 1 metal layer according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a structure for forming a layer 1 circuit according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural view of forming a layer 1 of resin material according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural view of forming a layer 1 resin layer according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of an N-stage circuit board according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a 7-stage circuit board according to an embodiment of the disclosure.

Fig. 8 is a schematic structural diagram of a 7-stage circuit board according to an embodiment of the disclosure.

Fig. 9 is a schematic structural diagram of a 7-step circuit board of a double-sided printing according to an embodiment of the disclosure.

Fig. 10 is a schematic flow chart of a method of manufacturing a circuit board according to an embodiment of the present disclosure.

The reference numerals of the main elements in the figures are explained as follows:

100. a substrate base plate; 101. a substrate buffer layer; 201. a layer 1 circuit; 2011. a 1 st metal film layer; 2012. a 1 st metal layer; 202. a layer 2 circuit; 203. a layer 3 circuit; 204. a layer 4 circuit; 205. a layer 5 circuit; 206. a layer 6 circuit; 207. a layer 7 circuit; 208. a layer 8 circuit; 301. a 1 st dielectric layer; 310. layer 1 of resin material; 3012. layer 1 resin layer; 302. a 2 nd dielectric layer; 303. a 3 rd dielectric layer; 304. a 4 th dielectric layer; 305. a 5 th dielectric layer; 306. a 6 th dielectric layer; 307. a 7 th dielectric layer; 400. a conductive material; 500. a backside circuit; 600. an electronic component; 700. a protective layer; 20n, nth layer circuit; 20(n +1), n +1 th layer circuit; 30n, an nth dielectric layer; 30n1, an nth layer of a first buffer layer; 30n2, nth resin layer; 30n3, an nth layer of second buffer layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

In an embodiment of the present disclosure, there is provided a method for manufacturing a circuit board, as shown in fig. 10, the method for manufacturing a circuit board includes:

step S110, as shown in fig. 3, providing a substrate base plate 100;

step S120, as shown in fig. 3, forming a layer 1 circuit 201 on one side of the substrate 100;

step S130, as shown in fig. 4 to 6, sequentially performing the 1 st circuit stacking operation to the nth circuit stacking operation, wherein the nth circuit stacking operation includes:

step S210n, forming an nth layer of dielectric layer 30n on a side of the nth layer of circuit 20n away from the substrate 100, wherein the nth layer of dielectric layer 30n is provided with at least one nth layer of via hole exposing the nth layer of circuit 20 n;

step S220n, forming an n +1 th layer of circuit 20(n +1) on the side of the n-th layer of dielectric layer 30n away from the substrate 100, and electrically connecting the n +1 th layer of circuit 20(n +1) with the n-th layer of circuit 20n through the n-th layer of via hole;

According to the method for manufacturing the circuit board provided by the present disclosure, each layer of circuit and each layer of dielectric layer can be sequentially stacked from the substrate 100 in the manufacturing process, and thus an N-level circuit board can be formed. Because each layer of circuit and each layer of dielectric layer are arranged on the same side of the substrate base plate 100, each layer of circuit and each layer of dielectric layer are not required to be formed on two sides of the substrate base plate 100 through pressing, structural change caused by expansion and contraction of each layer of material and structure in the pressing process is avoided, and particularly, the defects of internal short circuit, hole deviation, layer deviation and the like caused by pressing are avoided.

Further, the present disclosure provides a method for manufacturing a circuit board, which is suitable for a semiconductor process, such as a TFT (thin film transistor) -LCD (liquid crystal display) process. In the TFT-LCD process, each film layer is sequentially formed on the substrate 100, and a via hole penetrating through the dielectric layer can be formed through a patterning process to connect two adjacent layers of circuits, so that a circuit structure of any step can be formed naturally without a significant increase in cost compared to an HDI board. Moreover, the TFT-LCD technology can realize more accurate alignment, has small alignment deviation, for example, the alignment deviation is generally not more than 1.5 microns, can reduce the size of the via hole of the circuit board, reduce the line width of the circuit lead, reduce the space of the circuit lead, and further improve the interconnection density of the circuit board.

The following describes in detail the steps of the method for manufacturing a circuit board according to the embodiments of the present disclosure with reference to the accompanying drawings:

in step S110, the substrate 100 provided may be an inorganic substrate 100 or an organic substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass. In another embodiment of the present disclosure, the material of the substrate 100 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate 100 may also be a flexible substrate 100, for example, the material of the substrate 100 may be Polyimide (PI).

It is understood that, when the substrate base plate 100 is provided as the flexible substrate base plate 100, the prepared circuit board may be a flexible circuit board.

In step S120, a layer 1 circuit 201 may be formed on one side of the substrate base plate 100 by means of a photolithography process. For example, as shown in fig. 2, a layer 1 metal layer 2012 may be formed on one side of the substrate 100, and then the layer 1 metal layer 2012 may be patterned.

The thickness of the layer 1 metal layer 2012 can be determined according to the design requirements of the circuit board, and may be hundreds of nanometers, several micrometers, or 10 to 20 micrometers. The stricter the impedance requirement of the circuit board to the circuit to be prepared, the larger the size of the circuit board, the larger the required working current and working voltage, and the like, the larger the thickness of the layer 1 metal layer 2012 can be, so that the larger the thickness of the trace of the layer 1 circuit 201 is, the smaller the square resistance is.

The 1 st metal layer 2012 with a small thickness, for example, the 1 st metal layer 2012 with a thickness of several hundred nanometers, or the 1 st metal layer 2012 with a thickness of about 1 micrometer, may be formed by a sputtering process. That is, on the premise of satisfying the requirement of the layer 1 circuit 201, a thin layer 1 metal film can be formed as the layer 1 metal layer 2012 by sputtering.

For the 1 st metal layer with a thicker thickness, as shown in fig. 1, a sputtering method may be first adopted to form a thinner 1 st metal thin film layer 2011, for example, a metal thin film layer with a thickness not greater than 1 micron is formed, and then the 1 st metal thin film layer 2011 is used as a seed layer to perform electroplating, so that the 1 st metal thin film layer 2011 is thickened to a desired thickness, for example, to 10 to 20 microns, to obtain a required 1 st metal layer 2012.

The layer 1 metal layer 2012 may be patterned by:

step S310, forming a 1 st photoresist layer on a side of the 1 st metal layer 2012 away from the substrate 100;

step S320, exposing and developing the 1 st photoresist layer to expose a portion of the 1 st metal layer 2012 to be removed;

step S330, etching the exposed portion of the metal layer 2012 in the layer 1, so as to implement patterning of the metal layer 2012 in the layer 1, and obtain the required circuit 201 in the layer 1;

step S340, removing the remaining first photoresist layer.

The material of layer 1 metal layer 2012 may be platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or combinations thereof. For example, in one embodiment of the present disclosure, the material of the layer 1 metal layer 2012 may be copper.

Alternatively, as shown in fig. 1, the method of manufacturing a circuit board may further include forming a base buffer layer 101 on one side of the base substrate 100. In step S120, the layer 1 circuit 201 is formed on the surface of the base buffer layer 101 away from the base substrate 100. Thus, the base buffer layer 101 is formed on the layer 1 circuit 201 and the substrate base plate 100, and the base buffer layer 101 can provide a flattened surface for the layer 1 metal layer 2012 and the layer 1 circuit 201, and can enhance the adhesion between the layer 1 metal layer 2012 and the layer 1 circuit 201 and the substrate base plate 100, thereby improving the reliability and reliability of the prepared circuit board.

Alternatively, the material of the substrate buffer layer 101 may be an inorganic material, and for example, may be an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Optionally, the thickness of the substrate buffer layer 101 may be 1 to 10 micrometers.

In one embodiment of the present disclosure, the substrate buffer layer 101 may be formed by a deposition method, for example, a silicon nitride layer may be formed by a PECVD (plasma enhanced chemical vapor deposition) method as the substrate buffer layer 101.

In step S130, as shown in FIGS. 4 to 7, the circuit stacking operation from the 1 st to the Nth times can be sequentially performed to sequentially form a layer 1 dielectric layer 301, a layer 2 circuit 202, a layer 2 dielectric layer, a layer 3 circuit 203, a layer 3 dielectric layer 303. cndot. N dielectric layer 30N, and an N +1 layer circuit 20(N +1) on the side of the layer 1 circuit 201 away from the substrate 100 until an N +1 layer circuit is formed. Thus, a circuit board of N +1 layer circuit can be formed.

Wherein any number of circuit stacking operations includes a dielectric layer forming operation and a circuit forming operation performed in sequence. In other words, the nth circuit stacking operation includes:

in step S220n, an n +1 th layer circuit 20(n +1) is formed on the n-th layer dielectric layer 30n on the side away from the base substrate 100, and the n +1 th layer circuit 20(n +1) is electrically connected to the n-th layer circuit 20n through the n-th layer via hole.

For example, the 1 st circuit stacking operation includes:

step S2101, forming a 1 st dielectric layer 301 on the 1 st layer circuit 201 side far away from the substrate 100, wherein the 1 st dielectric layer 301 is provided with at least one 1 st layer via hole exposing the 1 st layer circuit 201;

in step S2201, a layer 2 circuit 202 is formed on the side of the layer 1 dielectric layer 301 away from the substrate 100, and the layer 2 circuit 202 is electrically connected to the layer 1 circuit 201 through the layer 1 via.

As another example, the 7 th circuit stacking operation includes:

step S2107, forming a 7 th dielectric layer 307 on the 7 th layer of circuit 207 on the side away from the substrate 100, wherein the 7 th dielectric layer is provided with at least one 7 th layer via hole exposing the 7 th layer of circuit 207;

in step S2207, a layer 8 circuit 208 is formed on the side of the layer 7 dielectric layer 307 away from the substrate 100, and the layer 8 circuit 208 is electrically connected to the layer 7 circuit 207 through the layer 7 via.

Thus, by means of the preparation method of the circuit board provided by the present disclosure, the circuit and the dielectric layer can be sequentially stacked from the substrate to finally form the required circuit board. For example, as shown in fig. 7, when N is 7, the formed circuit board may include a substrate 100, a base buffer layer 101, a layer 1 circuit 201, a layer 1 dielectric layer 301, a layer 2 circuit 202, a layer 2 dielectric layer 302, a layer 3 circuit 203, a layer 3 dielectric layer 303, a layer 4 circuit 204, a layer 4 dielectric layer 304, a layer 5 circuit 205, a layer 5 dielectric layer 305, a layer 6 circuit 206, a layer 6 dielectric layer 306, a layer 7 circuit 207, a layer 7 dielectric layer 307, and a layer 8 circuit 208, which are sequentially stacked.

In step S210n, the required nth dielectric layer 30n may be formed by:

step S410n, applying resin on the side of the nth layer circuit 20n away from the substrate 100 to form an nth layer resin material layer;

in step S420n, the nth resin material layer is patterned to obtain an nth via hole exposing the nth circuit 20n, and the remaining nth resin material layer is used as the nth resin layer 30n2 of the circuit board.

Therefore, in the preparation method of the circuit board, the dielectric layer can be formed without a pressing method, the deformation and displacement of the circuit lead caused in the pressing process are avoided, the alignment precision in the preparation process of the circuit board is improved, the interconnection density of the circuit board is improved, and the yield of the circuit board is improved.

Alternatively, in step S410n, the applied resin may be a resin for a photoresist, for example, a polyimide resin (PI). As such, the nth resin material layer may be patterned by means of a photolithography process. For example, the predetermined region of the nth resin material layer may be exposed; and then developed to remove part or all of the resin in the predetermined region of the nth layer, resulting in the nth layer resin layer 30n 2. It is to be understood that the nth resin layer 30n2 is formed with an nth via hole in an nth predetermined region to expose the nth layer of circuitry 20 n.

For example, as shown in fig. 4, the layer 1 resin material layer 310 may be formed on the side of the layer 1 circuit 201 away from the substrate 100, and then the layer 1 resin material layer 310 may be patterned to obtain the layer 1 resin layer 3012.

In this embodiment, since the nth resin material layer can be patterned by means of a photolithography process without using a laser drilling process, higher alignment accuracy and smaller via hole size can be achieved, thereby achieving higher density interconnection. Particularly, the circuit board preparation method can realize higher-precision alignment by means of a TFT-LCD process.

Alternatively, in order to improve the adhesion between the nth resin material layer and the nth circuit 20n, in step S210n, before step S410n, an nth first buffer material layer may be further formed on the nth circuit 20n on the side away from the base substrate 100; then in step S410n, a resin may be applied to the surface of the nth layer of the first buffer material layer away from the base substrate 100 to form an nth layer of resin material layer; after step S420n, the nth layer of the first buffer material layer may also be patterned to obtain an nth layer of vias exposing the nth layer of circuitry 20n, forming an nth layer of the first buffer layer 30n 1.

In other words, in step S210n, the nth dielectric layer 30n may be formed by: sequentially forming an nth first buffer material layer and an nth resin material layer which are stacked on one side of the nth circuit 20n away from the substrate 100; the nth resin material layer and the nth first buffer material layer are patterned in this order, and as shown in fig. 6, the nth first buffer layer 30n1 and the nth resin layer 30n2 are obtained as being sequentially stacked on the side of the nth circuit 20n remote from the base substrate 100.

As such, as shown in fig. 6, the n-th dielectric layer 30n is formed to include the n-th first buffer layer 30n1 and the n-th resin layer 30n2 laminated in this order on the side of the n-th circuit 20n away from the substrate board 100, and the n-th via hole penetrates the n-th first buffer layer 30n1 and the n-th resin layer 30n2 to expose the n-th circuit 20 n.

The material of the n-th first buffer material layer may be an inorganic material, for example, an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Optionally, the thickness of the nth first buffer material layer may be 1-10 micrometers. In one embodiment of the present disclosure, the material of the nth layer of the first buffer material layer is the same as the material of the base buffer layer 101.

In one embodiment of the present disclosure, the nth first buffer material layer may be formed by a deposition method, for example, a silicon nitride layer may be formed by a PECVD (plasma enhanced chemical vapor deposition) method as the nth first buffer material layer.

Alternatively, in order to improve the adhesion between the nth resin material layer and the (n +1) th layer of circuit 20(n +1), in step S210n, after step S410n, an nth second buffer material layer is formed on the surface of the nth resin material layer away from the base substrate 100; before the step S410n, the nth layer of second buffer material layer is also patterned to expose the portion of the nth layer of resin material layer to be patterned, as shown in fig. 6, forming an nth layer of second buffer layer 30n 2.

In other words, in step S210n, the nth dielectric layer 30n may be formed by: sequentially forming an nth resin material layer and an nth second buffer material layer on the side of the nth circuit 20n away from the substrate 100; the nth layer of the second buffer material layer and the nth layer of the resin material layer are sequentially patterned to obtain an nth layer of the resin layer 30n2 and an nth layer of the second buffer layer 30n2 sequentially stacked on the nth layer of the circuit 20n on the side away from the base substrate 100.

As such, as shown in fig. 6, the n-th dielectric layer 30n is formed to include an n-th resin layer 30n2 and an n-th second buffer layer 30n2 laminated in this order on the side of the n-th circuit 20n away from the substrate board 100, and an n-th via hole penetrates the n-th resin layer 30n2 and the n-th second buffer layer 30n2 to expose the n-th circuit 20 n.

The material of the nth layer of the second buffer material layer may be an inorganic material, for example, an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Optionally, the thickness of the nth second buffer material layer may be 1-10 micrometers. In one embodiment of the present disclosure, the material of the nth layer of the second buffer material layer is the same as the material of the base buffer layer 101.

In one embodiment of the present disclosure, the nth second buffer material layer may be formed by a deposition method, for example, a silicon nitride layer may be formed by a PECVD (plasma enhanced chemical vapor deposition) method as the nth second buffer material layer.

Of course, as shown in fig. 6, in the method of manufacturing the circuit board of the present disclosure, the nth dielectric layer 30n composed of the nth first buffer layer 30n1, the nth resin layer 30n2, and the nth second buffer layer 30n2, which are sequentially stacked, may also be prepared. For example, an nth first buffer material layer, an nth resin material layer, and an nth second buffer material layer may be sequentially formed on a side of the nth circuit 20n away from the substrate 100, and then the nth second buffer material layer, the nth resin material layer, and the nth first buffer material layer may be sequentially patterned to prepare the nth dielectric layer 30 n.

In step S220n, an n +1 th layer of circuitry 20(n +1) may be formed on the nth layer of dielectric layer 30n on a side away from the base substrate 100, and the n +1 th layer of circuitry 20(n +1) is electrically connected to the nth layer of circuitry 20n through the nth layer of vias. Among them, the method used for preparing the (n +1) th layer circuit 20(n +1) may be the same as the method for preparing the 1 st layer circuit 201. For example, an n +1 th metal thin film layer may be formed on the side of the nth dielectric layer 30n away from the substrate 100; then, thickening the (n +1) th metal film layer to a desired thickness by an electroplating process to obtain an (n +1) th metal layer; thereafter, the patterning operation is performed on the (n +1) th metal layer, so as to obtain the (n +1) th circuit 20. Further, the desired thickness is in the range of 10 to 20 microns.

Further, an anisotropic plating solution may be used to perform electroplating, so that the thickening speed of the (n +1) th metal film layer portion in the nth via hole is fast, and the thickening speed of the (n +1) th metal film layer portion on the nth dielectric layer 30n is slow, so that the nth metal layer can fill or substantially fill the nth via hole.

In order to prepare the circuit board for double-sided printing, as shown in fig. 8 and 9, the method for preparing a circuit board of the present disclosure may further include:

step S510, before step S120, forming at least one connection hole on the substrate base plate 100;

step S520, filling the connection hole with a conductive material 400;

step S530, forming a backside circuit 500 on one side of the base substrate 100, and enabling the backside circuit 500 and the layer 1 circuit 201 to be respectively located on two sides of the base substrate 100; the backside circuit 500 is electrically connected to the conductive material 400 in the connection hole.

In step S120, the layer 1 circuit 201 is formed on one side of the base substrate 100, and the layer 1 circuit 201 is electrically connected to the conductive material 400 in the connection hole.

In this manner, the resulting circuit board has a backside circuit 500 electrically connected to layer 1 circuitry 201. When double-sided printing is required, the electronic component 600 may be connected to the (N +1) th layer of circuitry 20(N +1) and the backside circuitry 500 to achieve double-sided printing.

In step S510, a mechanical punching, an etching punching, a laser punching, or other punching method may be used to form a desired connection hole on the substrate 100. For example, a glass punching technique may be used to form the desired connection holes in the glass substrate.

In step S520, the connection holes may be filled with metal as the conductive material 400, for example, the connection holes may be filled with copper as the conductive material 400, so as to electrically connect the layer 1 circuit 201 and the backside circuit 500.

In step 530, the backside circuitry 500 may be formed using the same or similar method as that used to form the layer 1 circuitry 201. For example, a backside metal material layer may be formed on the substrate 100 at a side where the backside circuit 500 is to be formed, and then the backside circuit 500 may be formed by patterning the backside metal material layer. The material and thickness of the backside circuit 500 may be the same as or different from those of the layer 1 circuit 201, and the disclosure is not limited thereto.

It is understood that step 530 may be executed first, and then step S120 may be executed; or step 530 may be executed after S120 is executed; each process in step 530 and each process in step 120 may also be performed simultaneously or alternately, and the disclosure is not limited thereto.

The circuit board manufacturing method of the present disclosure, as shown in fig. 7, may further include forming a protective layer 700 on a side of the N +1 th layer of circuit 20(N +1) away from the substrate base plate 100, for example, coating a liquid photo solder resist on a side of the N +1 th layer of circuit 20(N +1) away from the substrate base plate 100. Further, the required electronic components 600 may be connected to the N +1 th layer circuit 20(N + 1).

When the circuit board prepared by the present disclosure further includes the backside circuit 500, the method for preparing a circuit board of the present disclosure may further include forming a protective layer 700 on a side of the backside circuit 500 away from the substrate base plate 100, for example, coating a liquid photo solder resist on a side of the backside circuit 500 away from the substrate base plate 100. Further, the required electronic components 600 can be connected to the backside circuit 500 to realize double-sided printing of the circuit board.

The disclosed embodiment further provides a circuit board, as shown in fig. 6, including a substrate base plate 100, a 1

st layer circuit

201, and 1 st to nth layer stacked layers, which are sequentially stacked, wherein the nth layer pair stacked layer includes an nth layer dielectric layer 30N and an N +1 th layer circuit 20(N + 1);

the nth dielectric layer 30n is provided on the nth circuit 20n on the side away from the base substrate 100; the nth layer of dielectric layer 30n is provided with at least one nth layer of via exposing the nth layer of circuitry 20 n; wherein the material of the n-th dielectric layer 30n includes a resin for photoresist;

the (n +1) th layer circuit 20(n +1) is arranged on the side of the n-th layer dielectric layer 30n far away from the substrate 100, and the (n +1) th layer circuit 20(n +1) is electrically connected with the n-th layer circuit 20n through the n-th layer via hole;

The circuit board provided by the present disclosure may be prepared by using the circuit board preparation method provided in the above circuit board preparation method embodiment, and specific details, principles, and effects of the circuit board preparation method embodiment are described and introduced in detail, which are not described herein again. Particularly, the circuit board provided by the disclosure can be prepared without adopting a pressing process, particularly by adopting a TFT-LCD process, so that the preparation yield is high, higher alignment precision, higher wiring density and higher interconnection density can be realized more easily, the area of the circuit board is reduced more easily, and the electrical performance of the circuit board is improved.

Preferably, as shown in fig. 6, the nth dielectric layer 30n includes an nth resin layer 30n2, and further includes an nth first buffer layer 30n1 and/or an nth second buffer layer 30n 2; wherein,

the nth resin layer 30n2 is provided on the side of the nth circuit 20n away from the base substrate 100;

the nth layer of the first buffer layer 30n1 is arranged on the side of the nth layer of the circuit 20n far away from the substrate 100, and is arranged on the surface of the nth layer of the resin layer 30n2 close to the substrate 100;

the nth layer of the second buffer layer 30n2 is disposed on the surface of the nth layer of the resin layer 30n2 away from the substrate 100.

Preferably, as shown in fig. 9, the substrate base plate 100 is provided with at least one connection hole, and the connection hole is filled with a conductive material 400; the circuit board further includes a backside circuit 500, the backside circuit 500 is disposed on a side of the substrate base plate 100 away from the layer 1 circuit 201, and the backside circuit 500 and the layer 1 circuit 201 are electrically connected through the conductive material 400 in the connection hole. Thus, the circuit board can be used for double-sided printing.

The embodiment of the present disclosure also provides an electronic device, which includes any one of the circuit boards described in the above circuit board embodiments. The electronic device may be a smartphone, laptop, wearable device, or other type of electronic device. Since the electronic device has any one of the circuit boards described in the above embodiments of the circuit board, the electronic device has the same beneficial effects, and the details of the disclosure are not repeated herein.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims

1. A method for manufacturing a circuit board, comprising:

providing a substrate base plate;

forming a layer 1 circuit on one side of the substrate base plate;

wherein N is a positive integer greater than 1; n is more than or equal to 1 and less than or equal to N, and N is an integer;

wherein forming the n-th dielectric layer includes:

forming an nth layer of first buffer material layer on one side of the nth layer of circuit, which is far away from the substrate base plate, by adopting a plasma enhanced chemical vapor deposition method; the material of the first buffer material layer is an inorganic material; coating resin on the surface, away from the substrate, of the nth first buffer material layer to form an nth resin material layer; patterning the nth layer of the first buffer material layer after patterning the nth layer of the resin material layer to obtain an nth layer of via holes exposing the nth layer of circuitry; and/or the presence of a gas in the gas,

coating resin on one side of the nth layer of circuit, which is far away from the substrate base plate, so as to form an nth layer of resin material layer; forming an nth layer of second buffer material layer on the surface of the nth layer of resin material layer far away from the substrate by adopting a plasma enhanced chemical vapor deposition method; the material of the first buffer material layer is an inorganic material; patterning the nth second buffer material layer to expose a part to be patterned of the nth resin material layer; patterning the nth layer of resin material layer to obtain an nth layer of via hole exposing the nth layer of circuit;

wherein the thickness of the nth first buffer material layer is within the range of 1-10 microns; the thickness of the nth second buffer material layer is within the range of 1-10 microns;

wherein forming the n +1 th layer of circuitry comprises:

thickening the n +1 th metal film layer to a desired thickness by an electroplating process to obtain an n +1 th metal layer; the expected thickness is within the range of 10-20 microns;

and patterning the n +1 th metal layer to obtain the n +1 th circuit.

2. The method for manufacturing a circuit board according to claim 1, wherein the resin is a resin for a photoresist;

patterning the nth resin material layer includes:

exposing an nth preset area of the nth resin material layer;

3. The method for manufacturing a circuit board according to claim 1, further comprising:

forming a base buffer layer on one side of the substrate base plate;

forming a layer 1 circuit on one side of the substrate includes:

4. The method for manufacturing a circuit board according to claim 1, wherein before the forming of the layer 1 circuit, the method for manufacturing a circuit board further comprises:

forming at least one connection hole on the substrate base plate;

filling the connecting hole with a conductive material;

forming a layer 1 circuit on one side of the substrate includes:

5. The circuit board is characterized by comprising a substrate base plate, a 1 st layer of circuit, a 1 st layer of stacked layer and an Nth layer of stacked layer which are sequentially stacked, wherein the Nth layer comprises the following stacked layers:

the nth dielectric layer comprises an nth resin layer and further comprises an nth first buffer layer and/or an nth second buffer layer; wherein,

the nth layer of first buffer layer is arranged on one side, far away from the substrate base plate, of the nth layer of circuit and is arranged on the surface, close to the substrate base plate, of the nth layer of resin layer; the nth layer of the first buffer layer is made of inorganic materials; the thickness of the nth layer of the first buffer layer is within the range of 1-10 microns;

the nth layer of second buffer layer is arranged on the surface, away from the substrate base plate, of the nth layer of resin layer; the nth layer of second buffer layer is made of inorganic materials; the thickness of the nth layer of second buffer layer is within the range of 1-10 microns;

the n +1 th layer of circuit is formed by patterning a metal layer formed by electroplating, and the thickness of the circuit is within the range of 10-20 microns.

6. The circuit board of claim 5, wherein the substrate base plate is provided with at least one connection hole, and the connection hole is filled with a conductive material;

the circuit board further includes:

7. An electronic device comprising the circuit board according to any one of claims 5 to 6.