CN111092050A - Metal interconnection structure and manufacturing method thereof - Google Patents
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
The invention provides a metal interconnection structure and a manufacturing method thereof, wherein the metal interconnection structure comprises the following steps: forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening; the first barrier layer is wrapped with residue at the bottom of the opening. And removing the first barrier layer at the bottom of the opening to remove residues. And forming a second barrier layer, wherein the second barrier layer at least covers the bottom of the opening and the first barrier layer. And forming a second metal layer in the opening. And a second barrier layer is formed between the second metal layer and the first metal layer, and the first metal layer and the second metal layer are electrically connected through the second barrier layer. The second barrier layer has strong diffusion prevention capability, and can effectively prevent the mutual diffusion of the first metal layer and the second metal layer from forming metal alloy, so that the electromagnetic compatibility (EMC) performance of a semiconductor device made of the metal interconnection structure is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a metal interconnection structure and a manufacturing method thereof.
Background
A metal interconnection structure is an indispensable structure of a semiconductor device. In a semiconductor manufacturing process, the quality of the metal interconnect structure formed has a large impact on the performance of the semiconductor device.
With the continuous progress of the super-large scale integrated circuit technology, the feature size of the semiconductor device is continuously reduced, and the performance of the semiconductor device is stronger and stronger. However, as semiconductor dimensions continue to shrink, smaller and smaller interconnect structures carry higher and higher currents, and the response time requirements of the interconnect structures become shorter and shorter, which conventional aluminum interconnect structures have been unable to meet. Therefore, new material interconnection structures, such as copper-aluminum interconnection (Cu/Al), tungsten-copper interconnection (W/Cu), tungsten-aluminum interconnection (W/Al) and the like, are continuously developed.
However, new interconnect structures are not perfect and various problems are unavoidable. For example: in the copper-aluminum interconnection process, because metal copper and aluminum have strong activity, copper and aluminum can diffuse mutually after the copper-aluminum interconnection process is completed, in the subsequent high-temperature process, copper-aluminum alloy can be formed by the mutual diffusion of the copper and the aluminum, namely, a large amount of copper-aluminum alloy is formed at the part of the copper close to the aluminum, and the copper-aluminum alloy is also formed at the part of the aluminum close to the copper, so that the Radiation Emission (RE) test of a semiconductor device manufactured by the copper-aluminum interconnection structure does not reach the standard, the Radiation Emission (RE) is an interference-related sub-project in an electromagnetic compatibility (EMC) test project, and the electromagnetic compatibility (EMC) test fails.
Disclosure of Invention
The invention aims to provide a metal interconnection structure and a manufacturing method thereof, which can prevent metal layers of interconnection from inter-diffusing to form metal alloy, thereby improving the electromagnetic compatibility (EMC) performance of a semiconductor device made of the metal interconnection structure.
The invention provides a metal interconnection structure and a manufacturing method thereof, wherein the metal interconnection structure comprises the following steps:
providing a substrate, and forming a dielectric layer and a first metal layer on the substrate, wherein the dielectric layer surrounds the first metal layer; etching the dielectric layer to form an opening exposing the first metal layer;
forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening;
removing the first barrier layer at the bottom of the opening and exposing the first metal layer; and the number of the first and second groups,
forming a second barrier layer at least covering the first metal layer and the first barrier layer exposed by the opening;
and forming a second metal layer in the opening.
Further, the first barrier layer is TaN or TiN.
Further, a magnetron sputtering method is adopted as a method for forming the first barrier layer, and the specific parameters include: the power range of the bias power supply is 700W-900W, the flow rate of nitrogen is 21 sccm-26 sccm, and the thickness of the first barrier layer is 250 angstroms-350 angstroms.
Further, the first blocking layer at the bottom of the opening is removed, and a magnetron sputtering method is adopted, including: and bombarding and removing the first barrier layer at the bottom of the open pore by argon plasma sputtering under the condition that the power range of the bias power supply is 900-1200W, wherein impurities are generated in the bombardment process, and part of the impurities are adsorbed on the side wall of the open pore.
Further, the second barrier layer also covers the impurities adsorbed on the side wall of the opening.
Further, the second barrier layer is TaN or TiN.
Further, a magnetron sputtering method is adopted as a method for forming the second barrier layer, and the specific parameters include: the power range of the bias power supply is 700W-900W, the flow rate of nitrogen is 21 sccm-26 sccm, and the thickness of the second barrier layer is 200 angstroms-300 angstroms.
Furthermore, the material of the first metal layer comprises aluminum, and the material of the second metal layer comprises copper.
The present invention also provides a metal interconnect structure comprising:
the device comprises a substrate, a dielectric layer and a first metal layer, wherein the dielectric layer and the first metal layer are positioned on the substrate, and the dielectric layer surrounds the first metal layer;
the opening is formed in the dielectric layer to expose the first metal layer;
a first barrier layer covering sidewalls of the opening;
a second barrier layer covering the first metal layer and the first barrier layer exposed by the opening; and the number of the first and second groups,
and the second metal layer is positioned in the opening.
Furthermore, the material of the first metal layer comprises aluminum, and the material of the second metal layer comprises copper.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a metal interconnection structure and a manufacturing method thereof, wherein the metal interconnection structure comprises the following steps: forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening; the first barrier layer wraps the residue at the bottom of the opening. And removing the first barrier layer at the bottom of the opening to remove residues. And forming a second barrier layer, wherein the second barrier layer at least covers the bottom of the opening and the first barrier layer. And forming a second metal layer in the opening. And a second barrier layer is formed between the second metal layer and the first metal layer, and the first metal layer and the second metal layer are electrically connected through the second barrier layer. The second barrier layer can effectively prevent the first metal layer and the second metal layer from mutually diffusing to form metal alloy, so that the electromagnetic compatibility (EMC) performance of the semiconductor device containing the metal interconnection structure is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a metal interconnection structure according to an embodiment of the present invention.
Fig. 2 to 6 are schematic diagrams illustrating steps of a method for fabricating a metal interconnection structure according to an embodiment of the invention.
Wherein the reference numbers are as follows:
10-a substrate; 11-a dielectric layer; 11 a-a first dielectric layer; 11 b-a second dielectric layer; 12-a first metal layer; 13-a hard mask layer; 14-an anti-reflection layer; 15-an insulating layer; 21-a first barrier layer; 22-a second barrier layer; 31-residue; 32-impurities; 40-opening holes; 50-second metal layer.
Detailed Description
Based on the above research, the embodiment of the invention provides a metal interconnection structure and a manufacturing method thereof. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
The embodiment of the invention provides a manufacturing method of a metal interconnection structure, as shown in fig. 1, the method comprises the following steps:
providing a substrate, and forming a dielectric layer and a first metal layer on the substrate, wherein the dielectric layer surrounds the first metal layer; etching the dielectric layer to form an opening exposing the first metal layer;
forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening;
removing the first barrier layer at the bottom of the opening and exposing the first metal layer; and the number of the first and second groups,
forming a second barrier layer at least covering the first metal layer and the first barrier layer exposed by the opening;
and forming a second metal layer in the opening.
The metal interconnection structure and the method for fabricating the same according to the embodiments of the present invention are described in detail below with reference to fig. 2 to 6.
As shown in fig. 2, a substrate 10 is provided, a dielectric layer 11 and a first metal layer 12 are formed on the substrate 10, and the dielectric layer 11 surrounds the first metal layer 12; and etching the dielectric layer 11 to form an opening 40 exposing the first metal layer 12, wherein the opening 40 is a step hole, for example.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In the present embodiment, the material of the substrate 10 is preferably single crystal silicon (Si).
Specifically, first, a first dielectric layer 11a is formed on the substrate 10, and then, a first metal layer 12 is formed on the first dielectric layer 11 a. In this embodiment, the first dielectric layer 11a may be formed by a chemical vapor deposition method, a material of the first dielectric layer 11a includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, and in this embodiment, a material of the first dielectric layer 11a is preferably silicon oxide. The material of the first metal material layer includes, but is not limited to, aluminum, and may be formed by a sputtering method, for example.
In this embodiment, after the first metal layer 12 is formed, a hard mask layer 13, an anti-reflection layer 14 and an insulating layer 15 are sequentially formed on the first metal layer 12, and the insulating layer 15 covers the first metal layer 12, the hard mask layer 13, the anti-reflection layer 14 and the first dielectric layer 11 a. A hard mask layer 13 is formed on the first metal layer 12. The hard mask layer 13 has strong hardness and stable performance and is not easy to be etched away by chemical reaction with dry etching gas, and the first metal layer 12 is easy to be etched (including longitudinal etching and transverse etching) by chemical reaction with the dry etching gas, so that the hard mask layer 13 is not easy to be etched and can well keep the appearance in the process of forming the opening 40 by the subsequent etching process, and the first metal layer 12 is etched downwards and is also easy to be etched towards two sides (side digging) simultaneously, thereby increasing the contact area between the subsequently formed second metal layer and the first metal layer 12, reducing the contact resistance between the first metal layer 12 and the second metal layer, improving the contact performance between the first metal layer 12 and the second metal layer, and finally improving the performance of the semiconductor device.
Next, a second dielectric layer 11b is formed, and the second dielectric layer 11b covers the insulating layer 15. In this embodiment, the material of the second dielectric layer 11b includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like, and in this embodiment, the material of the second dielectric layer 11b is preferably silicon oxide, and may be formed by, for example, a chemical vapor deposition method. In other embodiments, the second dielectric layer 11b may be formed directly on the first metal layer 12, and the second dielectric layer11b cover the first dielectric layer 11a and the first metal layer 12. The present invention is not limited to this, and the corresponding layer may be configured according to the actual process requirement. And etching the dielectric layer 11 to form an opening 40 exposing the first metal layer 12. An over-etch may be used to expose the first metal layer 12 sufficiently. As shown in fig. 3, a first barrier layer 21 is formed, and the first barrier layer 21 covers at least the sidewall and the bottom of the opening 40, and the opening 40 is, for example, a step hole. The first barrier layer 21 on the sidewalls of the opening 40 serves to prevent diffusion of a second metal layer (e.g., copper) subsequently formed in the opening 40 into the dielectric layer 11, thereby preventing electromigration failure due to diffusion. The first barrier layer 21 is, for example, TaN or TiN. The barrier layer 21 can be formed by magnetron sputtering or PECVD deposition. In an embodiment of the invention, the first barrier layer is formed by a magnetron sputtering method, and the thickness of the first barrier layer is 250-350 angstroms. The target material is tantalum (Ta) material or titanium (Ti) material. Specifically, the metal interconnection structure with the opening 40 is cleaned, and then sent to a magnetron sputtering chamber of a magnetron sputtering device for sputtering to form the first barrier layer 21. Setting specific parameters: the power range of the bias power supply is 700W-900W, and the reaction gas is nitrogen (N)2) The flow rate is 21-26 sccm, and the flow rate of argon (Ar) as a working gas is 450-550 sccm. The higher bias power of this embodiment improves the step coverage of the first barrier layer 21.
The first metal layer 12 is, for example, aluminum (Al), and the dielectric layer 11 is etched to form an opening 40, so that AlF is easily generated when the first metal layer 12 is exposed (in order to fully expose, over-etching is adopted), for example, dry etching is adopted, and a gas containing fluorine (F) or a polymer containing fluorine (F) is used in a dry etching process, and is in contact with aluminum (Al)3(ii) a Oxidation of aluminum (Al) to Al2O3. Residue 31 is wrapped together during the formation of first barrier layer 21 at the bottom of opening 40. The residue 31 includes, for example: AlF3And Al2O3And the residue 31 can greatly increase the contact resistance between the first metal layer 12 and the subsequently formed second metal layer, and the performance and the service life of the finally formed semiconductor device are affected by the overlarge contact resistance. Thus requiring removal at opening 40A bottom first barrier layer 21 to remove residue 31. In this embodiment, only one film formation (first barrier layer 21) process is performed before removing the first barrier layer 21 at the bottom of the opening 40, which reduces the number of processes for forming a barrier layer once and improves WPH (yield per hour) compared to the two film formation processes (for example, forming a TaN barrier layer and then forming a Ta barrier layer) in the process for connecting a copper metal layer and a copper metal layer.
As shown in fig. 4, the first barrier layer 21 at the bottom of the opening 40 is removed to remove the residue 31. The method still adopts magnetron sputtering, and comprises the following steps: under the condition that the bias power supply power range is 900W-1200W, the flow rate of the working gas argon (Ar) is 450 sccm-550 sccm. The higher bias power and argon (Ar) flow increases the ability to penetrate (bombard) the first barrier layer 21 at the bottom of the opening 40. The first barrier layer 21 at the bottom of the opening 40 is bombardedly removed by argon (Ar) plasma sputtering to remove the residue 31. The removal of the residue 31 substantially reduces the contact resistance of the first metal layer 12 and the subsequently formed second metal layer. The bombardment process forms impurities, and part of the impurities are adsorbed on the side wall of the open hole. Specifically, the first barrier layer 21 and the residue 31 at the bottom of the opening 40 are removed by bombardment, a part of the first barrier layer is bombarded to the outside of the opening 40, and a part of the first barrier layer splashes (adsorbs) to the sidewall of the opening 40, and the impurities 32 are mainly concentrated at the position below the sidewall of the opening 40. The impurities 32 comprise the constituents of the residue 31 and the splashed aluminum particles, i.e. the impurities 32 comprise AlF3、Al2O3And particles of Al and the like. If the impurity 32 is exposed in the opening 40, the second metal layer (e.g., copper) subsequently formed in the opening 40 is in direct contact with the impurity 32 (containing metal), and the copper has high activity and diffuses into the impurity 32 to easily cause electromigration failure or cause unstable resistance of the second metal layer.
As shown in fig. 5, a second barrier layer 22 is formed, the second barrier layer 22 covers at least the bottom of the opening 40 and the first barrier layer 21, and the impurities 32 are encapsulated during the process of covering the first barrier layer 21 by the second barrier layer 22, that is, the impurities 32 are encapsulated between the first barrier layer 21 and the second barrier layer 22. In this way, the second metal layer (e.g., copper) subsequently formed in the opening 40 does not directly contact the impurity 32 (containing metal), thereby preventing the resistance of the second metal layer from being unstable due to the exposed impurity.
The second barrier layer is TaN or TiN, and the thickness of the second barrier layer is 200-300 angstroms. The method for forming the second barrier layer adopts a magnetron sputtering method, and the specific parameters comprise: the power range of the bias power supply is 700W-900W, and the reaction gas is nitrogen (N)2) The flow rate is 21sccm to 26sccm, and the flow rate of the working gas argon (Ar) is 450sccm to 550 sccm. The higher bias power of this embodiment improves the step coverage of the second barrier layer 22.
During the process of forming the first barrier layer 21 and the second barrier layer 22, a reaction gas of nitrogen (N)2) The flow rate is higher (for example, 21sccm to 26sccm), so that the nitridation is more sufficient during the formation of the TaN or TiN barrier layer, the crystal growth of the first barrier layer 21 and the second barrier layer 22 is more active, and the formed first barrier layer 21 and the second barrier layer 22 are more dense, so that the diffusion prevention capability is higher. On the one hand, diffusion of the subsequently formed second metal layer 50 (e.g. copper) into the dielectric layer 11 is prevented, and on the other hand interdiffusion of the first and second metal layers is prevented.
As shown in fig. 6, a second metal layer 50 is formed within the opening 40. The second metal layer 50 is, for example, copper, and is formed by an electroplating process; the second metal layer 50 may also be tungsten. The second metal layer 50 fills the opening 40, a second barrier layer 22 (located at the bottom of the opening 40) is formed between the second metal layer 50 and the first metal layer 12, and the first metal layer 12 and the second metal layer 50 are electrically connected through the second barrier layer 22.
The second barrier layer 22, on one hand, wraps the impurity 32, and prevents the resistance of the second metal layer 50 from being unstable due to the exposed leakage of the impurity 32; on the other hand, the crystal growth process of the second barrier layer 22 is more active, and the formed second barrier layer 22 is more dense, so that the diffusion prevention capability thereof is stronger (the diffusion prevention capability of the second barrier layer 22 is enhanced), and the mutual diffusion of the first metal layer 12 and the second metal layer 50 can be effectively prevented to form a metal alloy. Aluminum is difficult to block due to large crystal grains and uneven surface appearance. In this embodiment, the second barrier layer is TaN or TiN, and the formed second barrier layer 22 is more compact and has stronger diffusion prevention capability, so that mutual diffusion of the copper metal layer and the aluminum metal layer can be effectively prevented; the interdiffusion of the tungsten metal layer and the aluminum metal layer can be effectively prevented.
The present invention also provides a metal interconnection structure, as shown in fig. 6, including:
the semiconductor device comprises a substrate 10, a dielectric layer 11 and a first metal layer 12, wherein the dielectric layer 11 is positioned on the substrate 10 and surrounds the first metal layer 12;
the opening is formed in the dielectric layer to expose the first metal layer;
a first barrier layer 21, the first barrier layer 21 covering sidewalls of the opening 40;
a second barrier layer 22, wherein the second barrier layer 22 covers the first metal layer 12 and the first barrier layer 21 exposed by the opening 40; and the number of the first and second groups,
and a second metal layer 50 located within the opening 40.
The material of the first metal layer 12 includes aluminum, and the material of the second metal layer 50 includes copper.
In summary, the present invention provides a metal interconnection structure and a method for fabricating the same, including: forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening; the first barrier layer wraps the residue at the bottom of the opening. And removing the first barrier layer at the bottom of the opening to remove residues. And forming a second barrier layer, wherein the second barrier layer at least covers the bottom of the opening and the first barrier layer. And forming a second metal layer in the opening. And a second barrier layer is formed between the second metal layer and the first metal layer, and the first metal layer and the second metal layer are electrically connected through the second barrier layer. The second barrier layer has strong diffusion prevention capability and can effectively prevent the mutual diffusion of the first metal layer and the second metal layer from forming metal alloy, so that the electromagnetic compatibility (EMC) performance of the semiconductor device made of the metal interconnection structure is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a metal interconnection structure is characterized by comprising the following steps:
providing a substrate, and forming a dielectric layer and a first metal layer on the substrate, wherein the dielectric layer surrounds the first metal layer; etching the dielectric layer to form an opening exposing the first metal layer;
forming a first barrier layer, wherein the first barrier layer at least covers the side wall and the bottom of the opening;
removing the first barrier layer at the bottom of the opening and exposing the first metal layer; and the number of the first and second groups,
forming a second barrier layer at least covering the first metal layer and the first barrier layer exposed by the opening;
and forming a second metal layer in the opening.
2. The method of claim 1, wherein the first barrier layer is TaN or TiN.
3. The method for manufacturing a metal interconnection structure according to claim 2, wherein the method for forming the first barrier layer is a magnetron sputtering method, and specific parameters include: the power range of the bias power supply is 700W-900W, the flow rate of nitrogen is 21 sccm-26 sccm, and the thickness of the first barrier layer is 250 angstroms-350 angstroms.
4. The method of claim 1, wherein the removing the first barrier layer at the bottom of the opening by magnetron sputtering comprises: and bombarding and removing the first barrier layer at the bottom of the open pore by argon plasma sputtering under the condition that the power range of the bias power supply is 900-1200W, wherein impurities are generated in the bombardment process, and part of the impurities are adsorbed on the side wall of the open pore.
5. The method of claim 4, wherein the second barrier layer further covers the impurities adsorbed on the sidewalls of the opening.
6. The method of claim 1, wherein the second barrier layer is TaN or TiN.
7. The method for manufacturing a metal interconnection structure according to claim 6, wherein the second barrier layer is formed by magnetron sputtering, and specific parameters include: the power range of the bias power supply is 700W-900W, the flow rate of nitrogen is 21 sccm-26 sccm, and the thickness of the second barrier layer is 200 angstroms-300 angstroms.
8. The method as claimed in any one of claims 1 to 7, wherein the material of the first metal layer comprises Al, and the material of the second metal layer comprises Cu.
9. A metal interconnect structure, comprising:
the device comprises a substrate, a dielectric layer and a first metal layer, wherein the dielectric layer and the first metal layer are positioned on the substrate, and the dielectric layer surrounds the first metal layer;
the opening is formed in the dielectric layer to expose the first metal layer;
a first barrier layer covering sidewalls of the opening;
a second barrier layer covering the first metal layer and the first barrier layer exposed by the opening; and the number of the first and second groups,
and the second metal layer is positioned in the opening.
10. The metal interconnect structure of claim 9, wherein a material of the first metal layer comprises aluminum and a material of the second metal layer comprises copper.
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| CN201911359167.6A CN111092050B (en) | 2019-12-25 | 2019-12-25 | Metal interconnection structure and manufacturing method thereof |
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| CN201911359167.6A CN111092050B (en) | 2019-12-25 | 2019-12-25 | Metal interconnection structure and manufacturing method thereof |
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| CN111092050B CN111092050B (en) | 2022-08-19 |
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| CN201911359167.6A Active CN111092050B (en) | 2019-12-25 | 2019-12-25 | Metal interconnection structure and manufacturing method thereof |
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| CN111863721A (en) * | 2020-07-31 | 2020-10-30 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN114497199A (en) * | 2020-10-23 | 2022-05-13 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115295530A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN114497199B (en) * | 2020-10-23 | 2024-05-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN111863721A (en) * | 2020-07-31 | 2020-10-30 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| WO2022021581A1 (en) * | 2020-07-31 | 2022-02-03 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN114497199A (en) * | 2020-10-23 | 2022-05-13 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN114497199B (en) * | 2020-10-23 | 2024-05-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115295530A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115295530B (en) * | 2022-10-08 | 2023-01-24 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN111092050B (en) | 2022-08-19 |
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