CN111081653A - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN111081653A CN111081653A CN201911162862.3A CN201911162862A CN111081653A CN 111081653 A CN111081653 A CN 111081653A CN 201911162862 A CN201911162862 A CN 201911162862A CN 111081653 A CN111081653 A CN 111081653A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a semiconductor packaging structure, which comprises a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first chip, the second semiconductor device comprises a second chip, and the first semiconductor device and the second semiconductor device are oppositely arranged; a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and a second insulating layer covering the first insulating layer. Therefore, the first insulating layer isolates and covers the first semiconductor device and the second semiconductor device which are oppositely arranged, and the second insulating layer continuously covers the first insulating layer, so that the high-voltage resistance characteristic of a packaged product can be improved, and breakdown is effectively prevented. A corresponding method is also disclosed.
Description
Technical Field
The invention relates to the field of display, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip.
The packaging process is for example: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; the individual chips are then encapsulated and protected by a plastic housing. After the plastic package, a series of operations, such as a finished product test, are performed.
However, the breakdown resistance of the packaged product is still a problem that is being studied in the industry.
Disclosure of Invention
The invention aims to provide a semiconductor packaging structure and a preparation method thereof, which can improve the high-voltage resistance of a packaged product and effectively prevent breakdown.
To solve the above technical problem, the present invention provides a semiconductor package structure, including:
the semiconductor device comprises a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first chip, the second semiconductor device comprises a second chip, and the first semiconductor device and the second semiconductor device are oppositely arranged;
a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and
and a second insulating layer covering the first insulating layer.
Optionally, for the semiconductor package structure, a distance D between the first semiconductor device and the second semiconductor device is between 0.05 mm and 0.15 mm.
Optionally, for the semiconductor package structure, the first semiconductor device includes a signal transmitting module, and the second semiconductor device includes a signal receiving module.
Optionally, for the semiconductor package structure, the signal transmitting module and the signal receiving module are disposed opposite to each other.
Optionally, for the semiconductor package structure, the thickness of the first insulating layer is 1.6-3.6 mm, and the thickness of the second insulating layer is 1-2 mm.
The invention also provides a preparation method of the semiconductor packaging structure, which comprises the following steps:
preparing a first semiconductor device and a second semiconductor device, the first semiconductor device including a first chip, the second semiconductor device including a second chip;
clamping and moving the first semiconductor device and the second semiconductor device by a mold to reach a set relative position of the first semiconductor device and the second semiconductor device;
performing first insulation packaging, forming a first insulation layer to cover a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and isolating and fixing the first semiconductor device and the second semiconductor device; and
and performing second insulation packaging to form a second insulation layer to cover the first insulation layer.
Optionally, for the method for manufacturing the semiconductor package structure, the steps of manufacturing the first semiconductor device and the second semiconductor device each include:
providing a substrate;
disposing a chip on the substrate; and
and connecting the chip and the substrate by wire bonding.
Optionally, for the method for manufacturing the semiconductor package structure, the chip of the first semiconductor device, i.e., the first chip, includes a signal transmitting module, and the chip of the second semiconductor device, i.e., the second chip, includes a signal receiving module; moving the first semiconductor device and the second semiconductor device so that the signal transmitting module and the signal receiving module are disposed facing each other.
Optionally, with respect to the method for manufacturing the semiconductor package structure, a second insulating layer is formed, and the first semiconductor device and the second semiconductor device are partially exposed outside the second insulating layer, and then the method further includes: an electroplating process is performed on the exposed first and second semiconductor devices.
In the semiconductor packaging structure and the preparation method provided by the invention, the semiconductor packaging structure comprises a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first chip, the second semiconductor device comprises a second chip, and the first semiconductor device and the second semiconductor device are oppositely arranged; a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and a second insulating layer covering the first insulating layer. Therefore, the first insulating layer isolates and covers the first semiconductor device and the second semiconductor device which are oppositely arranged, and the second insulating layer continuously covers the first insulating layer, so that the high-voltage resistance characteristic of a packaged product can be improved, and breakdown is effectively prevented.
Correspondingly, the method for preparing the semiconductor packaging structure is simple in process and good in effect, and can greatly improve the production efficiency and the product yield.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the fabrication of a first semiconductor device and a second semiconductor device in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the formation of a first insulating layer according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating the formation of a second insulating layer according to an embodiment of the invention.
Detailed Description
The semiconductor package structure and the display device of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
The core idea of the invention is to provide a semiconductor packaging structure, which comprises:
the semiconductor device comprises a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first chip, the second semiconductor device comprises a second chip, and the first semiconductor device and the second semiconductor device are oppositely arranged;
a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and
and a second insulating layer covering the first insulating layer.
Therefore, the first insulating layer isolates and covers the first semiconductor device and the second semiconductor device which are oppositely arranged, and the second insulating layer continuously covers the first insulating layer, so that the high-voltage resistance characteristic of a packaged product can be improved, and breakdown is effectively prevented.
Correspondingly, the invention also provides a preparation method of the semiconductor packaging structure, which comprises the following steps:
preparing a first semiconductor device and a second semiconductor device, the first semiconductor device including a first chip, the second semiconductor device including a second chip;
clamping and moving the first semiconductor device and the second semiconductor device by a mold to reach a set relative position of the first semiconductor device and the second semiconductor device;
performing first insulation packaging, forming a first insulation layer to cover a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and isolating and fixing the first semiconductor device and the second semiconductor device; and
and performing second insulation packaging to form a second insulation layer to cover the first insulation layer.
Therefore, the method for preparing the semiconductor packaging structure is simple in process, the first semiconductor device and the second semiconductor device which are oppositely arranged are isolated and covered by the first insulating layer, the first insulating layer is continuously covered by the second insulating layer, the protection effect is good, the production efficiency can be greatly improved, and the product yield can be improved.
As shown in fig. 1 to 4, the following examples of the semiconductor package structure and the method for fabricating the same are given to clearly illustrate the content of the present invention, and it should be understood that the content of the present invention is not limited to the following examples, and other modifications by conventional technical means of those skilled in the art are within the scope of the idea of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a semiconductor package structure, including the following steps:
step S11 of preparing a first semiconductor device including a first chip and a second semiconductor device including a second chip;
a step S12 of clamping and moving the first semiconductor device and the second semiconductor device by a mold to reach a set relative position of the first semiconductor device and the second semiconductor device;
step S13 of performing a first insulation packaging, forming a first insulation layer to cover a portion of the first semiconductor device including the first chip and a portion of the second semiconductor device including the second chip, and isolating and fixing the first semiconductor device and the second semiconductor device; and
step S14, performing a second insulation packaging to form a second insulation layer to cover the first insulation layer.
Specifically, referring to fig. 1, for step S11, a first semiconductor device including the first chip 11 and a second semiconductor device including the second chip 21 are prepared.
In this step, the preparing of the first semiconductor device and the preparing of the second semiconductor device are substantially identical, and the steps of preparing the first semiconductor device and the second semiconductor device each include:
providing a substrate;
disposing a chip on the substrate; and
and connecting the chip and the substrate by wire bonding.
Specifically, for example, for the first semiconductor device, there may be:
providing a first substrate 10; the first substrate 10 has pads (not shown) thereon. The first substrate 10 may be formed of, for example, undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge). By way of example, in the present embodiment, the first substrate 10 is made of a single crystal silicon material. A buried layer (not shown) or the like may be formed in the first substrate 10. In addition, active devices or passive devices may be formed in the first substrate, and a metal interconnect layer may be formed on the active devices or the passive devices, for example, the bonding pad may be a top structure of the metal interconnect layer. For example, the number of the pads may be plural.
Thereafter, the first chip 11 is disposed on the first substrate 10, which may be done by using the prior art and will not be described in detail here.
Then, the first chip 11 and the first substrate 10 are wire bonded. A first wire 12 between the first chip 11 and the first substrate 10 is schematically shown in fig. 2.
Accordingly, the second chip 21 and the second substrate 20 may be prepared by the same or similar process, for example, by connecting the second chip 21 and the second substrate 20 through the second wire 22.
In an embodiment of the present invention, the chip of the first semiconductor device, i.e., the first chip, includes a signal transmitting module, and the chip of the second semiconductor device, i.e., the second chip, includes a signal receiving module;
in the embodiment of the present invention, the first substrate 10 and the second substrate 20 may have a specific shape, for example, the first substrate includes a first circumscribed portion 101 and a first carrying portion 102, a gradient is formed between the first circumscribed portion 101 and the first carrying portion 102, and the first carrying portion 102 may be lower than the first circumscribed portion 101 with reference to the first circumscribed portion 101, for example, the first carrying portion may be formed in the form of a groove, and more specifically, the groove may be formed at different (i.e., non-opposite) positions on opposite sides of the first substrate 10. The first carrier part 102 is used for arranging the first chip 11. Likewise, the second substrate 10 includes a second outer portion 201 and a second carrier portion 202, which may be completed in the same or similar manner as the first substrate 10. The second carrier portion 202 is used for arranging the second chip 21.
With continuing reference to fig. 2 for step S12, the first and second semiconductor devices may be clamped by a mold (not shown) and moved to reach a set relative position of the first and second semiconductor devices. Specifically, the actual position can be adjusted according to factors such as actual chip parameters and process requirements. In the embodiment of the present invention, the first chip 11 and the second chip 21 may be disposed opposite to each other. For example, the distance D (shown in FIG. 4) between the first chip 11 and the second chip 21 may be 0.05-0.15 mm, such as 0.06mm, 0.07mm, 0.08mm, 0.09mm, 0.10mm, 0.11mm, 0.12mm, 0.13mm, 0.14mm, etc. The distance D is the distance between the chips (including the wires) after routing.
Referring to fig. 3, in step S13, a first insulation packaging is performed, a first insulation layer 30 is formed to cover a portion of the first semiconductor device including the first chip 11 and a portion of the second semiconductor device including the second chip 21, and the first semiconductor device and the second semiconductor device are isolated and fixed.
In the embodiment of the present invention, the first insulating package may be in the form of an insulating paste.
In the embodiment of the invention, the whole first insulating layer 30 may be hexagonal, for example, the first external connection portion 101 and the second external connection portion 201 are coplanar, the first insulating layer 30 is symmetrically distributed on two sides of S1 and S2 of the coplanar, for example, on the side of S1, the length of three sides L1 is 0.5 to 0.7mm, L2 is 5 to 8mm, L3 is 0.5 to 0.7mm, two vertex angles α are 65 to 85 degrees, β is 65 to 85 degrees, or the thickness of the first insulating layer 30 on the side of S1 is 0.8 to 1.8 mm.
Specifically, the first insulating layer 30 covers between about 1/3-2/3 of the first external connection portion 101 and the second external connection portion 201.
Referring to fig. 4, in step S14, a second insulation packaging is performed to form a second insulation layer 40 to cover the first insulation layer.
In an embodiment of the present invention, the second insulating package may take the form of conventional packaging plastic.
In the embodiment of the present invention, the thickness H of the second insulating layer 40 may be, for example, 1 to 2 mm.
Further, after forming the second insulating layer, the method further includes: an electroplating process is performed on the exposed first and second semiconductor devices. Specifically, for example, the connection portions between the first external connection portion 101 and the second external connection portion 201 and other external modules are plated.
With continued reference to fig. 4, a semiconductor package structure obtained by the present invention includes:
a first semiconductor device including a first chip 11, a second semiconductor device including a second chip 21, the first semiconductor device and the second semiconductor device being disposed opposite to each other;
a first insulating layer 30 covering a portion of the first semiconductor device including the first chip 11 and a portion of the second semiconductor device including the second chip 21, and achieving isolation and fixation of the first semiconductor device and the second semiconductor device; and
and a second insulating layer 40 covering the first insulating layer 30.
Preferably, the distance D between the first semiconductor device and the second semiconductor device is 0.05-0.15 mm.
Preferably, the first chip includes a signal transmitting module, and the second semiconductor device includes a signal receiving module. The signal transmitting module and the signal receiving module are arranged just opposite to each other.
Preferably, the thickness of the first insulating layer is 1.6-3.6 mm, and the thickness of the second insulating layer is 1-2 mm.
In summary, in the semiconductor package structure and the manufacturing method thereof provided by the present invention, the semiconductor package structure includes a first semiconductor device including a first chip, a second semiconductor device including a second chip, and the first semiconductor device and the second semiconductor device are disposed opposite to each other; a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and a second insulating layer covering the first insulating layer. Therefore, the first insulating layer isolates and covers the first semiconductor device and the second semiconductor device which are oppositely arranged, and the second insulating layer continuously covers the first insulating layer, so that the high-voltage resistance characteristic of a packaged product can be improved, and breakdown is effectively prevented.
Correspondingly, the method for preparing the semiconductor packaging structure is simple in process and good in effect, and can greatly improve the production efficiency and the product yield.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A semiconductor package structure, comprising:
the semiconductor device comprises a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first chip, the second semiconductor device comprises a second chip, and the first semiconductor device and the second semiconductor device are oppositely arranged;
a first insulating layer covering a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and realizing isolation and fixation of the first semiconductor device and the second semiconductor device; and
and a second insulating layer covering the first insulating layer.
2. The semiconductor package structure of claim 1, wherein a spacing D between the first semiconductor device and the second semiconductor device is between 0.05 mm and 0.15 mm.
3. The semiconductor package structure of claim 2, wherein the first chip comprises a signal transmitting module and the second semiconductor device comprises a signal receiving module.
4. The semiconductor package of claim 3, wherein the signal transmitting module is disposed opposite to the signal receiving module.
5. The semiconductor package structure of claim 1, wherein the first insulating layer has a thickness of 1.6-3.6 mm, and the second insulating layer has a thickness of 1-2 mm.
6. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
preparing a first semiconductor device and a second semiconductor device, the first semiconductor device including a first chip, the second semiconductor device including a second chip;
clamping and moving the first semiconductor device and the second semiconductor device by a mold to reach a set relative position of the first semiconductor device and the second semiconductor device;
performing first insulation packaging, forming a first insulation layer to cover a part of the first semiconductor device including the first chip and a part of the second semiconductor device including the second chip, and isolating and fixing the first semiconductor device and the second semiconductor device; and
and performing second insulation packaging to form a second insulation layer to cover the first insulation layer.
7. The method of fabricating a semiconductor package according to claim 6, wherein the steps of fabricating the first semiconductor device and the second semiconductor device each comprise:
providing a substrate;
disposing a chip on the substrate; and
and connecting the chip and the substrate by wire bonding.
8. The method of manufacturing a semiconductor package according to claim 7, wherein the first chip includes a signal transmitting module, and the second chip includes a signal receiving module; moving the first semiconductor device and the second semiconductor device so that the signal transmitting module and the signal receiving module are disposed facing each other.
9. The method of fabricating a semiconductor package according to claim 6, wherein a second insulating layer is formed, the first semiconductor device and the second semiconductor device being partially exposed outside the second insulating layer, and thereafter further comprising: an electroplating process is performed on the exposed first and second semiconductor devices.
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| CN201911162862.3A CN111081653A (en) | 2019-11-25 | 2019-11-25 | Semiconductor packaging structure and preparation method thereof |
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| US20180204790A1 (en) * | 2015-08-07 | 2018-07-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
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2019
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| CN1591861A (en) * | 2003-08-28 | 2005-03-09 | 松下电器产业株式会社 | Circuit component built-in module and method for manufacturing the same |
| CN1665136A (en) * | 2004-03-03 | 2005-09-07 | 夏普株式会社 | Solid state relay |
| CN101599484A (en) * | 2008-06-05 | 2009-12-09 | 三菱电机株式会社 | Resin molded semiconductor device and manufacture method thereof |
| US20180204790A1 (en) * | 2015-08-07 | 2018-07-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
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Application publication date: 20200428 |
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