CN111079913A

CN111079913A - Operation method, device and related product

Info

Publication number: CN111079913A
Application number: CN201811221780.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2018-10-19
Filing date: 2018-10-19
Publication date: 2020-04-28
Anticipated expiration: 2038-10-19
Also published as: CN111079913B

Abstract

The disclosure relates to an operation method, an operation device and a related product. The device comprises a device determining module and an instruction generating module, wherein the device determining module is used for determining the running device for executing the scalar logic calculation macro instruction according to the received scalar logic calculation macro instruction. The instruction generation module is used for calculating macro instructions and operation equipment according to scalar logic to generate operation instructions. The operation method, the operation device and the related products provided by the embodiment of the disclosure can be used in a cross-platform mode, and have the advantages of good applicability, high instruction conversion speed, high processing efficiency, low error probability and low development cost of manpower and material resources.

Description

Operation method, device and related product

Technical Field

The present disclosure relates to the field of information processing technologies, and in particular, to a method and an apparatus for generating scalar logic calculation instructions, and a related product.

Background

With the continuous development of science and technology, neural network algorithms are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the scale of the neural network algorithms is continuously increased. A large-scale neural network model based on a Graphics Processing Unit (GPU) and a Central Processing Unit (CPU) takes a lot of computation time and consumes a lot of power. In the related art, the method for accelerating the processing speed of the neural network model has the problems of incapability of cross-platform processing, low processing efficiency, high development cost, easiness in making mistakes and the like.

Disclosure of Invention

In view of this, the present disclosure provides a scalar logic computation instruction generation method, apparatus, and related product, which enable cross-platform use, improve processing efficiency, and reduce error probability and development cost.

According to a first aspect of the present disclosure, there is provided a scalar logic computation instruction generation apparatus, the apparatus comprising:

the device determination module is used for determining running devices for executing the scalar logic calculation macro instructions according to the received scalar logic calculation macro instructions;

an instruction generation module, configured to calculate a macro instruction according to the scalar logic and the execution device, and generate an execution instruction,

wherein the scalar logic computation macro instruction refers to a macro instruction for performing a logic operation on a scalar,

the scalar logic computation macro-instruction includes an operation type, a first operand, a second operand, and an output address,

the operation instruction comprises the operation type, a first operation operand, a second operation operand and an operation output address, wherein the first operation operand, the second operation operand and the operation output address are determined according to the first operand, the second operand and the output address respectively.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more scalar logic computation instruction generation devices according to the first aspect, configured to obtain data to be computed and control information from another processing device, execute a specified machine learning operation, and transmit an execution result to the other processing device through an I/O interface;

when the machine learning operation device comprises a plurality of scalar logic calculation instruction generation devices, the scalar logic calculation instruction generation devices can be connected through a specific structure and transmit data;

the scalar logic calculation instruction generation devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data so as to support larger-scale machine learning operation; the scalar logic calculation instruction generation devices share the same control system or own respective control systems; the scalar logic calculation instruction generation devices share a memory or own memories; the interconnection mode of the scalar logic calculation instruction generation devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided a scalar logic computation instruction generation method, the method comprising:

according to the received scalar logic calculation macro instruction, determining an operation device for executing the scalar logic calculation macro instruction;

computing a macro instruction and the execution device according to the scalar logic, generating an execution instruction,

wherein the scalar logic computation macro instruction refers to a macro instruction for performing a logical operation on a scalar, the scalar logic computation macro instruction including an operation type, a first operand, a second operand, and an output address,

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

The device comprises a device determining module and an instruction generating module, wherein the device determining module is used for determining running equipment for executing the scalar logic calculation macro instruction according to the received scalar logic calculation macro instruction. The instruction generation module is used for calculating macro instructions and operation equipment according to scalar logic to generate operation instructions. The method, the device and the related products can be used in a cross-platform mode, the applicability is good, the instruction conversion speed is high, the processing efficiency is high, the error probability is low, and the cost of developing manpower and material resources is low.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of a scalar logic computation instruction generation apparatus according to an embodiment of the present disclosure.

Fig. 2 illustrates a block diagram of a scalar logic compute instruction generation apparatus according to an embodiment of the present disclosure.

Fig. 3a and 3b are schematic diagrams illustrating an application scenario of a scalar logic computation instruction generation apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 illustrates a flow diagram of a scalar logic compute instruction generation method according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 shows a block diagram of a scalar logic computation instruction generation apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a device determination module 11 and an instruction generation module 12. The device determining module 11 is configured to determine, according to the received scalar logic calculation macro, an execution device that executes the scalar logic calculation macro. The instruction generation module 12 is configured to calculate macro instructions and execution devices according to scalar logic, and generate execution instructions.

The scalar logic computation macro instruction is a macro instruction for performing a logic operation on a scalar. The scalar logic computing macro-instruction comprises an operation type, a first operand, a second operand and an output address, and the execution instruction comprises the operation type, a first execution operand, a second execution operand and an execution output address. The first operation operand, the second operation operand, and the operation output address are determined according to the first operand, the second operand, and the output address, respectively.

In this embodiment, macro is a name for batch processing, and macro may be a rule or pattern, or syntax replacement, which is automatically performed when macro is encountered. The scalar logic calculation macro instruction can be formed by integrating common scalar logic calculation instructions to be executed for performing calculation, control, transportation and other processing on data.

In this embodiment, the operation type may refer to a type of an operation performed by the scalar logic computation macro instruction on the data, and represents a specific type of the scalar logic computation macro instruction, for example, when an operation type of a certain scalar logic computation macro instruction is "XXX", the specific type of the operation performed by the scalar logic computation macro instruction on the data may be determined according to "XXX". The instruction set required for executing the scalar logic computation macro instruction can be determined according to the operation type, for example, when the operation type of a certain scalar logic computation macro instruction is "XXX", the required instruction set is all instruction sets required for performing the processing corresponding to "XXX". The first and second operands are scalar storage locations, which may include length of register, address of register, identification of register, immediate, and the like. The immediate is the number given in the immediate addressing mode instruction. The output address may be an address where data is stored, such as an output address and a write address of the processed data. The scalar logic computation macro instruction may also include other parameters related to scalar computation, which are not limited by this disclosure.

In one possible implementation, the scalar logic compute macro instruction may include at least one of: scalar and compute macro, scalar or compute macro, scalar non-compute macro, scalar compare compute macro.

It should be understood that the instruction format and inclusion of scalar logic compute macroinstructions may be configured as desired by one skilled in the art and are not limited by the present disclosure.

In this embodiment, the device determination module 11 may determine one or more running devices according to a scalar logic computation macro. Instruction generation module 12 may generate one or more execution instructions. When a plurality of generated operating instructions are provided, the plurality of operating instructions may be executed in the same operating device or different operating devices, and the present disclosure is not limited thereto.

In this embodiment, when the number of execution devices is one, the instruction generation module 12 may generate one or more execution instructions according to the scalar logic calculation macro instruction. When there are multiple execution devices, the instruction generation module 12 may generate an execution instruction corresponding to each execution device according to the scalar logic calculation macro, where each execution device may correspond to one or more execution instructions.

The scalar logic calculation instruction generation device provided by the embodiment of the disclosure comprises an equipment determination module and an instruction generation module, wherein the equipment determination module is used for determining an operation device for executing a scalar logic calculation macro instruction according to the received scalar logic calculation macro instruction. The instruction generation module is used for calculating macro instructions and operation equipment according to scalar logic to generate operation instructions. The device can be used in a cross-platform mode, the applicability is good, the instruction conversion speed is high, the processing efficiency is high, the error probability is low, and the development labor and material cost is low.

Fig. 2 illustrates a block diagram of a scalar logic compute instruction generation apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2, the device determining module 11 may include a first determining sub-module 111. The first determining submodule 111 is configured to determine the specified device as an operating device when it is determined that the scalar logic computation macro includes an identifier of the specified device and a resource of the specified device satisfies an execution condition for executing the scalar logic computation macro. Wherein, the execution condition may include: the designated device contains a set of instructions corresponding to scalar logic computation macroinstructions.

The identifier of the specific device may be a physical address, an IP address, a name, a number, and the like of the specific device. The mark may comprise one or any combination of numbers, letters, symbols. When the position of the identifier of the designated device of the scalar logic calculation macro instruction is null, determining that the scalar logic calculation macro instruction has no designated device; alternatively, when the field "identification of specified device" is not included in the scalar logic computation macro instruction, it is determined that the scalar logic computation macro instruction has no specified device.

In this implementation, the scalar logic compute macro may contain within it an identification of one or more specified devices that execute the scalar logic compute macro. When the scalar logic calculation macro includes the identifier of the specified device and the resource of the specified device meets the execution condition, the first determining submodule 111 may directly determine the specified device as the execution device, save the generation time for generating the execution instruction based on the scalar logic calculation macro, and ensure that the generated execution instruction can be executed by the corresponding execution device.

In a possible implementation manner, as shown in fig. 2, the apparatus may further include a macro instruction generation module 13. The macro instruction generation module 13 is configured to receive a scalar logic calculation instruction to be executed, and generate a scalar logic calculation macro instruction according to the determined identifier of the specific device and the scalar logic calculation instruction to be executed.

In this implementation, the specified device may be determined according to the type of operation of the scalar logic computation instruction to be executed, or the like. The received scalar logic calculation instruction to be executed can be one or a plurality of instructions.

The scalar logic compute instruction to be executed may include at least one of: scalar and calculation instructions to be executed, scalar or calculation instructions to be executed, scalar non-calculation instructions to be executed, and scalar comparison calculation instructions to be executed.

The scalar logic compute instruction to be executed may include at least the following: an operation type, a first operand, a second operand, and an output address.

In this implementation, when there is one scalar logic calculation instruction to be executed, the determined identifier of the specific device may be added to the scalar logic calculation instruction to be executed, and a scalar logic calculation macro instruction is generated. For example, some scalar logical compute instruction m to be executed is "XXX … … param". Where XXX is the operation type and param is the instruction parameter. Its designated device m-1 may be determined from the operation type "XXX" of the scalar logical compute instruction m to be executed. Then, an identification (e.g., 09) specifying the device M-1 is added to the scalar logic calculation instruction M to be executed, and a scalar logic calculation macro instruction M "XXX 09, … … param" corresponding to the scalar logic calculation instruction M to be executed is generated. When the scalar logic calculation instruction to be executed is multiple, the determined identifier of the designated device corresponding to each scalar logic calculation instruction to be executed can be added to the scalar logic calculation instruction to be executed, and one scalar logic calculation macro instruction or multiple corresponding scalar logic calculation macro instructions can be generated according to the multiple scalar logic calculation instructions to be executed with the identifiers of the designated devices.

It should be understood that one skilled in the art can arrange the instruction format and the content of the instruction to be executed with scalar logic computation instructions as needed, and the disclosure is not limited thereto.

In one possible implementation, as shown in fig. 2, the apparatus may further include a resource acquisition module 14. The device determination module 11 may also include a second determination submodule 112. The resource obtaining module 14 is configured to obtain resource information of the alternative device. The second determining submodule 112 is configured to, when it is determined that the scalar logic computation macro instruction does not include the identifier of the specified device, determine, from the candidate device, an execution device for executing the scalar logic computation macro instruction according to the received scalar logic computation macro instruction and resource information of the candidate device. Wherein the resource information may comprise a set of instructions contained by the alternative device. The instruction set included by the alternative device may be a set of instructions corresponding to the type of operation of one or more scalar logic compute macro instructions. The more instruction sets that the alternative device contains, the more types of scalar logic that the alternative device is capable of executing compute macroinstructions.

In this implementation, the second determination submodule 112 may determine, from the alternative devices, one or more executing devices capable of executing the scalar logic computation macro instruction upon determining that the scalar logic computation macro instruction does not include the identification of the specified device. Wherein the determined instruction set of the execution device includes an instruction set corresponding to a scalar logic computation macroinstruction. For example, a received scalar logic compute macro instruction is a scalar and compute macro instruction, and an alternate device containing an instruction set corresponding to the scalar and compute macro instruction may be determined to be a runtime device to ensure that it can execute the generated runtime instruction.

In one possible implementation, as shown in fig. 2, the device determining module 11 may further include a third determining sub-module 113. When it is determined that the scalar logic calculation macro includes the identifier of the specified device and the resource of the specified device does not satisfy the execution condition for executing the scalar logic calculation macro, the third determining submodule 113 determines the operating device according to the scalar logic calculation macro and the resource information of the alternative device.

In this implementation, when it is determined that the scalar logic computation macro includes the identifier of the specified device and the resource of the specified device does not satisfy the execution condition, the third determination submodule 113 may determine that the specified device of the scalar logic computation macro does not have the capability of executing the scalar logic computation macro. The third determination submodule 113 may determine an execution device from among alternative devices, and may determine an alternative device containing an instruction set corresponding to the scalar logic calculation macro instruction as an execution device.

In a possible implementation manner, the instruction generation module 12 is further configured to determine a data amount of the scalar logic computation macro instruction according to the first operand and the second operand of the scalar logic computation macro instruction, and generate the execution instruction according to the data amount of the scalar logic computation macro instruction, and resource information of the execution device. The resource information of the operating device may further include at least one of a storage capacity and a remaining storage capacity.

The storage capacity of the operating device may refer to the amount of binary information that the memory of the operating device can accommodate. The remaining storage capacity of the operating device may refer to the storage capacity that the operating device is currently available for instruction execution after the occupied storage capacity is removed. The resource information of the running device can characterize the running capability of the running device. The larger the storage capacity and the larger the remaining storage capacity are, the stronger the operation capability of the operation device is.

In this implementation, the instruction generating module 12 may determine a specific manner of splitting the scalar logic computation macro instruction according to the resource information of each running device, the data size of the scalar logic computation macro instruction, and the like, so as to split the scalar logic computation macro instruction and generate a running instruction corresponding to the running device.

In a possible implementation manner, the instruction generating module 12 may be configured to, when it is determined that there is one execution device and an operation data amount of the execution device is smaller than a data amount of the scalar logic calculation macro, split the scalar logic calculation macro into a plurality of execution instructions according to the operation data amount and the data amount of the execution device, so that the execution device sequentially executes the plurality of execution instructions. Wherein, the operation data amount of the operation device may be determined according to the resource information of the operation device. The operation data amount of the operation device may be determined according to the storage capacity or the remaining storage capacity of the operation device.

In this implementation, when it is determined that there is one execution device and the data amount of the execution device is greater than or equal to the data amount of the scalar logic calculation macro, the instruction generation module 12 may directly convert the scalar logic calculation macro into one execution instruction, and may also split the scalar logic calculation macro into multiple execution instructions, which is not limited in this disclosure.

In a possible implementation manner, the instruction generating module 12 may be configured to, when it is determined that there are multiple running devices, split the scalar logic computation macro instruction according to the running data amount of each running device and the data amount of the scalar logic computation macro instruction, and generate a running instruction corresponding to each running device. Wherein the operation data amount of each operation device may be determined according to the resource information of each operation device.

In this implementation, the instruction generating module 12 may generate one or more operation instructions for each operating device according to the operation data amount of each operating device, so that the corresponding operating device can execute the operation instructions.

In a possible implementation manner, the instruction generating module 12 may further split the scalar logic calculation macro instruction according to the scalar logic calculation macro instruction and a preset scalar logic calculation macro instruction splitting rule to generate the running instruction. The scalar logic computation macro instruction splitting rule may be determined according to a conventional scalar logic computation macro instruction splitting manner (e.g., splitting according to a scalar logic computation macro instruction processing procedure, etc.), in combination with an execution data amount threshold of instructions that all alternative devices are capable of executing. The scalar logic computing macro instruction is divided into the operation instructions with the data quantity smaller than or equal to the operation data quantity threshold value, so that the generated operation instructions can be executed in the corresponding operation device (the operation device is any one of the alternative devices). The storage capacities (or remaining storage capacities) of all the candidate devices may be compared, and the determined minimum storage capacity (or remaining storage capacity) may be determined as an operation data amount threshold of the instruction that can be executed by all the candidate devices.

It should be understood that, the person skilled in the art can set the generation mode of the operation instruction according to the actual needs, and the present disclosure does not limit this.

In this embodiment, the operation instruction generated by the instruction generation module according to the scalar logic calculation macro instruction may be a to-be-executed scalar logic calculation instruction, or may be one or more analyzed instructions obtained by analyzing the to-be-executed instruction, which is not limited in this disclosure.

In one possible implementation, as shown in fig. 2, the apparatus may further include a queue building module 15. The queue building module 15 is configured to sort the operation instructions according to a queue sorting rule, and build an instruction queue corresponding to the operation device according to the sorted operation instructions.

In this implementation, an instruction queue uniquely corresponding to each execution device may be constructed for each execution device. The operating instructions can be sequentially sent to the operating equipment uniquely corresponding to the instruction queue according to the sequence of the operating instructions in the instruction queue; or the instruction queue may be sent to the execution device, so that the execution device sequentially executes the execution instructions in the instruction queue according to the order of the execution instructions in the instruction queue. By the mode, the operation equipment can execute the operation instruction according to the instruction queue, the operation instruction is prevented from being executed mistakenly and delayed, and the operation instruction is prevented from being omitted.

In this implementation, the queue sorting rule may be determined according to information such as an expected execution time for executing the execution instruction, a generation time of the execution instruction, and an operation type related to the execution instruction itself, which is not limited by this disclosure.

In one possible implementation, as shown in FIG. 2, the apparatus may also include an instruction dispatch module 16. The instruction dispatch module 16 is configured to send the execution instruction to the execution device, so that the execution device executes the execution instruction.

In this implementation, when there is one execution instruction executed by the execution device, the execution instruction may be directly sent to the execution device. When the number of the operation instructions executed by the operation device is multiple, all of the multiple operation instructions may be sent to the operation device, so that the operation device sequentially executes the multiple operation instructions. The plurality of operation instructions can also be sequentially sent to the corresponding operation equipment, wherein after the operation equipment completes the current operation instruction, the next operation instruction corresponding to the current operation instruction is sent to the operation equipment each time. The manner in which the person skilled in the art can send the operation instruction to the operation device is set, and the present disclosure does not limit this.

In one possible implementation, as shown in FIG. 2, the instruction dispatch module 16 may include an instruction assembly submodule 161, an assembly translation submodule 162, and an instruction issue submodule 163. The instruction assembling sub-module 161 is used for generating an assembling file according to the operation instruction. The assembly translation sub-module 162 is used to translate the assembly file into a binary file. The instruction sending submodule 163 is configured to send the binary file to the operating device, so that the operating device executes the operating instruction according to the binary file.

By the method, the data volume of the operation instruction can be reduced, the time for sending the operation instruction to the operation equipment is saved, and the conversion and execution speed of the scalar logic calculation macro instruction is increased.

In this implementation manner, after the binary file is sent to the running device, the running device may decode the received binary file to obtain a corresponding running instruction, and execute the obtained running instruction to obtain an execution result.

In a possible implementation manner, the running device may be one or any combination of a CPU, a GPU, and an embedded Neural-Network Processing Unit (NPU). In this way, the speed at which the apparatus generates the run instruction from the scalar logic computation macroinstruction is increased.

In one possible implementation, the apparatus may be provided in the CPU and/or the NPU. The method realizes the process of generating the operation instruction according to the scalar logic calculation macro instruction by the CPU and/or the NPU, and provides more possible modes for realizing the device.

In one possible implementation, the scalar logical compute macro instruction may be a macro instruction for performing a logical operation on a scalar. For example, a macro instruction performs logical operations such as and, compare, or, and not on scalars. Different types of scalar logic computation macro instructions correspond to different operation types, for example, the operation type corresponding to a scalar and computation macro instruction may be SAND, the operation type corresponding to a scalar or computation macro instruction may be SOR.

In this embodiment, for a scalar logic compute macro-instruction, it must include an opcode, i.e., an operation type, and at least one operation domain that includes an identification of a specified device, a first operand, a second operand, and an output address. An opcode may be the portion of an instruction or field (usually denoted by a code) specified in a computer program that is to perform an operation, and is an instruction sequence number that tells the device executing the instruction which instruction specifically needs to be executed. The operation domain may be a source of all data required for executing the corresponding instruction, including parameter data, data to be operated on or processed, a corresponding operation method, or an address or the like storing the parameter data, the data to be operated on or processed, the corresponding operation method.

The present disclosure provides an execution device for executing an execution instruction generated by the scalar logic computation instruction generation apparatus described above. The operating device comprises a control module and an execution module. The control module is used for acquiring data, the neural network model and the operation instruction, can also be used for analyzing the operation instruction, acquiring a plurality of analysis instructions and sending the plurality of analysis instructions and the data to the execution module. The execution module is used for executing a plurality of analysis instructions according to the data to obtain an execution result.

In one possible implementation, the execution device further includes a storage module. The memory module may include at least one of a register and a cache, and the cache may include a scratch pad cache. The cache may be used to store data. The registers may be used to store scalar data within the data.

In one possible implementation, the control module may include an instruction storage sub-module and an instruction processing sub-module. The instruction storage submodule is used for storing the operation instruction. The instruction processing submodule is used for analyzing the operation instruction to obtain a plurality of analysis instructions.

In one possible implementation, the control module may further include a store queue submodule. The storage queue submodule is used for storing an operation instruction queue, and the operation instruction queue comprises an operation instruction and a plurality of analysis instructions which are required to be executed by the operation equipment. And all the instructions in the operation instruction queue are sequentially arranged according to the execution sequence.

In one possible implementation, the execution module may further include a dependency processing sub-module. The dependency relationship processing submodule is used for caching the first analysis instruction in the instruction storage submodule when the first analysis instruction is determined to have an incidence relationship with a zeroth analysis instruction before the first analysis instruction, and extracting the first analysis instruction from the instruction storage submodule to send the first analysis instruction to the execution module after the zeroth analysis instruction is executed.

The association relationship between the first parsing instruction and the zeroth parsing instruction before the first parsing instruction may include: the first storage address interval for storing the data required by the first analysis instruction and the zeroth storage address interval for storing the data required by the zeroth analysis instruction have an overlapping area. Conversely, the no association relationship between the first parse instruction and the zeroth parse instruction may be that the first memory address interval and the zeroth memory address interval have no overlapping area.

The present disclosure provides a scalar logic computation instruction processing system, which includes the above scalar logic computation instruction generation apparatus and the above execution device.

It should be noted that, although the scalar logic computation instruction generation apparatus, the execution device, and the scalar logic computation instruction processing system have been described as above by taking the above embodiments as examples, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application example

An application example according to the embodiment of the present disclosure is given below in conjunction with "a work process of a scalar logic calculation instruction generation apparatus generating a run instruction from a scalar logic calculation macro" as an exemplary application scenario to facilitate understanding of the flow of the scalar logic calculation instruction generation apparatus. It is to be understood by those skilled in the art that the following application examples are for the purpose of facilitating understanding of the embodiments of the present disclosure only and are not to be construed as limiting the embodiments of the present disclosure.

First, the instruction format of the scalar logic calculation macro instruction, the instruction format of the scalar logic calculation instruction to be executed, and the process of executing the execution instruction by the execution device are described, and specific examples are as follows.

The instruction format of the scalar logic compute macro instruction may be:

Type device_id,op1,op2,ans

the Type is an operation Type, the device _ id is an identifier of a designated device, and the op1 and the op2 are two operands. Ans is the storage address of the calculation result of the scalar logic calculation macro instruction or the identification of the register used for storing the calculation result. The size of the acquired scalar quantity and the size of the scalar quantity output by calculating the acquired scalar quantity may be set in advance.

For scalar logic compute macro-instructions, they must contain an operation type, a first operand, a second operand, and an output address. And the operation instruction generated by computing the macro instruction according to the scalar logic also comprises an operation type, a first operation operand, a second operation operand and an operation output address. Wherein the first operation operand, the second operation operand and the operation output address are determined according to the first operand, the second operand and the output address respectively.

Take the example where the execution instructions generated by a scalar logic calculation macro are "@ SAND #703, #704, # 8". After the operation device receives the operation instruction, the execution process is as follows: a first scalar is fetched from an address 703 of the register and a second scalar is fetched from an address 704 of the register, and the first scalar and the second scalar are subjected to an and logical operation, and the obtained result is stored as an execution result at a storage address 8 of the register.

The instruction format of the scalar logic compute instruction to be executed may be:

Type op1,op2,ans

the Type is an operation Type, and the op1 and the op2 are two operands. And Ans is a storage address of a calculation result of the scalar logic calculation instruction to be executed or an identification of a register for storing the calculation result.

Fig. 3a and 3b are schematic diagrams illustrating an application scenario of a scalar logic computation instruction generation apparatus according to an embodiment of the present disclosure. As shown in FIGS. 3a and 3b, the alternative devices for executing scalar logic computation macroinstructions can be a plurality of devices, and the alternative devices can be CPU-1, CPU-2, …, CPU-n, NPU-1, NPU-2, …, NPU-n and GPU-1, GPU-2, … and GPU-n. The working process and principle of computing macro instructions according to certain scalar logic to generate operation instructions are as follows.

Resource acquisition module 14

And acquiring resource information of the alternative device, wherein the resource information comprises the residual storage capacity and the storage capacity of the alternative device and an instruction set contained in the alternative device. The resource obtaining module 14 sends the obtained resource information of the candidate device to the device determining module 11 and the instruction generating module 12.

The device determination module 11 (including a first determination sub-module 111, a second determination sub-module 112, and a third determination sub-module 113)

When receiving the scalar logic computation macro instruction, determining an execution device executing the scalar logic computation macro instruction according to the received scalar logic computation macro instruction. For example, the following scalar logic compute macroinstruction is received. Where scalar logic compute macro instructions may be from different platforms.

Scalar logic compute macro instruction 1: @ XXX #01 … …

Scalar logic compute macro instruction 2: @ SSS #02 … …

Scalar logic compute macro instruction 3: @ DDD #04 … …

Scalar logic compute macro instruction 4: @ NNN … …

When determining that the scalar logic computation macro includes an identifier of a specified device and that the specified device includes an instruction set corresponding to the scalar logic computation macro, the first determination submodule 111 may determine that the specified device is an execution device that executes the scalar logic computation macro, and send the identifier of the determined execution device to the instruction generation module 12. For example, the first determination submodule 111 may determine a specified device corresponding to the identification 01, such as CPU-2 (the CPU-2 includes an instruction set corresponding to the scalar logic computation macro 1), as an execution device for executing the scalar logic computation macro 1. A designated device, such as CPU-1(CPU-1 contains a set of instructions corresponding to scalar logic compute macro instructions 2) to which the identifier 02 corresponds may be determined as the executing device for executing the scalar logic compute macro instructions 2.

When the third determining submodule 113 determines that the scalar logic computation macro instruction contains the identifier of the specified device and determines that the specified device does not contain the instruction set corresponding to the scalar logic computation macro instruction, the third determining submodule 113 may determine, as the execution device, the candidate device containing the instruction set corresponding to the scalar logic computation macro instruction, and transmit the identifier of the determined execution device to the instruction generating module 12. For example, when determining that the instruction set corresponding to the scalar logic computation macro instruction 3 is not included in the specified device corresponding to the identifier 04, the third determination submodule 113 may determine, as the execution device for executing the scalar logic computation macro instruction 3, an alternative device such as NPU-n, NPU-2 that includes the instruction set corresponding to the operation type DDD of the scalar logic computation macro instruction 3.

When the second determining submodule 112 determines that the scalar logic calculation macro instruction does not have the identifier of the specified device (the position corresponding to the identifier of the specified device is empty, or the scalar logic calculation macro instruction does not include the field of "identifier of the specified device"), the second determining submodule 112 may determine the operating device from the alternative devices according to the scalar logic calculation macro instruction and the resource information of the alternative devices (the specific determination process is detailed in the related description of the second determining submodule 112), and send the determined identifier of the operating device to the instruction generating module 12. For example, since the scalar logic computation macro 4 does not have the identifier of the specified device, the second determination submodule 112 may determine, from the candidate devices, the execution devices, for example, GPU-n (GPU-n includes an instruction set corresponding to the operation type NNN), which are used to execute the scalar logic computation macro 4, according to the operation type NNN of the scalar logic computation macro 4 and the resource information (included instruction set) of the candidate devices.

Instruction generation module 12

When there is one execution device, the scalar logic computation macro instruction may be split into multiple execution instructions, and the multiple execution instructions may be sent to the queue building module 15. For example, the plurality of execution instructions 2-1, 2-2, …, 2-n are generated from the scalar logic calculation of the data amount of the macro instruction 2 and the execution data amount of the execution device CPU-1. And generating a plurality of operating instructions 4-1, 4-2, … and 4-n according to the data volume of the scalar logic calculation macro instruction 4 and the operating data volume of the operating device GPU-n.

When it is determined that there is one execution device, a macro instruction may be calculated according to scalar logic to generate an execution instruction, and the execution instruction is sent to the queue building module 15. For example, one execution instruction 1-1 is generated by calculating the data amount of the macro instruction 1 and the execution data amount of the execution device CPU-2 according to scalar logic.

When a plurality of operating devices are determined, the scalar logic computation macroinstruction is split, an operating instruction corresponding to each operating device is generated, and the operating instruction is sent to the queue building module 15. For example, the data size of the macroinstruction 3, the operation data size of the operation device NPU-n, and the operation data size of the operation device NPU-2 are calculated based on scalar logic, a plurality of operation instructions 3-1, 3-2, …, 3-n are generated for the operation device NPU-n, and a plurality of operation instructions 3 ' -1, 3 ' -2, …, 3 ' -n are generated for the operation device NPU-2.

Queue building Block 15

When receiving the operation instruction, all the operation instructions to be executed by each operation device are sorted according to the queue sorting rule, a unique corresponding instruction queue is constructed for each operation device according to the sorted operation instructions, and the instruction queue is sent to the instruction dispatching module 16. In particular, the amount of the solvent to be used,

for an operation instruction 1-1 executed by the operation device CPU-2. The instruction queue CPU-2 "constructed corresponding to the execution device CPU-2 includes only the execution instructions 1-1.

For a plurality of execution instructions 2-1, 2-2, …, 2-n executed by the execution device CPU-1. And sequencing the plurality of operating instructions 2-1, 2-2, … and 2-n according to a queue sequencing rule, and constructing an instruction queue CPU-1' corresponding to the operating equipment CPU-1 according to the sequenced plurality of operating instructions 2-1, 2-2, … and 2-n.

For a plurality of execution instructions 3-1, 3-2, …, 3-n executed by the execution device NPU-n. The multiple operating instructions 3-1, 3-2, …, 3-n are sorted according to a queue sorting rule, and an instruction queue NPU-n' corresponding to the operating equipment NPU-n is constructed according to the sorted multiple operating instructions 3-n, …, 3-2, 3-1.

For the plurality of execution instructions 3 ' -1, 3 ' -2, …, 3 ' -n executed by the execution device NPU-2. The plurality of operating instructions 3 '-1, 3' -2, …, 3 '-n are ordered according to a queue ordering rule, and an instruction queue NPU-2 "corresponding to the operating device NPU-2 is constructed according to the ordered plurality of operating instructions 3' -n, …, 3 '-2, 3' -1.

For the plurality of execution instructions 4-1, 4-2, …, 4-n executed by the execution device GPU-n. And sequencing the plurality of operating instructions 4-1, 4-2, … and 4-n according to a queue sequencing rule, and constructing an instruction queue GPU-n' corresponding to the operating equipment GPU-n according to the sequenced plurality of operating instructions 4-1, 4-2, … and 4-n.

Instruction dispatch module 16

After the instruction queues are received, the operation instructions in each instruction queue are sequentially sent to corresponding operation equipment, so that the operation equipment executes the operation instructions. For example, the execution instruction 1-1 included in the instruction queue CPU-2 ″ is sent to its corresponding execution device CPU-2. And sequentially sending a plurality of running instructions 2-1, 2-2, … and 2-n in the instruction queue CPU-1' to the corresponding running equipment CPU-1. And sequentially sending the plurality of operating instructions 3-n, …, 3-2 and 3-1 in the instruction queue NPU-n' to the corresponding operating equipment NPU-n. And sequentially sending the plurality of running instructions 3 '-n, …, 3' -2 and 3 '-1 in the instruction queue NPU-2' to the corresponding running equipment NPU-2. And sequentially sending the multiple operating instructions 4-1, 4-2, … and 4-n in the queue GPU-n' to the corresponding operating equipment GPU-n.

After receiving the instruction queue, the operation device CPU-2, the operation device CPU-1, the operation device NPU-n and the operation device NPU-2 execute the operation instructions in sequence according to the arrangement sequence of the operation instructions in the instruction queue. Taking the operating device CPU-2 as an example, a specific process of executing the received operating instruction will be described. The running device CPU-2 comprises a control module, an execution module and a storage module. The control module comprises an instruction storage submodule, an instruction processing submodule and a storage queue submodule, and the execution module comprises a dependency relationship processing submodule, which refers to the relevant description about the operation equipment in detail.

Assume that the execution instruction 1-1 generated from the scalar logic computation macro instruction 1 is "@ XXX … …". After receiving the operation instruction 1-1, the operation device CPU-2 executes the operation instruction 1-1 as follows:

the control module of the operating device CPU-2 obtains data, a neural network model and an operating instruction 1-1. The instruction storage submodule is used for storing an operation instruction 1-1. The instruction processing submodule is used for analyzing the operation instruction 1-1, obtaining a plurality of analysis instructions such as an analysis instruction 0, an analysis instruction 1 and an analysis instruction 2, and sending the plurality of analysis instructions to the storage queue submodule and the execution module. The storage queue submodule is used for storing an operation instruction queue, the operation instruction queue comprises an analysis instruction 0, an analysis instruction 1, an analysis instruction 2 and other operation instructions which are required to be executed by the CPU-2 of the operation equipment, and all the instructions are sequentially arranged in the operation instruction queue according to the execution sequence. For example, the obtained sequence of the execution of the multiple analysis instructions is analysis instruction 0, analysis instruction 1, and analysis instruction 2, and there is an association relationship between analysis instruction 1 and analysis instruction 0.

After the execution module of the operating device CPU-2 receives the plurality of analysis instructions, the dependency relationship processing submodule judges whether an association relationship exists among the plurality of analysis instructions. And the dependency relationship processing submodule determines that the analysis instruction 1 and the analysis instruction 0 have an incidence relationship, caches the analysis instruction 1 into the instruction storage submodule, and extracts the analysis instruction 1 from the cache and sends the analysis instruction 1 to the execution module after determining that the analysis instruction 0 is executed, so that the execution module can execute the analysis instruction.

The execution module receives and executes the resolving instruction 0, the resolving instruction 1 and the resolving instruction 2 to complete the operation of the operation instruction 1-1.

The working process of the above modules can refer to the above related description.

Therefore, the device can be used in a cross-platform mode, the applicability is good, the instruction conversion speed is high, the processing efficiency is high, the error probability is low, and the cost of developing manpower and material resources is low.

The present disclosure provides a machine learning operation device, which may include one or more of the above scalar logic calculation instruction generation devices, and is configured to acquire data to be operated and control information from other processing devices, and execute a specified machine learning operation. The machine learning arithmetic device can obtain the scalar logic calculation macro instruction or the scalar logic calculation instruction to be executed from other machine learning arithmetic devices or non-machine learning arithmetic devices, and transmit the execution result to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one scalar logic computation instruction generation device is included, the scalar logic computation instruction generation devices can be linked and transmit data through a specific structure, for example, the data is interconnected and transmitted through a PCIE bus, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DDR4 controllers therein, where 64bit is used for data transmission and 8bit is used for ECC check in the 72-bit DDR4 controller. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600 MB/s.

In one embodiment, each group 393 of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transmission between the machine learning chip 389 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to a machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operation states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 illustrates a flow diagram of a scalar logic compute instruction generation method according to an embodiment of the present disclosure. As shown in fig. 6, the method is applied to the scalar logic calculation instruction generating apparatus described above, and includes step S41 and step S42. In step S41, an execution device that executes the scalar logic calculation macro is determined based on the received scalar logic calculation macro. In step S42, the macro instruction and the execution device are calculated based on scalar logic, and an execution instruction is generated.

In one possible implementation, step S41 may include: and when the scalar logic calculation macro instruction is determined to contain the identification of the specified device, and the resource of the specified device meets the execution condition for executing the scalar logic calculation macro instruction, determining the specified device as the running device. Wherein, the execution condition may include: the designated device contains a set of instructions corresponding to scalar logic computation macroinstructions.

In one possible implementation, the method may further include: and acquiring resource information of the alternative equipment. Wherein, step S41 may further include: and when the scalar logic calculation macro instruction is determined not to contain the identifier of the specified device, determining the running device for executing the scalar logic calculation macro instruction from the alternative devices according to the received scalar logic calculation macro instruction and the resource information of the alternative devices. Wherein the resource information may comprise a set of instructions contained by the alternative device.

In one possible implementation, step S41 may further include: and when the scalar logic calculation macro instruction is determined to contain the identification of the specified equipment and the resource of the specified equipment does not meet the execution condition for executing the scalar logic calculation macro instruction, determining the running equipment according to the scalar logic calculation macro instruction and the resource information of the alternative equipment.

In one possible implementation, the method may further include: and sequencing the operating instructions according to a queue sequencing rule, and constructing an instruction queue corresponding to the operating equipment according to the sequenced operating instructions.

In one possible implementation, the method may further include: and receiving a scalar logic calculation instruction to be executed, and generating a scalar logic calculation macro instruction according to the determined identification of the specified equipment and the scalar logic calculation instruction to be executed.

In one possible implementation, the method may further include: and sending the operation instruction to the operation equipment so as to enable the operation equipment to execute the operation instruction.

In one possible implementation manner, sending the execution instruction to the execution device to cause the execution device to execute the execution instruction includes: generating an assembly file according to the operation instruction; translating the assembly file into a binary file; and sending the binary file to the running equipment so that the running equipment executes the running instruction according to the binary file.

In one possible implementation, the resource information may include at least one of a storage capacity of the alternative device, a remaining storage capacity, and an instruction set included in the alternative device.

In one possible implementation, the running device may be one or any combination of a CPU, a GPU and an NPU.

In one possible implementation, the method may be applied in a CPU and/or NPU.

In one possible implementation, the scalar logic compute macro instruction may include at least one of the following instructions: scalar and compute macro, scalar or compute macro, scalar non-compute macro, scalar compare compute macro.

According to the scalar logic calculation instruction generation method provided by the embodiment of the disclosure, according to a received scalar logic calculation macro instruction, an operation device for executing the scalar logic calculation macro instruction is determined; and calculating the macro instruction and the running equipment according to the scalar logic to generate a running instruction. The method can be used in a cross-platform mode, and is good in applicability, high in instruction conversion speed, high in processing efficiency, low in error probability, and low in development labor and material cost.

The present disclosure also provides a scalar logic computation instruction execution method, which is applied to the above operating device, and the method includes: the data, the neural network model and the operation instruction are obtained through the operation equipment, the operation instruction is analyzed to obtain a plurality of analysis instructions, and the plurality of analysis instructions are executed according to the data to obtain an execution result.

In one possible implementation, the method may further include: the data and scalar data in the data are stored by the running device. The running equipment comprises a storage module, the storage module comprises any combination of a register and a cache, and the cache comprises a temporary cache. And the cache is used for storing data. And the register is used for storing scalar data in the data.

In one possible implementation, the method may further include:

storing the operation instruction through the operation equipment;

analyzing the operation instruction through the operation equipment to obtain a plurality of analysis instructions;

and storing an operation instruction queue through the operation equipment, wherein the operation instruction queue comprises an operation instruction and a plurality of analysis instructions, and the operation instruction queue operation instruction and the plurality of analysis instructions are sequentially arranged according to the executed sequence.

In one possible implementation, the method may further include:

the method comprises the steps that when the running equipment determines that the first analysis instruction and a zero analysis instruction before the first analysis instruction have an incidence relation, the first analysis instruction is cached, and after the execution of the zero analysis instruction is finished, the cached first analysis instruction is executed.

The method for analyzing the data comprises the following steps that an incidence relation exists between a first analysis instruction and a zeroth analysis instruction before the first analysis instruction: the first storage address interval for storing the data required by the first resolving instruction and the zeroth storage address interval for storing the data required by the zeroth resolving instruction have an overlapped area.

According to the scalar logic calculation instruction execution method provided by the embodiment of the disclosure, the operation equipment is used for acquiring data, the neural network model and the operation instruction, analyzing the operation instruction to obtain a plurality of analysis instructions, and executing the plurality of analysis instructions according to the data to obtain an execution result. The method can be used in a cross-platform mode, and is good in applicability, high in instruction conversion speed, high in processing efficiency, low in error probability, and low in development labor and material cost.

The present disclosure also provides a scalar logic computation instruction processing method, which is applied to a scalar logic computation instruction processing system including the scalar logic computation instruction generation apparatus and the execution device. The method comprises the scalar logic calculation instruction generation method applied to the scalar logic calculation instruction generation device and the scalar logic calculation instruction execution method applied to the running equipment. The method can be used in a cross-platform mode, and is good in applicability, high in instruction conversion speed, high in processing efficiency, low in error probability, and low in development labor and material cost.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some interfaces, and may be in an electrical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present disclosure may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a form of hardware or a form of a software program module.

The integrated modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An apparatus for generating scalar logical compute instructions, the apparatus comprising:

2. The apparatus of claim 1, wherein the device determination module comprises:

a first determining submodule, configured to determine, when it is determined that the scalar logic computation macro includes an identifier of a specified device and a resource of the specified device satisfies an execution condition for executing the scalar logic computation macro, the specified device as the running device,

wherein the execution condition includes: the designated device includes a set of instructions therein corresponding to the scalar logic compute macroinstructions.

3. The apparatus of claim 2, further comprising:

a resource obtaining module for obtaining resource information of the alternative device,

the device determination module further includes:

a second determining submodule, configured to determine, when it is determined that the scalar logic computation macro does not include the identifier of the specified device, an operating device for executing the scalar logic computation macro from the candidate device according to the received scalar logic computation macro and the resource information of the candidate device,

wherein the resource information comprises a set of instructions contained by the alternative device.

4. The apparatus of claim 3, wherein the device determination module further comprises:

and a third determining submodule, configured to determine, when it is determined that the scalar logic calculation macro includes the identifier of the specified device and the resource of the specified device does not satisfy the execution condition for executing the scalar logic calculation macro, an operating device according to the scalar logic calculation macro and the resource information of the candidate device.

5. The apparatus of claim 1, further comprising:

and the queue construction module is used for sequencing the operating instructions according to a queue sequencing rule and constructing an instruction queue corresponding to the operating equipment according to the sequenced operating instructions.

6. The apparatus of claim 2, further comprising:

and the macro instruction generation module is used for receiving a scalar logic calculation instruction to be executed and generating the scalar logic calculation macro instruction according to the determined identifier of the specified equipment and the scalar logic calculation instruction to be executed.

7. The apparatus of claim 1, further comprising:

an instruction dispatching module, configured to send the execution instruction to the execution device, so that the execution device executes the execution instruction,

wherein the instruction dispatch module comprises:

the instruction assembly submodule is used for generating an assembly file according to the operation instruction;

the assembly translation submodule is used for translating the assembly file into a binary file;

and the instruction sending submodule is used for sending the binary file to the operating equipment so as to enable the operating equipment to execute the operating instruction according to the binary file.

8. The apparatus of claim 1,

the running equipment is one or any combination of a CPU, a GPU and an NPU

The device is arranged in a CPU and/or an NPU;

the scalar logic compute macro instructions include at least one of: scalar and compute macro, scalar or compute macro, scalar non-compute macro, scalar compare compute macro.

9. A machine learning arithmetic device, the device comprising:

one or more scalar logic computation instruction generation devices according to any one of claims 1 to 8, for acquiring data to be computed and control information from other processing devices, executing a specified machine learning operation, and transmitting the execution result to the other processing devices through an I/O interface;

10. A combined treatment device, characterized in that the device comprises:

the machine learning computing device, universal interconnect interface, and other processing device of claim 9;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein, the combination processing device further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

11. The utility model provides a board card, its characterized in that, the board card includes: memory device, interface device and control device and machine learning chip comprising a machine learning arithmetic device according to claim 9 or a combined processing device according to claim 10;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

12. A method of scalar logic computation instruction generation, the method comprising:

13. The method of claim 12, wherein determining, from the received scalar logic compute macro, an execution device to execute the scalar logic compute macro comprises:

determining a designated device as the running device when determining that the scalar logic computation macro instruction comprises an identification of the designated device and the resources of the designated device meet the execution condition for executing the scalar logic computation macro instruction,

14. The method of claim 13, further comprising:

the resource information of the alternative device is acquired,

the method for determining the running equipment for executing the scalar logic calculation macro instruction according to the received scalar logic calculation macro instruction comprises the following steps:

when the scalar logic calculation macro instruction is determined not to contain the identifier of the specified device, determining an operating device for executing the scalar logic calculation macro instruction from the alternative device according to the received scalar logic calculation macro instruction and the resource information of the alternative device,

15. The method of claim 14, wherein determining, from the received scalar logic compute macro, an execution device to execute the scalar logic compute macro comprises:

and when the scalar logic calculation macro instruction is determined to contain the identifier of the specified equipment and the resource of the specified equipment does not meet the execution condition for executing the scalar logic calculation macro instruction, determining running equipment according to the scalar logic calculation macro instruction and the resource information of the alternative equipment.

16. The method of claim 12, further comprising:

and sequencing the operating instructions according to a queue sequencing rule, and constructing an instruction queue corresponding to the operating equipment according to the sequenced operating instructions.

17. The method of claim 13, further comprising:

and receiving a scalar logic calculation instruction to be executed, and generating the scalar logic calculation macro instruction according to the determined identification of the specified equipment and the scalar logic calculation instruction to be executed.

18. The method of claim 12, further comprising:

sending the operation instruction to the operation device to enable the operation device to execute the operation instruction,

wherein, sending the operation instruction to the operation device to enable the operation device to execute the operation instruction comprises:

generating an assembly file according to the operation instruction;

translating the assembly file into a binary file;

and sending the binary file to the operating equipment so that the operating equipment executes the operating instruction according to the binary file.

19. The method of claim 12,

the running equipment is one or any combination of a CPU, a GPU and an NPU;

the method is applied to a CPU and/or an NPU;