CN111078288A

CN111078288A - RISC core storage access instruction circuit in command processor

Info

Publication number: CN111078288A
Application number: CN201911147447.0A
Authority: CN
Inventors: 韩一鹏; 牛少平; 魏艳艳; 郝冲; 邓艺
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-04-28

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a RISC core memory access instruction circuit in a command processor (CMD). The invention includes LSU _ R (access interface register Unit), LSU _ G (access GSU Unit), LSU _ D (access Dcache Unit). The LSU unit is used for realizing data exchange between the RISC core and different memories, and the LSU unit can be used for accessing and storing: interface registers, GSU units, Dcache units. The present LSU is capable of supporting pipelining while being able to handle data exchanges for different memories.

Description

RISC core storage access instruction circuit in command processor

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to a RISC core memory access instruction circuit in a command processor (CMD).

Background

In a RISC core in a command processor (CMD), an LSU unit is used to implement data exchange between the RISC core and an external memory. Data exchange between the RISC core and the memory occurs frequently, and the performance of the LSU also substantially affects the operating speed of the entire RISC core. This requires the LSU to support pipelining while handling data exchanges for different memories.

Disclosure of Invention

The purpose of the invention is:

the present invention provides a RISC core memory access instruction circuit in a command processor (CMD) to enable data exchange between the RISC core and a memory.

The technical solution of the invention is as follows:

a RISC core memory access instruction circuit in a command processor (CMD), characterized by: LSU _ R, LSU _ G, LSU _ D has 3 cells in total.

The external instruction fetch decoding unit sends the received LD and ST instructions to the LSU _ R unit, and the LSU _ R unit converts the LD and ST instructions into loading or storage access to an interface register and replies a completion signal to instruction fetch decoding according to a fixed period;

the external instruction fetch decoding unit sends the received LD.G and ST.G instructions to the LSU _ G unit, the LSU _ G unit converts the instructions into loading or storage access to the GSU, 128 bits can be accessed once, and after the GSU loading or storage is finished, the LSU _ G unit replies a finishing signal of the GSU to the instruction fetch decoding unit;

the external instruction fetching decoding unit sends the received LD.D and ST.D instructions to the LSU _ D unit, the LSU _ D unit converts the instructions into load or storage access to Dcache, and after the load or storage is finished, the LSU _ G unit replies a finishing signal of Dcache to the instruction fetching decoding unit.

Drawings

FIG. 1 is a block diagram of the present invention;

wherein: 1. an LSU _ R unit; 2. an LSU _ G unit; 3. LSU _ D unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The technical scheme of the invention is further described in detail by combining the drawings and the specific embodiments in the specification.

The technical solution of the invention is as follows:

in one embodiment of the present invention, as shown in fig. 1, a RISC core memory access instruction circuit in a command processor (CMD) is provided, which includes an LSU _ R unit 1, an LSU _ G unit 2, and an LSU _ D unit 3.

The external instruction fetch decoding unit sends the received LD and ST instructions to the LSU _ R unit 1, and the LSU _ R unit 1 converts the LD and ST instructions into loading or storage access to an interface register and replies a completion signal to instruction fetch decoding according to a fixed period;

the external instruction fetch decoding unit sends the received LD.G and ST.G instructions to the LSU _ G unit 2, the LSU _ G unit 2 converts the instructions into load or storage access to the GSU, 128 bits can be accessed once, and after the GSU load or storage is finished, the LSU _ G unit 2 replies a finishing signal of the GSU to the instruction fetch decoding unit;

the external instruction fetch decoding unit sends the received LD.D and ST.D instructions to the LSU _ D unit 3, the LSU _ D unit 3 converts the instructions into load or store access to Dcache, and after the load or store is completed, the LSU _ G unit 2 returns a completion signal of Dcache to the instruction fetch decoding unit.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A RISC core memory access instruction circuit in a command processor, comprising: the LSU _ R unit comprises an LSU _ R unit (1), an LSU _ G unit (2) and an LSU _ D unit (3).

2. A RISC core memory access instruction circuit in a command processor of claim 1, wherein: the LSU _ R unit (1) is provided with an access interface for an interface register, and the RISC core loads or stores the interface register through LD and ST instructions through the LSU _ R unit (1).

3. A RISC core memory access instruction circuit in a command processor of claim 1, wherein: the LSU _ G unit (2) is provided with an access interface for the GSU module, the RISC core loads or stores the GSU module through the LSU _ G unit (2) through LD.G and ST.G instructions, and the access bit width is 128 bits.

4. A RISC core memory access instruction circuit in a command processor of claim 1, wherein: the LSU _ D unit (3) has an access interface to Dcache, and the RISC core loads or stores Dcache through LD and ST instructions via the LSU _ R unit (1).