CN111064912A - Frame format conversion circuit and method - Google Patents
Frame format conversion circuit and method Download PDFInfo
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- CN111064912A CN111064912A CN201911330669.6A CN201911330669A CN111064912A CN 111064912 A CN111064912 A CN 111064912A CN 201911330669 A CN201911330669 A CN 201911330669A CN 111064912 A CN111064912 A CN 111064912A
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Abstract
The application provides a frame format conversion circuit and a frame format conversion method, and relates to the technical field of data processing. The frame format conversion circuit comprises a metal wire switching network and N groups of frame data processing units, wherein the N groups of frame data processing units are sequentially cascaded, the metal wire switching network is used for acquiring frame data before conversion of an ith group of frame data processing unit, the ith group of frame data processing unit is any one of the N groups of frame data processing units except the Nth group of frame data processing unit, N is an integer larger than 1, the metal wire switching network is also used for transmitting converted frame data obtained after the frame data before conversion is mapped according to a target format to the Nth group of frame data processing unit, and the Nth group of frame data processing unit is used for outputting the converted frame data. The frame format conversion circuit and the method do not need to use a large-scale data selector, reduce routing and solve the problem of routing congestion in the frame format conversion circuit.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to a frame format conversion circuit and a method.
Background
The frame format conversion circuit is a circuit that converts input frame data into a desired format and outputs the converted frame data.
At present, a frame format conversion circuit generally stores N-beat frame data by using N register groups, collects complete frame data in the nth beat, performs data mapping according to a new frame format when beats, and finally selectively outputs the data through an N-select selector, thereby implementing conversion processing on the frame data.
However, in this processing method, a large number of metal lines are required for layout, and a large number of large data selectors (N-out-of-one selectors) are required, which causes a problem of routing congestion in the conventional frame format conversion circuit.
Disclosure of Invention
The present application is directed to a frame format conversion circuit and a method thereof, so as to solve the problem of routing congestion in the frame format conversion circuit in the prior art.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in one aspect, an embodiment of the present application provides a frame format conversion circuit, where the frame format conversion circuit includes a metal wire switching network and N sets of frame data processing units, each set of frame data processing units is connected to the metal wire switching network, and the N groups of frame data processing units are cascaded in sequence, the metal wire switching network is used for acquiring the frame data before transformation of all the ith group of frame data processing units, wherein the ith group of frame data processing units is any one of the N groups of frame data processing units except the Nth group of frame data processing units, N is more than i and is an integer more than 1, the metal wire switching network is further configured to transmit the transformed frame data obtained by mapping the frame data before transformation according to the target format to an nth group of frame data processing unit, and the nth group of frame data processing unit is configured to output the transformed frame data.
Further, the nth frame data processing unit includes a first selection array and a first buffer array, the first selection array is connected to the first buffer array, and the first selection array is respectively connected to the metal wire switching network and the nth-1 frame data processing unit, where the first selection array is configured to receive pre-transform frame data transmitted by the nth-1 frame data processing unit and post-transform frame data transmitted by the metal wire switching network, and select the post-transform frame data as target data from the pre-transform frame data and the post-transform frame data to transmit the post-transform frame data to the first buffer array, and the first buffer array is configured to output the post-transform frame data corresponding to the ith frame data processing unit.
Further, the first selection array includes a plurality of first selectors, the buffer array includes a plurality of first registers, the number of the first selectors is the same as that of the first registers, and an output end of each of the first selectors is connected to one of the first registers, wherein a first input end of each of the first selectors is connected to the metal wire switching network, a second input end of each of the first selectors is connected to the N-1 th group of frame data processing unit, and each of the first selectors is configured to select the transformed frame data transmitted by the metal wire switching network as target data and transmit the transformed frame data to a corresponding first register for storage, and each of the first registers is configured to output the transformed frame data.
Furthermore, the plurality of first selectors are all connected with a control line, and each first selector is used for receiving a first control signal through the control line, so that each first selector takes the data received by the first input end as target data according to the first control signal, and transmits the target data to the corresponding first register for storage.
Further, the plurality of first selectors are connected in sequence, and any one of the first selectors is connected to the control line.
Further, the ith group of frame data processing units comprises a second selection array and a second buffer array, the second selection array is connected with the second buffer array, and the second selection array is respectively connected with the metal wire switching network and the (i-1) th group of frame data processing units, wherein, when i is 1, the second selection array is respectively connected with the metal wire switching network and the frame data input end, the second selection array is used for receiving the frame data before transformation transmitted by the i-1 group frame data processing unit or the frame data input end and the frame data after transformation transmitted by the metal wire switching network, and selecting the frame data before transformation as target data from the frame data before transformation, the second buffer array is used for outputting the frame data before transformation to the (i +1) th group of frame data processing units.
Further, the second selection array comprises a plurality of second selectors, the second cache array comprises a plurality of second registers, the number of the second selectors is the same as that of the second registers, and the output end of each second selector is connected with one second register, wherein,
a first input end of the second selector is connected with the metal wire switching network, a second input end of the second selector is connected with the i-1 th group of frame data processing units or frame data input ends, and each second selector is used for selecting frame data before transformation as target data and transmitting the frame data before transformation to a corresponding second register for storage;
each second register is used for outputting the frame data before transformation to an (i +1) th group of frame data processing units.
Furthermore, the plurality of second selectors are all connected with a control line, and each second selector is used for receiving a second control signal through the control line, so that each second selector takes the received data at the second input end as target data according to the second control signal, and transmits the target data to the corresponding second register for storage.
Furthermore, each group of the frame data processing units is connected with a clock generator; the ith group of frame data processing units are used for transmitting the frame data before conversion to the (i +1) th group of frame data processing units in the next clock cycle after receiving the frame data before conversion in the current clock cycle, and the nth group of frame data processing units are used for outputting the frame data after conversion in the next clock cycle after receiving the frame data after conversion in the current clock cycle.
On the other hand, the embodiment of the present application provides a frame format conversion method, which is applied to a frame format conversion circuit, where the frame format conversion circuit includes a metal wire switching network and N groups of frame data processing units, each group of the frame data processing units is connected to the metal wire switching network, and the N groups of the frame data processing units are sequentially cascaded; the method comprises the following steps:
the metal wire switching network acquires frame data before transformation of all the ith group of frame data processing units, wherein the ith group of frame data processing units are any one of the N group of frame data processing units except the Nth group of frame data processing units, N is more than i, and N is an integer more than 1;
the metal wire switching network maps the frame data before conversion according to a target format and then transmits the frame data to the Nth group of frame data processing unit;
and the Nth group of frame data processing unit outputs the transformed frame data.
Compared with the prior art, the method has the following beneficial effects:
the embodiment of the application provides a frame format conversion circuit and a method, the frame format conversion circuit comprises a metal wire switching network and N groups of frame data processing units, each group of frame data processing units is connected with the metal wire switching network, the N groups of frame data processing units are sequentially cascaded, the metal wire switching network is used for acquiring frame data before conversion of an ith group of frame data processing units, the ith group of frame data processing units are any one of the N groups of frame data processing units except the Nth group of frame data processing units, N is an integer larger than 1, the metal wire switching network is also used for transmitting the frame data after conversion, which is obtained after mapping the frame data before conversion according to a target format, to the Nth group of frame data processing units, and the Nth group of frame data processing units are used for outputting the frame data after conversion. Because the N groups of frame data processing units in the frame format conversion circuit adopt the cascade mode and the Nth group of frame data processing units always output the data processed by the metal wire switching network, a large-scale data selector is not needed, the routing is reduced, and the problem of routing congestion in the frame format conversion circuit is solved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a circuit diagram of a frame format conversion circuit according to the prior art provided in an embodiment of the present application.
Fig. 2 is a timing diagram corresponding to a frame format conversion circuit in the prior art according to an embodiment of the present application.
Fig. 3 is a circuit diagram of a frame format conversion circuit according to an embodiment of the present application.
Fig. 4 is a timing diagram corresponding to a frame format conversion circuit according to an embodiment of the present application.
Fig. 5 is a schematic flow chart of a frame format conversion method according to an embodiment of the present application.
In the figure: 100-frame format conversion circuit; 110-a frame data processing unit; 120-wire switching network.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
A frame format conversion circuit is a circuit that converts input frame data into a desired format and outputs the converted frame data, and is widely used in a correlation system for data processing. For example, the frame data of 0101010101010101 is converted into 1010101010101010 or 1111111100000000, etc. It should be noted that the above example is only one implementation of the frame format conversion circuit, and in practical applications, the frame format conversion circuit may also convert the input frame data into frame data of other formats, and it is only necessary to satisfy that both bits 0 and 1 in the input frame data are the same as the numbers of bits 0 and 1 in the converted frame data. That is, if the number of bits 0 and the number of bits 1 of the input frame data are 5, the output transformed frame data may have various forms such as 1111100000, 1010101010, 10010010111, and the like.
A specific circuit diagram of a current frame format conversion circuit is shown in fig. 1, wherein, assuming that a single frame contains 10240-bit data and the bit width of a data input/output bus is 256 bits, the single frame data is divided into 10240/256 beats in total, that is, 40 beats are divided in total. As shown in fig. 1, the conventional single frame format conversion circuit requires 256 × 40+1 to 10496 registers, and 10240 × 4 to 40960 metal traces (internal traces not including registers and selectors); 256 of the 40-to-1 selectors and 10240 of the 2-to-1 selectors are required. Understandably, it requires a large number of metal wires and large data selectors (1-out-of-40 selectors), and has the problem of routing congestion.
The following explains the operation principle of the conventional frame format conversion circuit:
please refer to fig. 2, fig. 2 is a timing diagram corresponding to the frame format conversion circuit during operation, where the black portion indicates frame data output at this time, it can be understood that, in the conventional frame format conversion circuit, after receiving each beat of data, the data is buffered in the input register array, the metal wire switching network can obtain corresponding frame data in the input register array, convert the frame data according to a target format, and transmit the frame data to k two-out-of-one selector sets, the two-out-of-one selector set selects data transmitted by the metal wire switching network and buffers the data into k register sets, after collecting the frame data in the k beat, perform data mapping according to a new frame format, and then sequentially select and output the converted k beat of frame data through the 40-out-of-1 selector, so as to implement format conversion of the frame data, where k is a bit width number.
In other words, the k-beat frame data are respectively stored by k register groups, complete frame data are collected at the k-th beat, then data mapping is carried out according to a new frame format when beats, and the data are selectively output through a counter.
Although the circuit can realize the conversion of the frame data format, the application range is limited. In practical applications, as the process is continuously developed, the chip process is gradually developed toward more miniaturization. The traditional frame format conversion circuit can be applied to a 40nm chip manufacturing process, and the problem of routing congestion is not obvious. However, as the process evolves, the chip fabrication processes of 28nm and 16nm have appeared, and on this basis, the conventional frame format conversion circuit has a significant problem of routing congestion and deteriorates sharply as the frame capacity becomes larger.
In view of the above, referring to fig. 3 and fig. 4, an embodiment of the present invention provides a new frame format conversion circuit 100, where the frame format conversion circuit 100 includes a metal wire switching network 120 and N sets of frame data processing units 110, each set of frame data processing units 110 is connected to the metal wire switching network 120, and the N sets of frame data processing units 110 are sequentially cascaded. Through the frame format conversion circuit provided by the application, the conversion of the frame data format can be realized, the wiring is simpler, and the problem of routing congestion of the frame format conversion circuit is solved. In other words, compared with the conventional frame format conversion circuit, the frame format conversion circuit provided by the embodiment of the invention can achieve the same effect, and the wiring is simpler.
The frame format conversion circuit 100 provided by the present invention has an operation principle that the metal wire switching network 120 obtains frame data before conversion of all the ith frame data processing units 110, wherein the ith frame data processing unit 110 is any one of the N frame data processing units 110 except the nth frame data processing unit 110, N is greater than i and N is an integer greater than 1; and the wire switching network 120 is configured to map the frame data before conversion according to a target format to obtain converted frame data, transmit the converted frame data to the nth frame data processing unit 110, and then the nth frame data processing unit 110 is configured to output the converted frame data, thereby implementing conversion of a frame data format.
That is, the frame format conversion circuit 100 according to the present invention always outputs the converted frame data through the nth group of frame data processing units 110, so that it is not necessary to provide an N-out-of-one selector, thereby eliminating a large-scale data selector and accordingly reducing metal lines. As can be seen from a comparison between the conventional frame format conversion circuit in fig. 1 and the frame format conversion circuit provided in the present application in fig. 3, the conventional frame format conversion circuit needs 256 × 40+1 (10496 bit) registers, 10240 × 4 (40960 metal traces (internal traces not including registers and selectors), 256 40-from-1 selectors, and 10240 2-from-1 selectors; the frame format conversion circuit provided by the present application requires 256 × 41 ═ 10496bit registers, 10240 × 3 ═ 30720 metal traces (not including the registers and traces inside the selectors), and 10240 2-to-1 selectors. Compared with the existing frame format conversion circuit, the frame format conversion circuit provided by the application optimizes 10240 metal wires and 256 selectors 1 from 40, namely reduces the number of the metal wires by 25%, and greatly improves the difficulty of physical layout and wiring.
As an implementation manner of the present application, the nth frame data processing unit 110 includes a first selection array and a first buffer array, the first selection array is connected to the first buffer array, and the first selection array is respectively connected to the metal wire switching network 120 and the nth-1 frame data processing unit 110, where the first selection array is configured to receive pre-transformed frame data transmitted by the nth-1 frame data processing unit 110 and transformed frame data transmitted by the metal wire switching network 120, and select the transformed frame data from the pre-transformed frame data and the transformed frame data as target data, so as to transmit the transformed frame data to the first buffer array, and finally output the format-transformed frame data.
Optionally, the first selection array includes a plurality of first selectors, where the first selectors may be alternative selectors, the cache array includes a plurality of first registers, the number of the first selectors is the same as that of the first registers, and an output end of each first selector is connected to one first register.
The first selector is taken as an alternative selector, the alternative selector includes a first input end and a second input end, wherein the first input end of the first selector is connected to the metal wire switching network 120, the second input end of the first selector is connected to the N-1 th group of frame data processing unit 110, and each first selector is configured to select the transformed frame data transmitted by the metal wire switching network 120 as the target data, and transmit the transformed frame data to the corresponding first register for storage.
In addition, in order to control the first selectors, the plurality of first selectors provided by the present application are all connected to a control line, and each first selector receives a first control signal through the control line, so that each first selector takes data received by the first input terminal as target data according to the first control signal, and transmits the target data to the corresponding first register for storage.
As an implementation manner of the present application, each first selector is connected to a control line, so that each first selector can select target data according to a first control signal. As another implementation manner of the present application, a plurality of first selectors are connected in sequence, and any one of the first selectors is connected to a control line.
Meanwhile, as a possible implementation manner of the present application, the ith frame data processing unit 110 includes a second selection array and a second buffer array, the second selection array is connected to the second buffer array, and the second selection array is respectively connected to the metal wire switching network 120 and the (i-1) th frame data processing unit 110, where when i is equal to 1, the second selection array is respectively connected to the metal wire switching network 120 and the frame data input end. The second selection array is configured to receive the pre-transformed frame data transmitted by the i-1 th group frame data processing unit 110 or the frame data input terminal and the transformed frame data transmitted by the wire switching network 120, and select the pre-transformed frame data as the target data from the pre-transformed frame data to transmit the pre-transformed frame data to the second buffer array, and the second buffer array is configured to output the pre-transformed frame data to the i +1 th group frame data processing unit 110.
Optionally, the second selection array includes a plurality of second selectors, and the second selectors may also select an alternative selector, the second cache array includes a plurality of second registers, the number of the second selectors is the same as that of the second registers, and the output end of each second selector is connected to one second register, wherein the first input end of the second selector is connected to the metal wire switching network 120, the second input end of the second selector is connected to the i-1 th group frame data processing unit 110 or the frame data input end, and each second selector is configured to select frame data before transformation as target data, and transmit the frame data before transformation to the corresponding second register for storage; each of the second registers is used to output the frame data before transformation to the (i +1) th group frame data processing unit 110.
Meanwhile, the plurality of second selectors are all connected with a control line, and each second selector is used for receiving a second control signal through the control line, so that each second selector takes the received data of the second input end as target data according to the second control signal, and transmits the target data to the corresponding second register for storage.
It is understood that there are two connection manners between the second selector and the control line, one is that each first selector is connected to the control line, so that each first selector can select the target data according to the first control signal. The other type is that a plurality of first selectors are connected in sequence, and any one first selector is connected with a control line.
It should be noted that the frame format conversion circuit 100 provided in this application operates according to the clock cycle, that is, each group of frame data processing units 110 is connected to a clock generator (not shown), where the i-th group of frame data processing units 110 is configured to transmit the frame data before conversion to the frame data processing units 110 of the i + 1-th group in the next clock cycle after receiving the frame data before conversion in the current clock cycle, and the N-th group of frame data processing units 110 is configured to output the frame data after conversion in the next clock cycle after receiving the frame data after conversion in the current clock cycle.
As an optional implementation manner, the frame format conversion circuit 100 further includes an input array, the input array is respectively connected to the first group of frame data processing units 110 and the metal wire switching network 120, and as a possible implementation manner of the present application, the input array is a plurality of registers, and the input array is used for buffering the input frame data.
Taking fig. 3 as an example to explain in detail, it should be understood that fig. 3 is only one implementation manner of the present application, and in practical applications, the frame format conversion circuit 100 may also be another implementation manner. For example, the present application is described by taking an example that a single frame includes 10240-bit data, and the data input/output bus shown in fig. 3 has a width of 256 bits, so that it needs 10240/256 ═ 40 groups of frame data processing units 110 in total. In other implementations, the data input/output bus may have other values, such as 128 bits, and accordingly, in this case, 10240/128-80 frames of the data processing unit 110 are needed altogether, and so on.
In fig. 3, the frame format conversion circuit 100 includes 40 sets of frame data processing units 110 in total, the first set of frame data processing units 110 being D0, the second set of frame data processing units 110 being D1 …, the 40 th set of frame data processing units 110 being D39. Meanwhile, the width of the input/output bus of each group of frame data processing units 110 is 256 bits, taking D0 as an example, which includes 256 total alternatives and registers D0_0 and D0_1 … D0_255, the alternatives numbered D0_0 and D0_1 … D0_255 are connected in sequence, and the alternative selector numbered D0_0 is connected to the control line. In addition, in the alternative selector in each group of frame data processing units 110, the first input end is connected to the metal wire switching network 120, and the second input end is connected to the register of the previous group of frame data processing units 110, wherein in the first group of frame data processing units 110, the second input end of the alternative selector is connected to the input array, and meanwhile, the other registers except the register in the 40 th group of frame data processing units 110 are connected to the metal wire switching network 120.
For the sake of convenience, it is assumed that each single frame contains 10240-bit data of 0, i.e. each frame has 10240-bit 0, and the data input line width is 256 bits, the frame data is divided into 40 beats, each beat is 256-bit 0. Meanwhile, the target format of the frame data is 10240 1, that is, the frame data is transformed from 10240 0 to 10240 1 by the frame format transforming circuit 100 provided in the present application.
The frame format conversion circuit 100 operates according to a clock signal, when the operation starts, the first beat frame data is buffered to the input array, that is, the frame data stored in the registers numbered Din _0 and Din _1 … Din _255 are all 0, when a first clock cycle elapses, for example, when a rising edge of the clock signal is detected for the first time, the input array sends the frame data to the first group of frame data processing units 110, and the one-out-of-two selector of the first group of frame data processing units 110 obtains the second control signal according to the controller line, and further selects the frame data of the input array and buffers the frame data in the register. Meanwhile, the input array inputs the second beat frame data at this time. That is, at this time, data is buffered in D0_0 and D0_1 … D0_255, data is all 0, data is also buffered in Din _0 and Din _1 … Din _255, data is also all 0, and data is not buffered in D1-D39 at this time.
When the second clock cycle passes, the data in D0_0 and D0_1 … D0_255 are buffered to D1_0, D1_1 … D1_255, and the data in Din _0 and Din _1 … Din _255 are buffered to D0_0 and D0_1 … D0_255, that is, the data in D0_0, D0_1 … D0_255, D1_0 and D1_1 … D1_255 are all buffered with 0, and the data in D2-D39 are all not buffered at this time, and so on.
When the fourteenth clock cycle elapses, the data in D38_0 and D38_1 … D38_255 are transmitted to the alternative selector of the 40 th group of frame data processing units 110, and the wire switch network 120 receives the data in D38_0 and D38_1 … D38_255 and maps the data according to the target format, where the processed data is 256 pieces of 1, and at the same time, the wire switch network 120 transmits the processed data to the first input terminal of the alternative selector of the 40 th group of frame data processing units 110. And as can be seen from Cnt40<39 in the figure, the control signal of the alternative selector in the first 39 frame data processing units 110 is not the same as the control signal of the alternative selector in the 40 th frame data processing unit 110. That is, in the embodiment, the first 39 sets of frame data processing units 110 select the data at the second input terminal as the target data and buffer the target data into the corresponding register. The alternative selector in the 40 th group of frame data processing units 110 selects the data at the first input terminal as the target data and buffers the target data in the corresponding register. At this time, the data buffered in D0-D38 are all 0, and the data buffered in D39_0, D39_1 … D39_255 are all 1.
When the next clock cycle, D39_0, D39_1 … D39_255 output 256 1's, effecting a transformation of the frame data, and so on.
The timing diagram corresponding to the shift frame conversion circuit in operation provided by the application is consistent with the timing diagram corresponding to the conventional shift frame conversion circuit in operation.
Therefore, the frame format conversion circuit provided by the application actually shifts frame data in each clock cycle through a pipeline working mode, the frame data are shifted and cached into the N-level data storage devices, then remapping is carried out in the last beat according to a new frame format, the data to be output in the beat are mapped to the last-level storage device, the data in the penultimate beat are mapped to the penultimate memory, and so on, so that the new data can be continuously shifted to the cache array, meanwhile, the data newly mapped in the previous round is continuously output, and the conversion of the frame data is realized.
Meanwhile, it should be further noted that, in other possible implementations, the metal-switching network may also not convert the data of D38_0 according to the target format and transmit the converted data to D39_0, but convert the data of other beats according to the target format and transmit the converted data to D39_0, for example, convert the data buffered in D0_0 according to the target format and transmit the converted data to D39_0, and output the data through D39_ 0.
Second embodiment
Referring to fig. 5, an embodiment of the present application further provides a frame format conversion method, which is applied to the frame format conversion circuit of the first embodiment, where the frame format conversion circuit includes a metal wire switching network and N sets of frame data processing units, each set of frame data processing units is connected to the metal wire switching network, and the N sets of frame data processing units are sequentially cascaded; the method comprises the following steps:
s101, the metal wire switching network acquires frame data before transformation of all the ith frame data processing units, wherein the ith frame data processing unit is any one of the N frame data processing units except the Nth frame data processing unit, N is more than i, and N is an integer more than 1;
s102, the metal wire switching network maps the frame data before conversion according to a target format and transmits the frame data to the Nth group of frame data processing unit;
s103, the Nth group of frame data processing unit outputs the transformed frame data.
Since the frame format conversion circuit has been specifically described in the above embodiments, the description of the present application is omitted.
To sum up, the embodiment of the present application provides a frame format conversion circuit and a method, where the frame format conversion circuit includes a metal wire switching network and N sets of frame data processing units, each set of frame data processing units is connected to the metal wire switching network, and the N sets of frame data processing units are sequentially cascaded, and the metal wire switching network is configured to acquire frame data before conversion of an i-th set of frame data processing unit, where the i-th set of frame data processing unit is any one of the N-th set of frame data processing units except for the N-th set of frame data processing unit, and N is an integer greater than 1, the metal wire switching network is further configured to transmit converted frame data obtained after mapping frame data before conversion according to a target format to the N-th set of frame data processing unit, and the N-th set of frame data processing unit is configured to output the converted frame data. Because the N groups of frame data processing units in the frame format conversion circuit adopt the cascade mode and the Nth group of frame data processing units always output the data processed by the metal wire switching network, a large-scale data selector is not needed, the routing is reduced, and the problem of routing congestion in the frame format conversion circuit is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A frame format conversion circuit is characterized in that the frame format conversion circuit comprises a metal wire switching network and N groups of frame data processing units, each group of frame data processing units is connected with the metal wire switching network, and the N groups of frame data processing units are sequentially cascaded;
the metal wire switching network is used for acquiring frame data before transformation of all the ith group of frame data processing units, wherein the ith group of frame data processing units are any one of the N group of frame data processing units except the Nth group of frame data processing units, N is more than i, and N is an integer more than 1;
the metal wire switching network is also used for mapping the frame data before conversion according to a target format and then transmitting the frame data to the Nth group of frame data processing unit;
and the Nth group of frame data processing units are used for outputting the transformed frame data.
2. The frame format conversion circuit according to claim 1, wherein the N-th group of frame data processing units includes a first selection array and a first buffer array, the first selection array is connected to the first buffer array, and the first selection array is connected to the metal wire switching network and the N-1-th group of frame data processing units, respectively, wherein,
the first selection array is configured to receive pre-transform frame data transmitted by the N-1 th group of frame data processing units and post-transform frame data transmitted by the metal wire switching network, and select the post-transform frame data as target data to transmit the post-transform frame data to the first cache array;
the first buffer array is used for outputting the transformed frame data corresponding to the ith group of frame data processing unit.
3. The frame format conversion circuit of claim 2, wherein the first selection array comprises a plurality of first selectors, the buffer array comprises a plurality of first registers, the number of the first selectors and the number of the first registers are the same, and an output terminal of each of the first selectors is connected to one of the first registers, wherein,
a first input end of the first selector is connected with the metal wire switching network, and a second input end of the first selector is connected with the N-1 th framing data processing unit;
each first selector is used for selecting the transformed frame data transmitted by the metal wire switching network as target data and transmitting the transformed frame data to a corresponding first register for storage;
each of the first registers is configured to output the transformed frame data.
4. The frame format conversion circuit according to claim 3, wherein the plurality of first selectors are each connected to a control line;
each first selector is used for receiving a first control signal through the control line, so that each first selector takes the data received by the first input end as target data according to the first control signal, and transmits the target data to the corresponding first register for storage.
5. The frame format conversion circuit according to claim 4, wherein the plurality of first selectors are connected in sequence, and any one of the first selectors is connected to the control line.
6. The frame format conversion circuit according to claim 1, wherein the ith group of frame data processing units includes a second selection array and a second buffer array, the second selection array is connected to the second buffer array, and the second selection array is respectively connected to the metal wire switching network and the (i-1) th group of frame data processing units, wherein when i is 1, the second selection array is respectively connected to the metal wire switching network and a frame data input terminal;
the second selection array is configured to receive pre-transformation frame data transmitted by the i-1 th group of frame data processing units or frame data input terminals and transformed frame data transmitted by the metal wire switching network, and select the pre-transformation frame data as target data from the pre-transformation frame data, so as to transmit the pre-transformation frame data to the second cache array;
the second buffer array is used for outputting the frame data before transformation to an (i +1) th group of frame data processing units.
7. The frame format conversion circuit of claim 6, wherein the second selection array comprises a plurality of second selectors, the second buffer array comprises a plurality of second registers, the number of second selectors and second registers is the same, and an output of each of the second selectors is connected to one of the second registers, wherein,
a first input end of the second selector is connected with the metal wire switching network, a second input end of the second selector is connected with the i-1 th group of frame data processing units or frame data input ends, and each second selector is used for selecting frame data before transformation as target data and transmitting the frame data before transformation to a corresponding second register for storage;
each second register is used for outputting the frame data before transformation to an (i +1) th group of frame data processing units.
8. The frame format conversion circuit according to claim 7, wherein the plurality of second selectors are each connected to a control line;
each second selector is used for receiving a second control signal through the control line, so that each second selector takes the received data of the second input end as target data according to the second control signal, and transmits the target data to the corresponding second register for storage.
9. The frame format conversion circuit according to claim 1, wherein each of the groups of the frame data processing units is connected to a clock generator; wherein the content of the first and second substances,
the ith group of frame data processing units are used for transmitting the frame data before conversion to the (i +1) th group of frame data processing units in the next clock period after the frame data before conversion is received in the current clock period;
and the Nth group of frame data processing units are used for outputting the converted frame data in the next clock cycle after receiving the converted frame data in the current clock cycle.
10. A frame format conversion method is characterized in that the method is applied to a frame format conversion circuit, the frame format conversion circuit comprises a metal wire switching network and N groups of frame data processing units, each group of frame data processing units is connected with the metal wire switching network, and the N groups of frame data processing units are sequentially cascaded; the method comprises the following steps:
the metal wire switching network acquires frame data before transformation of all the ith group of frame data processing units, wherein the ith group of frame data processing units are any one of the N group of frame data processing units except the Nth group of frame data processing units, N is more than i, and N is an integer more than 1;
the metal wire switching network maps the frame data before conversion according to a target format and then transmits the frame data to the Nth group of frame data processing unit;
and the Nth group of frame data processing unit outputs the transformed frame data.
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