CN111048591B - TFET device with parallel operation function - Google Patents

TFET device with parallel operation function Download PDF

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CN111048591B
CN111048591B CN201911130562.7A CN201911130562A CN111048591B CN 111048591 B CN111048591 B CN 111048591B CN 201911130562 A CN201911130562 A CN 201911130562A CN 111048591 B CN111048591 B CN 111048591B
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face
cuboid block
oxide layer
gate oxide
same plane
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CN111048591A (en
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叶浩
胡建平
张子豪
高晗晔
戴凯
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Ningbo University
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Ningbo University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Abstract

The invention discloses a TFET device with a parallel operation function, which comprises a first metal gate, a second metal gate, a third metal gate, a silicon-based channel, a first high-K dielectric gate oxide layer, a second high-K dielectric gate oxide layer, a third high-K dielectric gate oxide layer, a source region, a drain region, a first barrier layer and a second barrier layer, wherein the silicon-based channel is realized by adopting an inverted L-shaped structure, and the first metal gate, the second metal gate and the third metal gate are positioned on the outer side of the silicon-based channel and are used as three independently input grid electrodes; the advantages are compact structure, through three independent grid control, the current carrier can pass through the upper channel, the lower channel or the whole channel of the inverted L-shaped silicon-based channel, so that the conduction currents in the three states are equivalent, and the function of parallel operation is achieved, thus greatly reducing the use number of transistors in VLSI circuit design, further simplifying the structure of the VLSI circuit, and greatly reducing the area and power consumption of the VLSI circuit.

Description

TFET device with parallel operation function
Technical Field
The invention relates to a TFET device, in particular to a TFET device with a parallel operation function.
Background
With the continuous development of semiconductor technology, the semiconductor industry has stepped into nanoscale process nodes, and the performance of semiconductors is limited by various physical limitations. In semiconductor device scaling, a series of problems arise due to short channel effects: such as the decay of the threshold voltage and the decay of the subthreshold slope, these problems directly lead to a significant increase in leakage current and ultimately to a catastrophic increase in the static power consumption of VLSI circuits. Recently, Intel corporation declared that their chip fabricated at the 10nm process node had a transistor density of 1.008 billion per square millimeter, which has a great demand for further improvement in low power consumption and performance of transistors. A Tunnel Field Effect Transistor (TFET) is a new transistor based on an inter-band tunneling transport mechanism, and its subthreshold swing can break through the physical limit of 60 mV/dec, which is one of the most promising candidates for next-generation low-power devices.
In the field of VLSI circuit (very large scale integrated circuit) design, it is necessary to avoid the series operation of transistors as much as possible in order to allow the VLSI circuit to operate at high speed, and thus the parallel operation of transistors is more used logically. The circuit unit with the parallel operation function has high use power in a VLSI circuit. The traditional TFET device is of a plane structure, a circuit unit with a parallel operation function is designed based on the traditional TFET device, and basic functions can be realized only by adopting three TFET devices, so that the quantity of the TFET devices in a VLSI circuit is large, the circuit structure is complex, and the circuit area and the power consumption are large. With further research on TFET devices, multi-gate TFET devices have been proposed. The multi-gate TFET device has a plurality of independent input ends, and the gate control capability is enhanced, so that higher on-current can be obtained. Multi-gate TFET devices have currently attracted considerable research interest, but all current research is limited to dual-gate TFET devices. Compared with the traditional TFET device, the circuit unit with the parallel operation function designed based on the double-gate TFET device has the advantages that although the number of devices is reduced (three devices are reduced to two devices), the number of TFET devices in a final VLSI circuit is still huge, the circuit structure is still complex, and the circuit area and the power consumption are still large.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a TFET device with a parallel operation function, which can compactly realize the parallel operation function, thereby greatly reducing the using number of transistors in VLSI circuit design, further simplifying the structure of the VLSI circuit, and greatly reducing the area and the power consumption of the VLSI circuit.
The technical scheme adopted by the invention for solving the technical problems is as follows: a TFET device with a parallel operation function comprises a first metal gate, a second metal gate, a third metal gate, a silicon-based channel, a first high-K dielectric gate oxide layer, a second high-K dielectric gate oxide layer, a third high-K dielectric gate oxide layer, a source region, a drain region, a first barrier layer and a second barrier layer, wherein the first metal gate, the second metal gate, the third metal gate, the source region, the drain region, the second high-K dielectric gate oxide layer, the third high-K dielectric gate oxide layer, the first barrier layer and the second barrier layer are all cuboid in shape; the source region, the silicon-based channel and the drain region are sequentially arranged and connected in a left-to-right sequence, the silicon-based channel comprises a first cuboid block and a second cuboid block, the first cuboid block is positioned above the second cuboid block, the front end face of the first cuboid and the front end face of the second cuboid block are positioned on the same plane, the lower end face of the first cuboid block is attached and connected with the upper end face of the second cuboid block, the left end face of the first cuboid block and the left end face of the second cuboid block are positioned on the same plane, the right end face of the first cuboid block and the right end face of the second cuboid block are positioned on the same plane, the length of the first cuboid block in the front-back direction is larger than that of the second cuboid block in the front-back direction, and the right end face of the source region is respectively connected with the left end face of the first cuboid and the left end face of the second cuboid block The left end face of the drain region is respectively in fit connection with the right end face of the first cuboid block and the right end face of the second cuboid block, the front end face of the source region, the front end face of the drain region and the front end face of the first cuboid block are located on the same plane, the rear end face of the source region, the rear end face of the drain region and the rear end face of the first cuboid block are located on the same plane, and the lower end face of the source region, the lower end face of the second cuboid block and the lower end face of the drain region are located on the same plane; the first barrier layer, the first high-K dielectric gate oxide layer and the second barrier layer are sequentially arranged and connected from left to right, the three layers are positioned in a space defined by the source region, the drain region and the silicon-based channel, the first high-K dielectric gate oxide layer comprises a third cuboid block and a fourth cuboid block, the third cuboid block is positioned above the fourth cuboid block, the front end face of the third cuboid and the front end face of the fourth cuboid block are positioned on the same plane, the lower end face of the third cuboid block is attached and connected with the upper end face of the fourth cuboid block, the left end face of the third cuboid block and the left end face of the fourth cuboid block are positioned on the same plane, the right end face of the third cuboid block and the right end face of the fourth cuboid block are positioned on the same plane, the length of the third cuboid block in the front-back direction is greater than that of the fourth cuboid block in the front-back direction, the left end face of the first barrier layer is attached and connected with the right end face of the source region, the upper end face of the first barrier layer is attached and fixedly connected with the lower end face of the first cuboid block, the front end face of the first barrier layer is attached and fixedly connected with the rear end face of the second cuboid block, the rear end face of the first barrier layer and the rear end face of the source region are positioned on the same plane, the right end face of the first barrier layer is respectively attached and connected with the left end face of the third cuboid block and the left end face of the fourth cuboid block, the upper end face of the third cuboid block is attached and fixedly connected with the lower end face of the first cuboid block, and the front end face of the third cuboid block and the front end face of the fourth cuboid block are respectively attached and fixedly connected with the rear end face of the second cuboid block The rear end face of the third cuboid block and the rear end face of the first barrier layer are positioned on the same plane, the right end face of the third cuboid block and the right end face of the fourth cuboid block are respectively attached and fixedly connected with the left end face of the second barrier layer, the upper end surface of the second barrier layer is fixedly connected with the lower end surface of the first cuboid block in a fitting manner, the right end face of the second barrier layer is fixedly connected with the left end face of the drain region in an attaching manner, the front end face of the second barrier layer is fixedly connected with the rear end face of the second cuboid block in an attaching manner, the rear end face of the second barrier layer and the rear end face of the drain region are positioned on the same plane, and the lower end face of the first barrier layer, the lower end face of the fourth cuboid block and the lower end face of the second barrier layer and the lower end face of the drain region are positioned on the same plane; the third metal grid is positioned below the third cuboid block, the left end face of the third metal grid is fixedly attached to the right end face of the first barrier layer, the front end face of the third metal grid is fixedly attached to the rear end face of the fourth cuboid block, the upper end face of the third metal grid is fixedly attached to the lower end face of the third cuboid block, the right end face of the third metal grid is fixedly attached to the left end face of the second barrier layer, the rear end face of the third metal grid and the rear end face of the drain region are positioned on the same plane, and the lower end face of the third metal grid and the lower end face of the first barrier layer are positioned on the same plane; the second high-K dielectric gate oxide layer is positioned above the first cuboid block, the lower end face of the second high-K dielectric gate oxide layer is fixedly attached to the upper end face of the first cuboid block, the left end face of the second high-K dielectric gate oxide layer and the left end face of the third metal gate are positioned on the same plane, the right end face of the second high-K dielectric gate oxide layer and the right end face of the first metal gate are positioned on the same plane, the front end face of the second high-K dielectric gate oxide layer and the front end face of the first cuboid block are positioned on the same plane, the rear end face of the second high-K dielectric gate oxide layer and the rear end face of the first cuboid block are positioned on the same plane, the first metal gate is positioned above the second high-K dielectric gate oxide layer, and the lower end face of the first metal gate is fixedly attached to the upper end face of the second high-K dielectric gate oxide layer, the left end face of the first metal gate and the left end face of the second high-K dielectric gate oxide layer are positioned on the same plane, the right end face of the first metal gate and the right end face of the second high-K dielectric gate oxide layer are positioned on the same plane, the front end face of the first metal gate and the front end face of the second high-K dielectric gate oxide layer are positioned on the same plane, and the rear end face of the first metal gate and the rear end face of the second high-K dielectric gate oxide layer are positioned on the same plane; the third high-K dielectric gate oxide layer is positioned on the front side of the second cuboid block, the rear end face of the third high-K dielectric gate oxide layer is fixedly attached to the front end face of the second cuboid block, the left end face of the third high-K dielectric gate oxide layer and the left end face of the third metal gate are positioned on the same plane, the right end face of the third high-K dielectric gate oxide layer and the right end face of the third metal gate are positioned on the same plane, the upper end face of the third high-K dielectric gate oxide layer and the upper end face of the first cuboid block are positioned on the same plane, the lower end face of the third high-K dielectric gate oxide layer and the lower end face of the second cuboid block are positioned on the same plane, the second metal gate is positioned on the front side of the third high-K dielectric gate oxide layer, and the rear end face of the second metal gate is fixedly attached to the front end face of the third high-K dielectric gate oxide layer, the left end face of the second metal grid and the left end face of the third metal grid are located on the same plane, the right end face of the second metal grid and the right end face of the third metal grid are located on the same plane, the upper end face of the second metal grid and the upper end face of the first cuboid block are located on the same plane, and the lower end face of the second metal grid and the lower end face of the third high-K dielectric grid oxygen layer are located on the same plane.
The first metal gate is made of TiN, the gate work function is 3.77eV, the second metal gate is made of TiN, the gate work function is 3.77eV, the third metal gate is made of TiN, the gate work function is 3.87eV, the first cuboid block is made of Si, the second cuboid block is made of Si, and the third cuboid block is made of HfO2The material of the fourth cuboid block is HfO2The second high-K dielectric gate oxide layer is made of HfO2The third high-K dielectric gate oxide layer is made of HfO2The source region is made of Si, the drain region is made of Si, the first barrier layer is made of silicon nitride, and the second barrier layer is made of silicon nitride.
The length of the first metal gate along the left-right direction is 30nm, the length of the first metal gate along the front-back direction is 20nm, and the thickness of the first metal gate is 2 nm; the length of the second metal gate along the left-right direction is 30nm, the length of the second metal gate along the front-back direction is 2nm, and the thickness of the second metal gate is 25 nm; the length of the third metal gate along the left-right direction is 30nm, the length along the front-back direction is 14nm, and the thickness is 19 nm; the length of the first cuboid block along the left-right direction is 30nm, the length along the front-back direction is 20nm, and the thickness is 5 nm; the length of the second cuboid block along the left-right direction is 30nm, the length of the second cuboid block along the front-back direction is 5nm, and the thickness of the second cuboid block is 20 nm; the length of the third cuboid block along the left-right direction is 30nm, the length along the front-back direction is 15nm, and the thickness is 1 nm; the length of the fourth cuboid block along the left-right direction is 30nm, the length along the front-back direction is 1nm, and the thickness is 19 nm; the length of the second high-K dielectric gate oxide layer along the left-right direction is 30nm, the length of the second high-K dielectric gate oxide layer along the front-back direction is 20nm, and the thickness of the second high-K dielectric gate oxide layer is 1 nm; the length of the third high-K dielectric gate oxide layer along the left-right direction is 30nm, the length of the third high-K dielectric gate oxide layer along the front-back direction is 1nm, and the thickness of the third high-K dielectric gate oxide layer is 25 nm; the length of the source region along the left-right direction is 30nm, the length along the front-back direction is 10nm, and the thickness is 25 nm; the length of the drain region along the left-right direction is 30nm, the length along the front-back direction is 10nm, and the thickness is 25 nm; the length of the first barrier layer along the left-right direction is 4nm, the length of the first barrier layer along the front-back direction is 20nm, and the thickness of the first barrier layer is 20 nm; (ii) a The length of the second barrier layer along the left-right direction is 4nm, the length along the front-back direction is 20nm, and the thickness is 20 nm. In the structure, three grid electrodes of a first metal grid, a second metal grid and a third metal grid are reasonably distributed on three sides of an inverted L-shaped silicon-based channel, the horizontal channel formed by a first cuboid block and a vertical channel formed by a second cuboid block are equal in size and shape, the first metal grid and the third metal grid jointly control the horizontal channel, the second metal grid and the third metal grid jointly control the vertical channel, and the grid work function of the third metal grid is slightly higher than the grid work functions of the other two metal grids (the first metal grid and the second metal grid), so that the contribution degrees of inputs of the three grid electrodes of the first metal grid, the second metal grid and the third metal grid to the conduction current of a device are similar, when the input numbers are the same as logic '1' and logic '0', the output currents similar to each other can be obtained, and the first high-K dielectric grid oxide layer, the second high-K dielectric grid oxide layer and the third high-K dielectric grid oxide layer with the same thickness are selected to enhance the first metal grid, And the control capability of the second metal gate and the third metal gate on the silicon-based channel. The first metal gate, the second metal gate and the third metal gate respectively adopt lower gate work functions to enable the threshold voltages of the first metal gate, the second metal gate and the third metal gate to be lower, the influence of input on the conduction current of the device is weakened, and the device has a NOR logic switching function, namely, when three metal gates input one logic '1', the device can obtain larger conduction current, and when two or more logic '1's are input, the increase amplitude of the conduction current of the device is not large.
Compared with the prior art, the invention has the advantages that: the silicon-based channel is realized by adopting an inverted L-shaped structure, the silicon-based channel is a thin body channel, the first metal gate, the second metal gate and the third metal gate are positioned at the outer side of the silicon-based channel and are used as three independently input gates, and the first high-K dielectric gate oxide layer, the second high-K dielectric gate oxide layer, the third high-K dielectric gate oxide layer, the source region, the drain region, the first barrier layer and the second barrier layer are arranged according to corresponding positions, so that the TFET device with the parallel operation function is realized by adopting a compact structure, in the TFET device, as the thin body channel is used, through three independent gate controls, current carriers can pass through an upper channel, a lower channel or the whole channel of the inverted L-shaped silicon-based channel, so that the conduction currents under the three states are equivalent, and the function of the parallel operation is achieved, therefore, the TFET device is taken as the parallel connection of three transistors in terms of logic function, compared with the traditional circuit with three transistors connected in parallel, the circuit reduces the number of the transistors in the large-scale integrated circuit design, can effectively improve the logic density of each area of the large-scale integrated circuit, and greatly reduces the chip area, and the switching current ratio of the TFET device reaches more than 10^6, the conduction current reaches a very high level in the TFET device and reaches 1.92 multiplied by 10^ -7A, the leakage current is very low, and the circuit has the characteristic of low power consumption.
Drawings
Fig. 1 is a first perspective view of a TFET device having a parallel operation function according to the present invention;
figure 2 is an exploded view of a TFET device of the present invention having parallel operation functionality;
figure 3 is a second perspective view of a TFET device of the present invention having a parallel operation function;
fig. 4 is a simulation curve of the transmission characteristics of the TFET device with parallel operation function according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 1 to 3, a TFET device with a parallel operation function includes a first metal gate 1, a second metal gate 2, a third metal gate 3, a silicon-based channel 4, a first high-K dielectric gate oxide layer 5, a second high-K dielectric gate oxide layer 6, a third high-K dielectric gate oxide layer 7, a source region 8, a drain region 9, a first barrier layer 10 and a second barrier layer 11, where the first metal gate 1, the second metal gate 2, the third metal gate 3, the source region 8, the drain region 9, the second high-K dielectric gate oxide layer 6, the third high-K dielectric gate oxide layer 7, the first barrier layer 10 and the second barrier layer 11 are all in a rectangular parallelepiped shape; the source region 8, the silicon-based channel 4 and the drain region 9 are sequentially arranged and connected in the order from left to right, the silicon-based channel 4 comprises a first rectangular parallelepiped block 41 and a second rectangular parallelepiped block 42, the first rectangular parallelepiped block 41 is located above the second rectangular parallelepiped block 42, the front end face of the first rectangular parallelepiped block is located on the same plane as the front end face of the second rectangular parallelepiped block 42, the lower end face of the first rectangular parallelepiped block 41 is attached and connected to the upper end face of the second rectangular parallelepiped block 42, the left end face of the first rectangular parallelepiped block 41 is located on the same plane as the left end face of the second rectangular parallelepiped block 42, the right end face of the first rectangular parallelepiped block 41 is located on the same plane as the right end face of the second rectangular parallelepiped block 42, the length of the first rectangular parallelepiped block 41 in the front-rear direction is greater than the length of the second rectangular parallelepiped block 42 in the front-rear direction, the right end face of the source region 8 is attached and connected to the left end face of the first rectangular parallelepiped block 41 and the left end face of the second rectangular parallelepiped block 42, the left end face of the drain region 9 is respectively attached and connected with the right end face of the first rectangular parallelepiped block 41 and the right end face of the second rectangular parallelepiped block 42, the front end face of the source region 8, the front end face of the drain region 9 and the front end face of the first rectangular parallelepiped block 41 are located on the same plane, the rear end face of the source region 8, the rear end face of the drain region 9 and the rear end face of the first rectangular parallelepiped block 41 are located on the same plane, and the lower end face of the source region 8, the lower end face of the second rectangular parallelepiped block 42 and the lower end face of the drain region 9 are located on the same plane; the first barrier layer 10, the first high-K dielectric gate oxide layer 5 and the second barrier layer 11 are sequentially arranged and connected from left to right, and the three layers are positioned in a space surrounded by the source region 8, the drain region 9 and the silicon-based channel 4, the first high-K dielectric gate oxide layer 5 comprises a third cuboid block 51 and a fourth cuboid block 52, the third cuboid block 51 is positioned above the fourth cuboid block 52, the front end face of the third cuboid block 51 and the front end face of the fourth cuboid block 52 are positioned on the same plane, the lower end face of the third cuboid block 51 is attached and connected with the upper end face of the fourth cuboid block 52, the left end face of the third cuboid block 51 and the left end face of the fourth cuboid block 52 are positioned on the same plane, the right end face of the third cuboid block 51 and the right end face of the fourth cuboid block 52 are positioned on the same plane, the length of the third cuboid block 51 in the front-back direction is greater than the length of the fourth cuboid block 52 in the front-back direction, the left end face of the first barrier layer 10 is bonded to the right end face of the source region 8, the upper end face of the first barrier layer 10 is bonded to and fixedly connected to the lower end face of the first rectangular parallelepiped block 41, the front end face of the first barrier layer 10 is bonded to and fixedly connected to the rear end face of the second rectangular parallelepiped block, the rear end face of the first barrier layer 10 and the rear end face of the source region 8 are located on the same plane, the right end face of the first barrier layer 10 is bonded to and fixedly connected to the left end face of the third rectangular parallelepiped block 51 and the left end face of the fourth rectangular parallelepiped block 52, the upper end face of the third rectangular parallelepiped block 51 and the lower end face of the first rectangular parallelepiped block 41 are bonded to and fixedly connected to the front end face of the third rectangular parallelepiped block 51 and the front end face of the fourth rectangular parallelepiped block 52, the rear end face of the third rectangular parallelepiped block 51 and the rear end face of the first barrier layer 10 are located on the same plane, the right end face of the third rectangular parallelepiped block 51 and the right end face of the fourth rectangular parallelepiped block 52 are bonded to and fixedly connected to the left end face of the second barrier layer 11, respectively The upper end face of the second barrier layer 11 is fixedly connected with the lower end face of the first cuboid block 41 in an attaching manner, the right end face of the second barrier layer 11 is fixedly connected with the left end face of the drain region 9 in an attaching manner, the front end face of the second barrier layer 11 is fixedly connected with the rear end face of the second cuboid block 42 in an attaching manner, the rear end face of the second barrier layer 11 and the rear end face of the drain region 9 are located on the same plane, and the lower end face of the first barrier layer 10, the lower end face of the fourth cuboid block 52 and the lower end face of the second barrier layer 11 and the lower end face of the drain region 9 are located on the same plane; the third metal gate 3 is positioned below the third cuboid block 51, the left end face of the third metal gate 3 is fixedly attached to the right end face of the first barrier layer 10, the front end face of the third metal gate 3 is fixedly attached to the rear end face of the fourth cuboid block 52, the upper end face of the third metal gate 3 is fixedly attached to the lower end face of the third cuboid block 51, the right end face of the third metal gate 3 is fixedly attached to the left end face of the second barrier layer 11, the rear end face of the third metal gate 3 and the rear end face of the drain region 9 are positioned on the same plane, and the lower end face of the third metal gate 3 and the lower end face of the first barrier layer 10 are positioned on the same plane; the second high-K dielectric gate oxide layer 6 is positioned above the first cuboid block 41, the lower end face of the second high-K dielectric gate oxide layer 6 is fixedly attached to the upper end face of the first cuboid block 41, the left end face of the second high-K dielectric gate oxide layer 6 and the left end face of the third metal gate 3 are positioned on the same plane, the right end face of the second high-K dielectric gate oxide layer 6 and the right end face of the first metal gate 1 are positioned on the same plane, the front end face of the second high-K dielectric gate oxide layer 6 and the front end face of the first cuboid block 41 are positioned on the same plane, the rear end face of the second high-K dielectric gate oxide layer 6 and the rear end face of the first cuboid block 41 are positioned on the same plane, the first metal gate 1 is positioned above the second high-K dielectric gate oxide layer 6, the lower end face of the first metal gate 1 and the upper end face of the second high-K dielectric gate oxide layer 6 are fixedly attached to each other, the left end face of the first metal gate 1 and the left end face of the second high-K dielectric gate oxide layer 6 are positioned on the same plane, the right end face of the first metal gate 1 and the right end face of the second high-K dielectric gate oxide layer 6 are located on the same plane, the front end face of the first metal gate 1 and the front end face of the second high-K dielectric gate oxide layer 6 are located on the same plane, and the rear end face of the first metal gate 1 and the rear end face of the second high-K dielectric gate oxide layer 6 are located on the same plane; the third high-K dielectric gate oxide layer 7 is positioned at the front side of the second cuboid block 42, the rear end face of the third high-K dielectric gate oxide layer 7 is jointed and fixedly connected with the front end face of the second cuboid block 42, the left end face of the third high-K dielectric gate oxide layer 7 and the left end face of the third metal gate 3 are positioned on the same plane, the right end face of the third high-K dielectric gate oxide layer 7 and the right end face of the third metal gate 3 are positioned on the same plane, the upper end face of the third high-K dielectric gate oxide layer 7 and the upper end face of the first cuboid block 41 are positioned on the same plane, the lower end face of the third high-K dielectric gate oxide layer 7 and the lower end face of the second cuboid block 42 are positioned on the same plane, the second metal gate 2 is positioned at the front side of the third high-K dielectric gate oxide layer 7, the rear end face of the second metal gate 2 is jointed and fixedly connected with the front end face of the third high-K dielectric gate oxide layer 7, the left end face of the second metal gate 2 and the left end face of the third metal gate 3 are positioned on the same plane, the right end face of the second metal gate 2 and the right end face of the third metal gate 3 are located on the same plane, the upper end face of the second metal gate 2 and the upper end face of the first cuboid block 41 are located on the same plane, and the lower end face of the second metal gate 2 and the lower end face of the third high-K dielectric gate oxide layer 7 are located on the same plane.
In this embodiment, the first metal gate 1 is made of TiN, the gate work function is 3.77eV, the second metal gate 2 is made of TiN, the gate work function is 3.77eV, the third metal gate 3 is made of TiN, the gate work function is 3.87eV, the first rectangular block 41 is made of Si, the second rectangular block 42 is made of Si, and the third rectangular block 51 is made of HfO2The fourth rectangular parallelepiped block 52 is made of HfO2The second high-K dielectric gate oxide layer 6 is made of HfO2The third high-K dielectric gate oxide layer 7 is made of HfO2The source region 8 is made of Si, the drain region 9 is made of Si, the first barrier layer 10 is made of silicon nitride, and the second barrier layer 11 is made of silicon nitride.
In this embodiment, the length of the first metal gate 1 along the left-right direction is 30nm, the length along the front-back direction is 20nm, and the thickness is 2 nm; the length of the second metal grid 2 along the left-right direction is 30nm, the length along the front-back direction is 2nm, and the thickness is 25 nm; the length of the third metal grid 3 along the left-right direction is 30nm, the length along the front-back direction is 14nm, and the thickness is 19 nm; the first rectangular parallelepiped block 41 had a length of 30nm in the left-right direction, a length of 20nm in the front-rear direction, and a thickness of 5 nm; the second rectangular parallelepiped block 42 had a length of 30nm in the left-right direction, a length of 5nm in the front-rear direction, and a thickness of 20 nm; the third rectangular parallelepiped block 51 had a length of 30nm in the left-right direction, a length of 15nm in the front-rear direction, and a thickness of 1 nm; the fourth rectangular parallelepiped block 52 had a length of 30nm in the left-right direction, a length of 1nm in the front-rear direction, and a thickness of 19 nm; the length of the second high-K dielectric gate oxide layer 6 along the left-right direction is 30nm, the length along the front-back direction is 20nm, and the thickness is 1 nm; the third high-K dielectric gate oxide layer 7 has a length of 30nm in the left-right direction, a length of 1nm in the front-back direction and a thickness of 25 nm; the length of the source region 8 along the left-right direction is 30nm, the length along the front-back direction is 10nm, and the thickness is 25 nm; the length of the drain region 9 in the left-right direction is 30nm, the length in the front-back direction is 10nm, and the thickness is 25 nm; the length of the first barrier layer 10 in the left-right direction is 4nm, the length in the front-back direction is 20nm, and the thickness is 20 nm; the second barrier layer 11 had a length of 4nm in the left-right direction, a length of 20nm in the front-rear direction, and a thickness of 20 nm.
The simulation curve of the transmission characteristic of the TFET device with the parallel operation function is shown in fig. 4. In fig. 4, a 0x0 curve is a simulation curve obtained by performing dc scanning on the second metal gate 2 when the first metal gate 1 is fixed to logic 0, that is, the first metal gate 1 is grounded at 0V, and the third metal gate 3 is fixed to logic 0, that is, the third metal gate 3 is grounded at 0V, and the scanning range is 0V-1V; the 1x1 curve is a simulation curve obtained by fixing the first metal gate 1 as logic 1, namely, the first metal gate 1 is switched in a high level of 1V, and the third metal gate 3 is fixed as logic 1, namely, when the first metal gate 1 is switched in a high level of 1V, performing direct current scanning on the second metal gate 2, wherein the scanning range is 0V-1V; the 1x0 curve is a simulation curve obtained by fixing the first metal gate 1 as logic 1, that is, the first metal gate 1 is connected to a high level of 1V, and the third metal gate 3 is fixed as logic 0, that is, when the third metal gate 3 is grounded at 0V, performing dc scanning on the second metal gate 2, wherein the scanning range is 0V-1V; the 0x1 curve is a simulation curve obtained by fixing the first metal gate 1 to logic 0, i.e., grounding the first metal gate 1 at 0V, and fixing the third metal gate 3 to logic 1, i.e., performing dc scanning on the second metal gate 2 when the third metal gate 3 is at a high level connected to 1V, with a scanning range of 0V to 1V. Analysis of FIG. 4 reveals that: when only one metal is biased to be high, the conduction current of the TFET device reaches 1.92 multiplied by 10^ -7A, when two metal gates are biased to be high, the conduction current of the TFET device reaches 2.23 multiplied by 10^ -7A, when the three metal gates are all biased to be high, the conduction current of the TFET device reaches 8.83 multiplied by 10^ -7A, and when the three metal gates of the TFET device are all accessed to be 0V, the TFET device is not conducted, and the leakage current is 1.13 multiplied by 10^ -13A.

Claims (3)

1. A TFET device with a parallel operation function is characterized by comprising a first metal gate, a second metal gate, a third metal gate, a silicon-based channel, a first high-K dielectric gate oxide layer, a second high-K dielectric gate oxide layer, a third high-K dielectric gate oxide layer, a source region, a drain region, a first barrier layer and a second barrier layer, wherein the first metal gate, the second metal gate, the third metal gate, the source region, the drain region, the second high-K dielectric gate oxide layer, the third high-K dielectric gate oxide layer, the first barrier layer and the second barrier layer are all in a cuboid shape;
the source region, the silicon-based channel and the drain region are sequentially arranged and connected in a left-to-right sequence, the silicon-based channel comprises a first cuboid block and a second cuboid block, the first cuboid block is positioned above the second cuboid block, the front end face of the first cuboid and the front end face of the second cuboid block are positioned on the same plane, the lower end face of the first cuboid block is attached and connected with the upper end face of the second cuboid block, the left end face of the first cuboid block and the left end face of the second cuboid block are positioned on the same plane, the right end face of the first cuboid block and the right end face of the second cuboid block are positioned on the same plane, the length of the first cuboid block in the front-back direction is larger than that of the second cuboid block in the front-back direction, and the right end face of the source region is respectively connected with the left end face of the first cuboid and the left end face of the second cuboid block The left end face of the drain region is respectively in fit connection with the right end face of the first cuboid block and the right end face of the second cuboid block, the front end face of the source region, the front end face of the drain region and the front end face of the first cuboid block are located on the same plane, the rear end face of the source region, the rear end face of the drain region and the rear end face of the first cuboid block are located on the same plane, and the lower end face of the source region, the lower end face of the second cuboid block and the lower end face of the drain region are located on the same plane;
the first barrier layer, the first high-K dielectric gate oxide layer and the second barrier layer are sequentially arranged and connected from left to right, the three layers are positioned in a space defined by the source region, the drain region and the silicon-based channel, the first high-K dielectric gate oxide layer comprises a third cuboid block and a fourth cuboid block, the third cuboid block is positioned above the fourth cuboid block, the front end face of the third cuboid and the front end face of the fourth cuboid block are positioned on the same plane, the lower end face of the third cuboid block is attached and connected with the upper end face of the fourth cuboid block, the left end face of the third cuboid block and the left end face of the fourth cuboid block are positioned on the same plane, the right end face of the third cuboid block and the right end face of the fourth cuboid block are positioned on the same plane, the length of the third cuboid block in the front-back direction is greater than that of the fourth cuboid block in the front-back direction, the left end face of the first barrier layer is attached and connected with the right end face of the source region, the upper end face of the first barrier layer is attached and fixedly connected with the lower end face of the first cuboid block, the front end face of the first barrier layer is attached and fixedly connected with the rear end face of the second cuboid block, the rear end face of the first barrier layer and the rear end face of the source region are positioned on the same plane, the right end face of the first barrier layer is respectively attached and connected with the left end face of the third cuboid block and the left end face of the fourth cuboid block, the upper end face of the third cuboid block is attached and fixedly connected with the lower end face of the first cuboid block, and the front end face of the third cuboid block and the front end face of the fourth cuboid block are respectively attached and fixedly connected with the rear end face of the second cuboid block The rear end face of the third cuboid block and the rear end face of the first barrier layer are positioned on the same plane, the right end face of the third cuboid block and the right end face of the fourth cuboid block are respectively attached and fixedly connected with the left end face of the second barrier layer, the upper end surface of the second barrier layer is fixedly connected with the lower end surface of the first cuboid block in a fitting manner, the right end face of the second barrier layer is fixedly connected with the left end face of the drain region in an attaching manner, the front end face of the second barrier layer is fixedly connected with the rear end face of the second cuboid block in an attaching manner, the rear end face of the second barrier layer and the rear end face of the drain region are positioned on the same plane, and the lower end face of the first barrier layer, the lower end face of the fourth cuboid block and the lower end face of the second barrier layer and the lower end face of the drain region are positioned on the same plane;
the third metal grid is positioned below the third cuboid block, the left end face of the third metal grid is fixedly connected with the right end face of the first barrier layer in an attaching manner, the front end face of the third metal grid is fixedly connected with the rear end face of the fourth cuboid block in an attaching manner, the upper end face of the third metal grid is fixedly connected with the lower end face of the third cuboid block in an attaching manner, the right end face of the third metal grid is fixedly connected with the left end face of the second barrier layer in an attaching manner, the rear end face of the third metal grid and the rear end face of the drain region are positioned on the same plane, and the lower end face of the third metal grid and the lower end face of the first barrier layer are positioned on the same plane;
the second high-K dielectric gate oxide layer is positioned above the first cuboid block, the lower end face of the second high-K dielectric gate oxide layer is fixedly connected with the upper end face of the first cuboid block in an attaching manner, the left end face of the second high-K dielectric gate oxide layer and the left end face of the third metal gate are positioned on the same plane, the right end face of the second high-K dielectric gate oxide layer and the right end face of the first metal gate are positioned on the same plane, the front end face of the second high-K dielectric gate oxide layer and the front end face of the first cuboid block are positioned on the same plane, the rear end face of the second high-K dielectric gate oxide layer and the rear end face of the first cuboid block are positioned on the same plane, the first metal gate is positioned above the second high-K dielectric gate oxide layer, and the lower end face of the first metal gate is fixedly connected with the upper end face of the second high-K dielectric gate oxide layer in an attaching manner, the left end surface of the first metal gate and the left end surface of the second high-K dielectric gate oxide layer are positioned on the same plane, the right end surface of the first metal gate and the right end surface of the second high-K dielectric gate oxide layer are positioned on the same plane, the front end surface of the first metal gate and the front end surface of the second high-K dielectric gate oxide layer are positioned on the same plane, and the rear end surface of the first metal gate and the rear end surface of the second high-K dielectric gate oxide layer are positioned on the same plane;
the third high-K dielectric gate oxide layer is positioned on the front side of the second cuboid block, the rear end face of the third high-K dielectric gate oxide layer is fixedly attached to the front end face of the second cuboid block, the left end face of the third high-K dielectric gate oxide layer and the left end face of the third metal gate are positioned on the same plane, the right end face of the third high-K dielectric gate oxide layer and the right end face of the third metal gate are positioned on the same plane, the upper end face of the third high-K dielectric gate oxide layer and the upper end face of the first cuboid block are positioned on the same plane, the lower end face of the third high-K dielectric gate oxide layer and the lower end face of the second cuboid block are positioned on the same plane, the second metal gate is positioned on the front side of the third high-K dielectric gate oxide layer, and the rear end face of the second metal gate is fixedly attached to the front end face of the third high-K dielectric gate oxide layer, the left end face of the second metal grid and the left end face of the third metal grid are located on the same plane, the right end face of the second metal grid and the right end face of the third metal grid are located on the same plane, the upper end face of the second metal grid and the upper end face of the first cuboid block are located on the same plane, and the lower end face of the second metal grid and the lower end face of the third high-K dielectric grid oxygen layer are located on the same plane.
2. The TFET device of claim 1, wherein the first metal gate is made of TiN with a gate work function of 3.77eV, the second metal gate is made of TiN with a gate work function of 3.77eV, the third metal gate is made of TiN with a gate work function of 3.87eV, the first cuboid block is made of Si, the second cuboid block is made of Si, and the third cuboid block is made of HfO2The material of the fourth cuboid block is HfO2The second high-K dielectric gate oxide layer is made of HfO2The third high-K dielectric gate oxide layer is made of HfO2The source region is made of Si, the drain region is made of Si, the first barrier layer is made of silicon nitride, and the second barrier layer is made of silicon nitride.
3. The TFET device of claim 1, wherein the first metal gate has a length of 30nm in a left-right direction, a length of 20nm in a front-back direction, and a thickness of 2 nm; the length of the second metal gate along the left-right direction is 30nm, the length of the second metal gate along the front-back direction is 2nm, and the thickness of the second metal gate is 25 nm; the length of the third metal gate along the left-right direction is 30nm, the length along the front-back direction is 14nm, and the thickness is 19 nm; the length of the first cuboid block along the left-right direction is 30nm, the length along the front-back direction is 20nm, and the thickness is 5 nm; the length of the second cuboid block along the left-right direction is 30nm, the length along the front-back direction is 5nm, and the thickness is 20 nm; the length of the third cuboid block along the left-right direction is 30nm, the length along the front-back direction is 15nm, and the thickness is 1 nm; the length of the fourth cuboid block along the left-right direction is 30nm, the length along the front-back direction is 1nm, and the thickness is 19 nm; the length of the second high-K dielectric gate oxide layer along the left-right direction is 30nm, the length of the second high-K dielectric gate oxide layer along the front-back direction is 20nm, and the thickness of the second high-K dielectric gate oxide layer is 1 nm; the length of the third high-K dielectric gate oxide layer along the left-right direction is 30nm, the length of the third high-K dielectric gate oxide layer along the front-back direction is 1nm, and the thickness of the third high-K dielectric gate oxide layer is 25 nm; the length of the source region along the left-right direction is 30nm, the length along the front-back direction is 10nm, and the thickness is 25 nm; the length of the drain region along the left-right direction is 30nm, the length along the front-back direction is 10nm, and the thickness is 25 nm; the length of the first barrier layer along the left-right direction is 4nm, the length of the first barrier layer along the front-back direction is 20nm, and the thickness of the first barrier layer is 20 nm; the length of the second barrier layer along the left-right direction is 4nm, the length along the front-back direction is 20nm, and the thickness is 20 nm.
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Publication number Priority date Publication date Assignee Title
JPS54158881A (en) * 1978-05-31 1979-12-15 Secr Defence Brit Field effect device and method of fabricating same
DE10320874A1 (en) * 2003-05-09 2004-12-09 Infineon Technologies Ag Integrated semiconductor memory has memory cell with inversion channel and small gate dielectric thickness permitting thermal majority carriers to tunnel to gate electrode
CN101740393A (en) * 2008-11-27 2010-06-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacture method thereof
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