CN111048529A - Circuit substrate, manufacturing method thereof and display substrate - Google Patents

Circuit substrate, manufacturing method thereof and display substrate Download PDF

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Publication number
CN111048529A
CN111048529A CN201911356040.9A CN201911356040A CN111048529A CN 111048529 A CN111048529 A CN 111048529A CN 201911356040 A CN201911356040 A CN 201911356040A CN 111048529 A CN111048529 A CN 111048529A
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substrate
cross
section
line segment
line
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CN111048529B (en
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解蒙蒙
夏兴达
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Shanghai Tianma Microelectronics Co Ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The invention discloses a circuit substrate, a manufacturing method thereof and a display substrate, and belongs to the technical field of display. The display substrate comprises the circuit substrate. The manufacturing method of the circuit substrate is used for manufacturing the circuit substrate. In the cutting direction, the first cross section of the first through hole is designed to be narrower than the second cross section of the first through hole in the first direction, and the first cross section of the second through hole is designed to be narrower than the first cross section of the second through hole in the second direction, namely the through holes in the cutting direction occupy smaller space, so that the distance between the side surface conductive connecting parts of the substrate substrates in each unit substrate can be reduced, and the manufacturing of a panel with higher PPI is facilitated.

Description

Circuit substrate, manufacturing method thereof and display substrate
Technical Field
The invention relates to the technical field of display, in particular to a circuit substrate, a manufacturing method of the circuit substrate and a display substrate.
Background
With the continuous development of display technologies, the application range of Micro-LED (Light-Emitting Diode, LED) and mini LED and other novel display technologies in the backlight field is more and more extensive. The Micro-LED is a display technology which is used for carrying out microminiaturization and matrixing on a traditional LED structure and manufacturing a driving circuit by adopting an integrated circuit process so as to realize addressing control and independent driving of each pixel point. Since various indexes such as brightness, life, contrast, reaction time, energy consumption, viewing angle, and resolution of the Micro-LED technology are better than those of LCD (liquid crystal display) and OLED (organic electroluminescent diode) technologies, and have advantages of self-luminescence, simple structure, small volume, and energy saving, the Micro-LED technology is considered as a next generation display technology, and various display technology leaders have started to be actively deployed.
At present, Micro LEDs and mini LEDs, whether used for backlight of a liquid crystal display device or for backlight of a large-sized TV, are integrated on a Printed Circuit Board (PCB), and emit light by adopting a passive driving manner, which can realize a normal backlight function, but have certain defects in aspects of dynamic local backlight brightness adjustment, reliability, power consumption, and the like. In order to solve the above problem, it is considered to use a glass substrate, i.e., to integrate both the Micro LED and the mini LED on the glass substrate. In the prior art, a reserved cutting line of a glass substrate integrated with Micro LEDs or mini LEDs is drilled by laser, a metal material is poured into a hole to connect upper and lower tracks of the substrate, and finally, the glass substrate is cut along the cutting line by a laser or a cutter wheel to form a plurality of independent substrates.
Therefore, how to solve the problems that the circuit substrate integrated with the Micro-LED or the mini LED in the prior art is not suitable for splicing the higher PPI panel, and the direct wiring process for manufacturing the side edge of the substrate in the tiled display is not mature, and is easy to wear and break, is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the invention provides a circuit substrate, a manufacturing method thereof and a display substrate, so as to solve the problems that the circuit substrate integrated with Micro-LEDs or mini-LEDs in the prior art is not suitable for splicing higher PPI panels, and the direct wiring process for manufacturing the side edge of the substrate in the splicing display is not mature, and is easy to wear and break.
The invention provides a circuit substrate which comprises a plurality of unit substrates arranged in an array, wherein a plurality of through holes are arranged between any adjacent unit substrates, the through holes comprise a plurality of first through holes arranged along a first direction and a plurality of second through holes arranged along a second direction, and the first direction is intersected with the second direction; the unit substrate comprises a substrate base plate and a driving circuit arranged on the substrate base plate, the via hole penetrates through the opposite top surface and the bottom surface of the substrate base plate, and the driving circuit comprises a first signal line positioned on the top surface of the substrate base plate and a second signal line positioned on the bottom surface of the substrate base plate; the circuit substrate also comprises a plurality of conductive connecting parts which are in one-to-one correspondence with the via holes, at least one part of each conductive connecting part is positioned in the corresponding via hole, one end of each conductive connecting part is electrically connected with the first signal wire, and the other end of each conductive connecting part is electrically connected with the second signal wire; the via includes a first cross section parallel to the bottom surface of the substrate base; on the plane of the first cross section, the first via hole comprises a first symmetrical shaft extending along the first direction and a second symmetrical shaft extending along the second direction; a connecting line of the intersection point of the first symmetry axis and the first via hole forms a first line segment, a connecting line of the intersection point of the second symmetry axis and the first via hole forms a second line segment, and the length of the second line segment is greater than that of the first line segment; on the plane where the first cross section is located, the second via hole comprises a third symmetry axis extending along the first direction and a fourth symmetry axis extending along the second direction; the connecting line of the intersection point of the third symmetry axis and the second through hole forms a third line segment, the connecting line of the intersection point of the fourth symmetry axis and the second through hole forms a fourth line segment, and the length of the third line segment is greater than that of the fourth line segment.
Based on the same inventive concept, the invention also provides a display substrate comprising the circuit substrate.
Based on the same inventive concept, the invention also provides a manufacturing method of the circuit substrate, which is used for manufacturing the circuit substrate and comprises the following steps: providing a substrate mother board; manufacturing a driving circuit on the substrate base plate mother board, wherein the driving circuit comprises a first signal line positioned on the top surface of the substrate base plate mother board and a second signal line lead positioned on the bottom surface of the substrate base plate mother board, and the top surface and the bottom surface are oppositely arranged; manufacturing a plurality of through holes penetrating through a mother board of a substrate, wherein the through holes comprise a plurality of first through holes distributed along a first direction and a plurality of second through holes distributed along a second direction; the via includes a first cross section parallel to a bottom surface of the substrate baseplate motherboard; on the plane of the first cross section, the first via hole comprises a first symmetrical shaft extending along the first direction and a second symmetrical shaft extending along the second direction; a connecting line of the intersection point of the first symmetry axis and the first via hole forms a first line segment, a connecting line of the intersection point of the second symmetry axis and the first via hole forms a second line segment, and the length of the second line segment is greater than that of the first line segment; on the plane where the first cross section is located, the second via hole comprises a third symmetry axis extending along the first direction and a fourth symmetry axis extending along the second direction; the connection line of the intersection point of the third symmetry axis and the second through hole forms a third line segment, the connection line of the intersection point of the fourth symmetry axis and the second through hole forms a fourth line segment, and the length of the third line segment is greater than that of the fourth line segment; each first via hole is distributed on a preset first cutting line and can be divided into two symmetrical first sub-holes by the first cutting line along the direction vertical to the substrate mother board; each second through hole is distributed on a preset second cutting line and can be divided into two symmetrical second sub-holes by the second cutting line along the direction vertical to the substrate mother board; the extending direction of the first cutting line is the same as the first direction, and the extending direction of the second cutting line is the same as the second direction; and manufacturing conductive connecting parts which correspond to the via holes one by one, wherein at least one part of each conductive connecting part is positioned in the corresponding via hole, and the conductive connecting parts are used for respectively connecting the corresponding first signal line and the second signal line.
Compared with the prior art, the circuit substrate, the manufacturing method thereof and the display substrate provided by the invention at least realize the following beneficial effects:
the circuit substrate comprises a plurality of unit substrates arranged in an array, a plurality of through holes are formed between any adjacent unit substrates, and when the unit substrates are used for manufacturing a backlight substrate or a display substrate of a Micro LED or a mini LED, cutting lines need to be reserved at the through hole positions of the circuit substrate and cut along the cutting lines to form a plurality of independent unit substrates. In the cutting direction, the first cross section of the first through hole, which is parallel to the bottom surface of the substrate base plate, is designed to be narrower than the second cross section in the first direction, and the first cross section of the second through hole, which is parallel to the bottom surface of the substrate base plate, is designed to be narrower than the first cross section in the second direction, namely, the occupied space of the through hole in the cutting direction is smaller, so that the distance between the side surface conductive connecting parts of the substrate base plate in each unit base plate can be reduced, the whole base plate space occupied by the through hole is reduced, and the manufacturing of a panel with higher PPI is facilitated.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic plan view of a circuit substrate according to an embodiment of the present invention;
FIG. 2 is a schematic sectional view taken along line A-A' of FIG. 1;
FIG. 3 is a schematic plan view of the circuit substrate of FIG. 1 after being cut;
FIG. 4 is a schematic diagram of a first cross section of the first via of FIG. 1;
FIG. 5 is a schematic diagram of a first cross section of the second via of FIG. 1;
FIG. 6 is a schematic plan view of another circuit substrate according to an embodiment of the present invention;
FIG. 7 is a schematic plan view of the circuit substrate of FIG. 6 after being cut;
FIG. 8 is a schematic diagram of a first cross section of the first via in FIG. 6;
FIG. 9 is a schematic diagram of a first cross section of the second via of FIG. 6;
FIG. 10 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;
FIG. 11 is a schematic illustration of a process prior to forming the structure of FIG. 10;
FIG. 12 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;
FIG. 13 is a schematic top view of the through hole of FIG. 12;
FIG. 14 is a schematic view of another cross-sectional configuration taken along line A-A' of FIG. 1;
FIG. 15 is a schematic top view of the through hole of FIG. 14;
FIG. 16 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;
FIG. 17 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;
fig. 18 is a schematic plan view illustrating a display substrate according to an embodiment of the invention;
fig. 19 is a flow chart of a method for manufacturing a circuit substrate according to an embodiment of the invention;
FIG. 20 is a schematic cross-sectional view of a substrate mother substrate provided;
FIG. 21 is a cross-sectional view of the substrate mother board after the driver circuits are formed thereon;
FIG. 22 is a schematic cross-sectional view of a substrate after a plurality of vias have been formed through a motherboard of the substrate;
FIG. 23 is a schematic plan view of the substrate after multiple vias have been formed through the motherboard;
fig. 24 is a schematic cross-sectional view of the conductive connection portion corresponding to the via hole.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1 to 5, fig. 1 is a schematic plan structure of a circuit substrate according to an embodiment of the present invention, fig. 2 is a schematic sectional structure along a direction a-a' in fig. 1, fig. 3 is a schematic plan structure of the circuit substrate in fig. 1 after being cut, fig. 4 is a schematic structural diagram of a first cross section of a first via in fig. 1, fig. 5 is a schematic structural diagram of a first cross section of a second via in fig. 1, and a circuit substrate 000 according to an embodiment of the present invention includes:
the unit substrates 10 are arranged in an array, a plurality of via holes 20 are arranged between any adjacent unit substrates 10, each via hole 20 comprises a plurality of first via holes 201 arranged along a first direction X and a plurality of second via holes 202 arranged along a second direction Y, and the plurality of first via holes 201 and the plurality of second via holes 202 intersect to define the range of the unit substrates 10; the first direction X and the second direction Y are both parallel to the plane of the circuit substrate 000, and the first direction X intersects with the second direction Y;
each unit substrate 10 includes a substrate 101 and a driving circuit 102 disposed on the substrate 101, the via 20 penetrates through a top surface 101A and a bottom surface 101B of the substrate 101 opposite to each other, and the driving circuit 102 includes a first signal line 1021 at the top surface 101A of the substrate 101 and a second signal line 1022 at the bottom surface 101B of the substrate 101;
the circuit substrate 000 further includes a plurality of conductive connection portions 30 corresponding to the vias 20 one to one, at least a portion of each conductive connection portion 30 is located in the corresponding via 20, and one end of each conductive connection portion 30 is electrically connected to the first signal line 1021, and the other end of each conductive connection portion 30 is electrically connected to the second signal line 1022;
it can be understood that, when the circuit substrate 000 of the present embodiment is used as a display substrate, optionally, each unit substrate 10 of the display substrate may further include a Micro-LED or a mini LED on the substrate 101, and the first signal line 1021 and the second signal line 1022 are electrically connected to the Micro-LED or the mini LED for providing a driving signal to the Micro-LED or the mini LED, so as to drive the Micro-LED or the mini LED to emit light. The circuit board 000 may be used for Micro-LED or mini LED lighting, and may also be used in liquid crystal display or organic light emitting diode display.
The via 20 includes a first cross-section M1 (it is understood that the first cross-section M1 is represented by a straight line in fig. 2, and is actually a surface) parallel to the substrate base surface 101B.
As shown in fig. 4, on the plane where the first cross section M1 is located, the first via 201 includes a first symmetry axis L1 extending along the first direction X and a second symmetry axis L2 extending along the second direction Y; a connecting line of the intersection point of the first symmetry axis L1 and the first via hole 201 forms a first line segment L11, a connecting line of the intersection point of the second symmetry axis L2 and the first via hole 201 forms a second line segment L21, and the length of the second line segment L21 is greater than that of the first line segment L11;
as shown in fig. 5, on the plane where the first cross section M1 is located, the second via 202 includes a third symmetry axis L3 extending along the first direction X and a fourth symmetry axis L4 extending along the second direction Y; a connecting line of the intersection point of the third symmetry axis L3 and the second via hole 202 forms a third line segment L31, a connecting line of the intersection point of the fourth symmetry axis L4 and the second via hole 202 forms a fourth line segment L41, and the length of the third line segment L31 is greater than that of the fourth line segment L41.
Specifically, the circuit substrate 000 of the embodiment includes a plurality of unit substrates 10 arranged in an array, a plurality of via holes 20 are disposed between any adjacent unit substrates 10, and when the unit substrates 10 are used for manufacturing a backlight substrate or a display substrate of a Micro LED or a mini LED, cutting lines need to be reserved at the via holes 20 of the circuit substrate 000 and cut along the cutting lines to form a plurality of independent unit substrates 10 (as shown in fig. 3); each unit substrate 10 includes a substrate 101 and a driving circuit 102 disposed on the substrate 101, the via 20 penetrates through a top surface 101A and a bottom surface 101B of the substrate 101 opposite to each other, and the driving circuit 102 includes a first signal line 1021 at the top surface 101A of the substrate 101 and a second signal line 1022 at the bottom surface 101B of the substrate 101; the circuit substrate 000 further includes a plurality of conductive connection portions 30 corresponding to the vias 20 one to one, at least a portion of each conductive connection portion 30 is located in the corresponding via 20, and one end of each conductive connection portion 30 is electrically connected to the first signal line 1021, and the other end of each conductive connection portion 30 is electrically connected to the second signal line 1022; the first signal line 1021 and the second signal line 1022 are electrically connected with the Micro-LED or the mini LED and are used for providing driving signals for the Micro-LED or the mini LED, so that the Micro-LED or the mini LED is driven to emit light. In the related art, when the unit substrate 10 of the embodiment is used to manufacture a backlight substrate or a display substrate of a Micro LED or a mini LED, the most of the unit substrates 10 are the via holes 20, and therefore, the space occupied by the via holes is directly related to the displayed PPI. In order to solve this problem, in the present embodiment, in the cutting direction (the cutting direction is the same as the first direction X or the second direction Y), the first cross section M1 of the first via 201 parallel to the bottom surface of the substrate base plate is designed to be narrower than the second direction Y in the first direction X, and the first cross section M1 of the second via 202 parallel to the bottom surface of the substrate base plate is designed to be narrower than the first direction Y in the second direction Y, that is, the occupied space of the via 20 in the cutting direction is small, so that the distance D between the side conductive connection portions 30 of the substrate base plate 101 in each unit base plate 10 can be reduced, the whole base plate space occupied by the via 20 is reduced, and the panel with higher PPI can be manufactured.
It should be noted that, in the present embodiment, the shape of the first cross section M1 of the first via 201 and the second via 202 in fig. 1, 4 and 5 is only an example, and in a specific implementation, the first cross section M1 is not limited to the shape illustrated in the drawings, but may also be other shapes, and it is only necessary to satisfy that, in the cutting direction, the first cross section M1 of the first via 201 parallel to the bottom surface of the substrate base is designed to be narrower in the first direction X than in the second direction Y, and the first cross section M1 of the second via 202 parallel to the bottom surface of the substrate base is designed to be narrower in the second direction Y than in the first direction X, which is beneficial to reduce an occupied space of the via 20 in the cutting direction, and the present embodiment is not limited.
In some alternative embodiments, please continue to refer to fig. 1-5, in the present embodiment, the first cross section M1 of the via 20 is elliptical. Optionally, the length of the second line segment L21 is twice the length of the first line segment L11, and the length of the third line segment L31 is twice the length of the fourth line segment L41.
The present embodiment further explains that in order to make the first cross section M1 of the first via 201 parallel to the bottom surface of the substrate board narrower than the second direction Y in the cutting direction, and the first cross section M1 of the second via 202 parallel to the bottom surface of the substrate board narrower than the first direction Y in the second direction Y, the first cross section M1 of the via 20 may be in an elliptical shape (as shown in fig. 4 and 5), and since the first cross section M1 of the via 20 is in an elliptical regular pattern, the process difficulty may be reduced, and the space occupied by the via 20 in the cutting direction may be reduced, so that the distance D between the side conductive connections 30 of the substrate board 101 in each unit board 10 may be reduced, and a panel with higher PPI may be manufactured. Optionally, in this embodiment, the length of the second line segment L21 of the first via 201 is twice as long as the length of the first line segment L11, and the length of the third line segment L31 of the second via 202 is twice as long as the length of the fourth line segment L41, so that when the conductive connection portion 30 is formed by injecting a conductive material into the via 20, each individual unit substrate 10 of the conductive connection portion 30 after being cut can have enough volume to achieve better conductive performance, thereby achieving electrical connection between the first signal line 1021 on the top surface 101A of the substrate 101 and the second signal line 1022 on the bottom surface 101B of the substrate 101, and ensuring that the via 20 occupies a small space in the cutting direction, so as to make a panel with higher PPI as much as possible.
In some alternative embodiments, please refer to fig. 6, 7, 8, and 9, in which fig. 6 is a schematic plan structure view of another circuit substrate provided in an embodiment of the present invention, fig. 7 is a schematic plan structure view of the circuit substrate in fig. 6 after being cut, fig. 8 is a schematic plan structure view of a first cross section of a first via in fig. 6, and fig. 9 is a schematic plan structure view of a first cross section of a second via in fig. 6, in this embodiment, a shape of a first cross section M1 of a via 20 is "8" shaped. Optionally, the length of the second line segment L21 is four times the length of the first line segment L11, and the length of the third line segment L31 is four times the length of the fourth line segment L41.
The present embodiment further explains that in order to design the first cross section M1 of the first via 201 parallel to the bottom surface of the substrate base plate to be narrower in the first direction X than the second direction Y, and the first cross section M1 of the second via 202 parallel to the bottom surface of the substrate base plate to be narrower in the second direction Y than the first direction X, the first cross section M1 of the via 20 may be shaped like an "8" (as shown in fig. 8 and 9), since the first cross section M1 of the via 20 is a regular pattern like an "8", the space occupied by the via 20 in the cutting direction may be further reduced while the difficulty of the manufacturing process is reduced, and thus the distance D between the side conductive connections 30 of the substrate base plate 101 in each unit base plate 10 may be further reduced, which is advantageous for manufacturing a panel with higher PPI. Optionally, in this embodiment, the length of the second line segment L21 of the first via 201 is designed to be four times the length of the first line segment L11, and the length of the third line segment L31 of the second via 202 is four times the length of the fourth line segment L41, so that when the conductive material is injected into the via 20 to form the conductive connection portion 30, it is ensured that each individual unit substrate 10 after being cut has enough volume to achieve better conductive performance, the first signal line 1021 on the top surface 101A of the substrate 101 and the second signal line 1022 on the bottom surface 101B of the substrate 101 are electrically connected, and the occupied space of the via 20 in the cutting direction is further made small enough, which is convenient for manufacturing a panel with higher PPI.
In some alternative embodiments, please continue to refer to fig. 1 to fig. 9, in the present embodiment, the length of the second line segment L21 and the length of the third line segment L31 are both greater than or equal to 50 μm.
In the circuit substrate 000 designed in this embodiment, when the circuit substrate 000 is cut into a plurality of independent unit substrates 10, a laser cutting technology is generally adopted, and in consideration of laser cutting accuracy, in this embodiment, it is required to make the length of the second line segment L21 of the first via 201 and the length of the third line segment L31 of the second via 202 both greater than or equal to the laser beam diameter, and the length of the optional second line segment L21 of the first via 201 and the length of the third line segment L31 of the second via 202 both greater than or equal to 50 μm, so that when laser cutting is performed, the conductive connection portions 30 located in the first via 201 and the second via 202 are not broken down by the laser beam, a situation that each independent unit substrate 10 after being cut has no conductive connection portion 30 with enough volume to realize conductive performance can be avoided, and a situation that no conductive connection portion 30 exists on the side of the unit substrate 10 after cutting is prevented, thereby, the first signal line 1021 on the top surface 101A of the substrate base plate 101 and the second signal line 1022 on the bottom surface 101B of the substrate base plate 101 can be electrically connected.
In some alternative embodiments, the vias 20 may be disposed in a rounded corner structure at the positions of the top surface 101A of the substrate base 101 and the bottom surface 101B of the substrate base 101, as shown in fig. 10, fig. 10 is another schematic cross-sectional structure along the direction a-a' in fig. 1, the vias 20 may be disposed in a rounded corner structure at the positions of the top surface 101A of the substrate base 101 and the bottom surface 101B of the substrate base 101 (the dashed area C in fig. 10), which may avoid the situation of the broken trace wear when the first signal line 1021 and the second signal line 1022 are connected to the conductive connection portion 30 in the vias 20 due to the right-angle structure, and is beneficial to enhancing the conductive performance of the circuit board 000.
It should be noted that the via hole 20 of the present embodiment may be formed by exposure etching or laser, and after the via hole 20 is formed, a metal material, such as copper, may be deposited in the via hole 20 by electroplating or sputtering, etc. to form the conductive connection portion 30. Before forming the conductive connection portion 30, firstly, a fillet structure of the dotted line region C in fig. 10 is manufactured, and since the right-angle structure cannot be directly ground, a laser-modified etching manner, that is, adjusting the position of a laser focus, may be adopted, a large number of laser focuses may form a laser-modified region represented by a black region in fig. 11 (fig. 11 is a schematic process diagram before forming the structure in fig. 10), and then the black region is etched away by a solution etching method, so that the fillet structure shown in fig. 10 may be obtained.
In some alternative embodiments, referring to fig. 1, 12-15 in combination, fig. 12 is another schematic cross-sectional view taken along a-a' direction in fig. 1, FIG. 13 is a schematic top view of the through hole of FIG. 12, FIG. 14 is a schematic cross-sectional view taken along the line A-A' of FIG. 1, fig. 15 is a schematic top view of the via of fig. 14 (for clarity, the shape of the via 20 is illustrated, and the conductive connection 30 is not illustrated in fig. 12-15), in this embodiment, the via 20 further includes a second cross section M2 (it is understood that the second cross section M2 is shown as a straight line in fig. 10, and is actually a surface) parallel to the bottom surface 101B of the substrate base 101, the second cross section M2 is located on the side of the first cross section M1 close to the bottom surface 101B of the substrate base 101 (as shown in fig. 12), alternatively, the second cross section M2 is located on the side of the first cross section M1 close to the top surface 101A of the substrate base plate 101 (as shown in fig. 14);
the orthographic projection of the second cross section M2 to the base substrate 101 is within the range of the orthographic projection of the first cross section to the base substrate (as shown in fig. 12 and 13, and fig. 14 and 15, the first cross section M1 in fig. 15 is represented by a dotted line to represent that it is not visible from an actual top view).
The present embodiment further explains that each via 20 further includes a second cross section M2 parallel to the bottom surface 101B of the substrate base 101, the second cross section M2 is located on the side of the first cross section M1 close to the bottom surface 101B of the substrate base 101 (as shown in fig. 12), or the second cross section M2 is located on the side of the first cross section M1 close to the top surface 101A of the substrate base 101 (as shown in fig. 14), optionally, the side of the substrate base 101 in the unit base 10 formed by the via 20 is an arc-shaped structure, when the second cross section M2 is located on the side of the first cross section M1 close to the bottom surface 101B of the substrate base 101, the risk of easily causing abrasion and breakage when the first signal line 1021 of the top surface 101A of the substrate base 101 is connected to the conductive connection 30 in the via 20 can be prevented, when the second cross section M2 is located on the side of the first cross section M1 close to the top surface 101A of, the risk that the second signal line 1022 on the bottom surface 101B of the substrate base plate 101 is easily worn and broken when connected to the conductive connection portion 30 in the via hole 20 can be prevented, and the structure of the via hole 20 can also prevent the sputtered metal material from causing uneven thickness on the side surface of the unit base plate 10 formed by the via hole 20 when the conductive connection portion 30 is manufactured, so that the slope-shaped via hole 20 shown in fig. 12 and 14 can be formed by combining laser modification and etching in the above embodiment, so that the thicknesses of the conductive connection portions 30 in the upper half portion and the lower half portion in the via hole 20 are as uniform as possible, and better conductive performance is realized.
In some alternative embodiments, please refer to fig. 1 and fig. 16 in combination, fig. 16 is another schematic sectional structure view along a-a' direction in fig. 1, in this embodiment, the via 20 further includes a third cross section M3 parallel to the bottom surface 101B of the substrate base 101, the third cross section M3 is located on a side of the first cross section M1 away from the second cross section M2, and a forward projection of the third cross section M3 to the substrate base 101 coincides with a forward projection of the second cross section M2 to the substrate base.
The present embodiment further explains that each via 20 further includes a second cross section M2 parallel to the bottom surface 101B of the substrate base plate 101, the second cross section M2 is located on the side of the first cross section M1 close to the top surface 101A of the substrate base plate 101, and further includes a third cross section M3 parallel to the bottom surface 101B of the substrate base plate 101, the third cross section M3 is located on the side of the first cross section M1 away from the second cross section M2, and the orthographic projection of the third cross section M3 to the substrate base plate 101 coincides with the orthographic projection of the second cross section M2 to the substrate base plate, so that the risk of abrasion breakage when the first signal line 1021 of the top surface 101A of the substrate base plate 101 is connected to the conductive connection 30 in the via 20 can be prevented, and the risk of abrasion breakage when the second signal line 1022 of the bottom surface 101B of the substrate base plate 101 is connected to the conductive connection 30 in the via 20 can be prevented, the connection performance of the driving circuit 102 and the conductive connection portion is made better. In addition, the structure of the via hole 20 can also prevent the uneven thickness of the sputtered metal material on the side surface of the unit substrate 10 formed by the via hole 20 when the conductive connection part 30 is manufactured, so that the present embodiment can form the via hole 20 shown in fig. 16 by combining laser modification and etching in the above embodiments, so that the thicknesses of the conductive connection parts 30 at the upper half part and the lower half part in the via hole 20 are as uniform as possible, and better conductivity is achieved.
Optionally, with continuing reference to fig. 12, 14 and 16, in the present embodiment, the via hole 20 includes a vertical cross section (not shown) perpendicular to the bottom surface 101B of the substrate base 101, and an intersecting line H formed by the vertical cross section and a side edge of the via hole 20 is an arc, so that a joint between a side surface of the substrate base 101 in the unit base 10 and the top surface 101A of the substrate base 101 and a joint between a side surface of the substrate base 101 in the unit base 10 and the bottom surface 101B of the substrate base 101 are smoother, which is more beneficial to the layout of signal lines and further reduces the risk of signal line abrasion and disconnection.
In some alternative embodiments, please refer to fig. 1 and 17 in combination, fig. 17 is a schematic cross-sectional view taken along a-a' direction in fig. 1, in which the conductive connection portion 30 includes: a first portion 301 located within the via 20; a second portion 302 connected to the first portion 301 and located on the top surface 101A of the substrate base plate 101; and a third portion 303 connected to the first portion 301 and located on the bottom surface 101B of the base substrate 101; the second portion 302 is connected to a first signal line 1021, and the third portion 303 is connected to a second signal line 1022. In fig. 17, in order to clearly illustrate the structure of the conductive connection portion 30 of the present embodiment, the first portion 301, the second portion 302, and the third portion 303 are illustrated with different filling patterns, and it is understood that the first portion 301, the second portion 302, and the third portion 303 are actually an integral structure although filling with different patterns is employed.
The present embodiment further explains that the conductive connection portion 30 includes a first portion 301, a second portion 302, and a third portion 303 that are integrally formed, where the first portion 301 is located in the via 20, the second portion 302 is located on the top surface 101A of the substrate 101 and connected to the first signal line 1021 of the driving circuit 102, and the third portion 303 is located on the bottom surface 101B of the substrate 101 and connected to the second signal line 1022 of the driving circuit 102, and the present embodiment designs that at least a part of the conductive connection portion 30 (the second portion 302 and the third portion 303) is beyond the via 20 and extends to the upper and lower surfaces of the substrate 101, so that the risk of fraying and breaking when the first signal line 1021 and the second signal line 1022 are routed to the boundary between the upper and lower surfaces of the substrate 101 and the side surface of the via 20 can be avoided, which is beneficial to enhance the conductive stability and reliability of the driving circuit 102.
It should be noted that, in this embodiment, the boundary between the upper and lower surfaces of the substrate base 101 and the side surface of the via hole 20 may be a rounded corner structure shown in fig. 10, a rounded structure shown in fig. 16, or a structure shown in fig. 17, which only needs to meet the requirement of further reducing the wear of the signal line at the position, and is beneficial to improving the yield of the circuit base 000.
In some alternative embodiments, please continue to refer to fig. 1 and 17, in this embodiment, the forward projection of the first portion 301 of the conductive connection portion 30 to the substrate 101 is located within the forward projection range of the second portion 302 to the substrate 101, and the forward projection of the first portion 301 to the substrate 101 is located within the forward projection range of the third portion 303 to the substrate 101.
The present embodiment further explains that the orthographic projection of the first portion 301 of the conductive connecting portion 30 onto the substrate base plate 101 is not only located in the orthographic projection range of the second portion 302 onto the substrate base plate 101, but also located in the orthographic projection range of the third portion 303 onto the substrate base plate 101, that is, on a plane parallel to the top surface 101A of the substrate base plate 101, the outer diameter R1 of the first portion 301 of the conductive connecting portion located inside the via hole 20 is smaller than not only the outer diameter R2 of the second portion 302 located outside the via hole 20 but also the outer diameter R3 of the third portion 303 located outside the via hole 20, and optionally, the outer diameter R2 of the second portion 302 may be equal to the outer diameter R3 of the third portion 303, so as to increase the conductive performance and robustness of the conductive connecting portion 30, avoid the signal line connected thereto from being worn and broken, and also improve the symmetry of the conductive connecting portion 30 in the direction perpendicular to the top surface 101A of the substrate base.
In some alternative embodiments, with continued reference to fig. 1 and 17, in the present embodiment, the thickness K1 of the conductive connection 30 is greater than the thickness K2 of the substrate base plate 101 in the direction perpendicular to the top surface 101A of the substrate base plate 101.
The present embodiment further explains that due to the design of the second portion 302 and the third portion 303 of the conductive connection portion 30, the thickness K1 of the conductive connection portion 30 is greater than the thickness K2 of the substrate base plate 101 in the direction perpendicular to the top surface 101A of the substrate base plate 101, so as to further increase the thickness of the conductive connection portion 30, avoid the risk of abrasion of the first signal line 1021 and the second signal line 1022 at the via 20, and facilitate the improvement of the conductive performance of the conductive connection portion 30.
In some alternative embodiments, referring to fig. 18, fig. 18 is a schematic plan view illustrating a display substrate according to an embodiment of the present invention, and the display substrate 111 provided in this embodiment includes the circuit substrate 000 provided in any one of the embodiments. Optionally, the display substrate 111 further includes a plurality of Micro light emitting diodes 40 (Micro-LEDs) disposed on the circuit substrate 000, the circuit substrate 000 is configured to drive the plurality of Micro light emitting diodes 40 to emit light, the Micro LEDs are LEDs with a grain size of about 1-10 microns, and the Micro LEDs have self-luminous display characteristics, and have advantages of being all solid, long in service life, high in brightness, low in power consumption, small in size, ultra-high in resolution, applicable to extreme environments such as high temperature or radiation, and capable of realizing a display screen with pixel particles of 0.05 mm or less. Alternatively, the display substrate 111 further comprises a plurality of mini LEDs disposed on the circuit substrate 000, which is also known as sub-millimeter light emitting diodes, meaning LEDs having a die size of between about 100 microns and 1000 microns; the first signal line 1021 and the second signal line 1022 are electrically connected with the Micro-LED or the mini LED40 and are used for providing a driving signal for the Micro-LED or the mini LED40, so that the Micro-LED or the mini LED40 is driven to emit light. The display substrate 111 may be used for Micro-LED or mini LED lighting, and may also be used for liquid crystal display or organic light emitting diode display. The display substrate 111 provided in the embodiment of the present invention has the beneficial effects of the circuit substrate 000 provided in the embodiment of the present invention, and specific descriptions of the circuit substrate 000 in the above embodiments may be specifically referred to, and this embodiment is not described herein again.
It should be noted that fig. 18 of the present embodiment only illustrates a schematic plan structure view of the display substrate 111 with one via 20 structure, and it is understood that the structure of the display substrate 111 can also be understood with reference to the structure of the circuit substrate 000 illustrated in any one of fig. 1 to 17, which is not repeated herein.
In some optional embodiments, please refer to fig. 1 to 17 and fig. 19 in combination, where fig. 19 is a flow chart of a method for manufacturing a circuit substrate according to an embodiment of the present invention, the method for manufacturing a circuit substrate according to the embodiment is used to manufacture the circuit substrate 000 according to any of the above embodiments, and the method includes:
step 001: providing a substrate base plate 101 motherboard (i.e. the substrate base plate in the above embodiment), as shown in fig. 20, fig. 20 is a schematic cross-sectional structure diagram of the provided substrate base plate 101 motherboard;
step 002: manufacturing a driving circuit 102 on the substrate base board 101 motherboard, wherein the driving circuit 102 comprises a first signal line 1021 positioned on a top surface 101A of the substrate base board 101 motherboard and a second signal line 1022 lead positioned on a bottom surface 101B of the substrate base board 101 motherboard, and the top surface 101A is arranged opposite to the bottom surface 101B, as shown in fig. 21, fig. 21 is a schematic cross-sectional structure after the driving circuit 102 is manufactured on the substrate base board 101 motherboard;
step 003: a plurality of through holes 20 penetrating through the mother board of the substrate base plate 101 are manufactured, the through holes 20 include a plurality of first through holes 201 arranged along a first direction X and a plurality of second through holes 202 arranged along a second direction Y, as shown in fig. 22 and 23, fig. 22 is a schematic cross-sectional structure diagram after the plurality of through holes 20 penetrating through the mother board of the substrate base plate 101 are manufactured (the cross section of fig. 22 is schematically illustrated by taking only two first through holes 201 as an example), and fig. 23 is a schematic plan-view structure diagram after the plurality of through holes 20 penetrating through the mother board of the substrate base plate 101 are manufactured;
wherein, as shown in fig. 2, 4, 5, the via 20 comprises a first cross section M1 parallel to the motherboard bottom surface 101B of the substrate base plate 101;
on the plane of the first cross section M1, the first via 201 includes a first symmetry axis L1 extending along the first direction X and a second symmetry axis L2 extending along the second direction Y; a connecting line of the intersection point of the first symmetry axis L1 and the first via hole 201 forms a first line segment L11, a connecting line of the intersection point of the second symmetry axis L2 and the first via hole 201 forms a second line segment L21, and the length of the second line segment L21 is greater than that of the first line segment L11;
on the plane of the first cross section M1, the second via 202 includes a third symmetry axis L3 extending along the first direction X and a fourth symmetry axis L4 extending along the second direction Y; a connecting line of the intersection point of the third symmetry axis L3 and the second via hole 202 forms a third line segment L31, a connecting line of the intersection point of the fourth symmetry axis L4 and the second via hole 202 forms a fourth line segment L41, and the length of the third line segment L31 is greater than that of the fourth line segment L41;
as shown in fig. 23, each of the first vias 201 is distributed on a preset first cut line Q1 and can be divided into two symmetrical first sub-holes 2010 by a first cut line Q1 in a direction perpendicular to the motherboard of the substrate base board 101; each second via 202 is distributed on a preset second cutting line Q2 and can be divided into two symmetrical second sub-holes 2020 along a direction perpendicular to the mother substrate of the substrate base plate 101 by the second cutting line Q2; wherein, the extending direction of the first cutting line Q1 is the same as the first direction X, and the extending direction of the second cutting line Q2 is the same as the second direction Y;
step 004: conductive connection portions 30 corresponding to the vias 20 one to one are manufactured, at least a portion of each conductive connection portion 30 is located in the corresponding via 20, the conductive connection portions 30 are used for respectively connecting the corresponding first signal line 1021 and the corresponding second signal line 1022, as shown in fig. 24, fig. 24 is a schematic cross-sectional structure diagram after the conductive connection portions corresponding to the vias one to one are manufactured, and a schematic plan structure diagram of the finally manufactured circuit substrate 000 is shown in fig. 1.
In this embodiment, the method for manufacturing the circuit board 000 is further explained, and optionally, the drilling manner for forming the plurality of vias 20 penetrating through the motherboard of the substrate board 101 in step 003 may be exposure etching or laser. The conductive connection portions 30 corresponding to the via holes 20 one to one are manufactured in step 004, and a metal material may be deposited in the via holes 20 by electroplating or sputtering, etc., to form the conductive connection portions 30. The circuit substrate 000 manufactured by the manufacturing method of this embodiment has the beneficial effects of the circuit substrate 000 provided by the above embodiments, and specific descriptions of the circuit substrate 000 in the above embodiments may be specifically referred to, and no further description is given in this embodiment.
Optionally, in some optional embodiments, after the circuit substrate 000 is manufactured, the circuit substrate 000 may be cut into a plurality of independent unit substrates 10 (as shown in fig. 3) along the first cutting line Q1 and the second cutting line Q2 by using a laser cutting process, where the unit substrates 10 manufactured in this embodiment have the beneficial effects of the circuit substrate 000 provided in the above embodiments, and specific descriptions of the circuit substrate 000 in the above embodiments may be specifically referred to, and are not repeated herein. .
As can be seen from the above embodiments, the circuit substrate, the manufacturing method thereof, and the display substrate provided by the present invention at least achieve the following advantages:
the circuit substrate comprises a plurality of unit substrates arranged in an array, a plurality of through holes are formed between any adjacent unit substrates, and when the unit substrates are used for manufacturing a backlight substrate or a display substrate of a Micro LED or a mini LED, cutting lines need to be reserved at the through hole positions of the circuit substrate and cut along the cutting lines to form a plurality of independent unit substrates. In the cutting direction, the first cross section of the first through hole, which is parallel to the bottom surface of the substrate base plate, is designed to be narrower than the second cross section in the first direction, and the first cross section of the second through hole, which is parallel to the bottom surface of the substrate base plate, is designed to be narrower than the first cross section in the second direction, namely, the occupied space of the through hole in the cutting direction is smaller, so that the distance between the side surface conductive connecting parts of the substrate base plate in each unit base plate can be reduced, the whole base plate space occupied by the through hole is reduced, and the manufacturing of a panel with higher PPI is facilitated.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (15)

1. A circuit substrate, comprising:
the unit substrates are arranged in an array, a plurality of through holes are arranged between any adjacent unit substrates, the through holes comprise a plurality of first through holes arranged along a first direction and a plurality of second through holes arranged along a second direction, and the first direction is intersected with the second direction;
the unit substrate comprises a substrate base plate and a driving circuit arranged on the substrate base plate, the via hole penetrates through the opposite top surface and the bottom surface of the substrate base plate, and the driving circuit comprises a first signal line positioned on the top surface of the substrate base plate and a second signal line positioned on the bottom surface of the substrate base plate;
the circuit substrate further comprises a plurality of conductive connecting parts which are in one-to-one correspondence with the via holes, at least one part of each conductive connecting part is positioned in the corresponding via hole, one end of each conductive connecting part is electrically connected with the first signal line, and the other end of each conductive connecting part is electrically connected with the second signal line;
the via includes a first cross section parallel to the substrate base surface;
on the plane of the first cross section, the first via hole comprises a first symmetry axis extending along the first direction and a second symmetry axis extending along the second direction; a connecting line of the intersection point of the first symmetry axis and the first via hole forms a first line segment, a connecting line of the intersection point of the second symmetry axis and the first via hole forms a second line segment, and the length of the second line segment is greater than that of the first line segment;
on the plane where the first cross section is located, the second via hole comprises a third symmetry axis extending along the first direction and a fourth symmetry axis extending along the second direction; and a line of the intersection point of the third symmetry axis and the second through hole forms a third line segment, a line of the intersection point of the fourth symmetry axis and the second through hole forms a fourth line segment, and the length of the third line segment is greater than that of the fourth line segment.
2. The circuit substrate of claim 1, wherein the first cross-section of the via is elliptical in shape.
3. The circuit substrate of claim 2, wherein the second line segment has twice the length of the first line segment, and the third line segment has twice the length of the fourth line segment.
4. The circuit substrate of claim 1, wherein the first cross-section of the via is "8" shaped.
5. The circuit substrate of claim 4, wherein the length of the second line segment is four times the length of the first line segment, and the length of the third line segment is four times the length of the fourth line segment.
6. The circuit substrate of claim 1, wherein the length of the second line segment and the length of the third line segment are both greater than or equal to 50 μ ι η.
7. The circuit substrate of claim 1, wherein the via further comprises a second cross section parallel to the bottom surface of the substrate base plate, the second cross section being located on a side of the first cross section adjacent to the bottom surface of the substrate base plate, or the second cross section being located on a side of the first cross section adjacent to the top surface of the substrate base plate;
the orthographic projection of the second cross section to the substrate base plate is located in the range of the orthographic projection of the first cross section to the substrate base plate.
8. The circuit substrate of claim 7, wherein the via further comprises a third cross section parallel to the bottom surface of the substrate base, the third cross section being on a side of the first cross section away from the second cross section, an orthographic projection of the third cross section toward the substrate base coinciding with an orthographic projection of the second cross section toward the substrate base.
9. The circuit substrate of claim 1, wherein the via comprises a vertical cross-section perpendicular to the bottom surface of the substrate base, wherein an intersection of the vertical cross-section with the side edge of the via is an arc.
10. The circuit substrate according to claim 1, wherein the conductive connection portion comprises:
a first portion located within the via;
a second portion connected to the first portion and located on a top surface of the substrate base plate;
and a third portion connected to the first portion and located at a bottom surface of the substrate base;
the second portion is connected to the first signal line, and the third portion is connected to the second signal line.
11. The circuit substrate according to claim 10, wherein the orthographic projection of the first portion onto the base substrate is within the orthographic projection range of the second portion onto the base substrate, and the orthographic projection of the first portion onto the base substrate is within the orthographic projection range of the third portion onto the base substrate.
12. The circuit substrate according to claim 1, wherein the thickness of the conductive connection portion is greater than the thickness of the substrate base in a direction perpendicular to the top surface of the substrate base.
13. A display substrate comprising the circuit substrate according to any one of claims 1 to 12.
14. The display substrate of claim 13, further comprising: the circuit board is used for driving the micro light-emitting diodes to emit light.
15. A method for manufacturing a circuit substrate, the method being used for manufacturing the circuit substrate according to any one of claims 1 to 12, the method comprising:
providing a substrate mother board;
manufacturing a driving circuit on the substrate base board mother board, wherein the driving circuit comprises a first signal line positioned on the top surface of the substrate base board mother board and a second signal line lead positioned on the bottom surface of the substrate base board mother board, and the top surface and the bottom surface are oppositely arranged;
manufacturing a plurality of via holes penetrating through the substrate base plate, wherein the via holes comprise a plurality of first via holes distributed along a first direction and a plurality of second via holes distributed along a second direction;
the via includes a first cross section parallel to a bottom surface of the substrate baseplate motherboard;
on the plane of the first cross section, the first via hole comprises a first symmetry axis extending along the first direction and a second symmetry axis extending along the second direction; a connecting line of the intersection point of the first symmetry axis and the first via hole forms a first line segment, a connecting line of the intersection point of the second symmetry axis and the first via hole forms a second line segment, and the length of the second line segment is greater than that of the first line segment;
on the plane where the first cross section is located, the second via hole comprises a third symmetry axis extending along the first direction and a fourth symmetry axis extending along the second direction; a line of the intersection point of the third symmetry axis and the second via hole forms a third line segment, a line of the intersection point of the fourth symmetry axis and the second via hole forms a fourth line segment, and the length of the third line segment is greater than that of the fourth line segment;
each first via hole is distributed on a preset first cutting line and can be divided into two symmetrical first sub-holes by the first cutting line along the direction vertical to the substrate mother board; each second through hole is distributed on a preset second cutting line and can be divided into two symmetrical second sub-holes by the second cutting line along the direction vertical to the substrate mother board; the extending direction of the first cutting line is the same as the first direction, and the extending direction of the second cutting line is the same as the second direction;
and manufacturing conductive connecting parts which are in one-to-one correspondence with the via holes, wherein at least one part of each conductive connecting part is positioned in the corresponding via hole, and the conductive connecting parts are used for respectively connecting the corresponding first signal line and the corresponding second signal line.
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