CN111048525A - Preparation method of array substrate and array substrate - Google Patents
Preparation method of array substrate and array substrate Download PDFInfo
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- CN111048525A CN111048525A CN201911178033.4A CN201911178033A CN111048525A CN 111048525 A CN111048525 A CN 111048525A CN 201911178033 A CN201911178033 A CN 201911178033A CN 111048525 A CN111048525 A CN 111048525A
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000002161 passivation Methods 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 36
- 238000000059 patterning Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 71
- 239000011521 glass Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000002834 transmittance Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000010409 thin film Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 10
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a preparation method of an array substrate and the array substrate.A first photomask process is adopted to carry out patterning treatment on a first metal layer to obtain a grid; patterning the second metal layer and the active layer by adopting a second photomask process to form a source drain metal layer, a channel and a semiconductor; and patterning the passivation layer by adopting a third photomask manufacturing process to form a contact hole and a transparent electrode pattern, and depositing a transparent electrode on the passivation layer according to the transparent electrode pattern. The array substrate of the thin film transistor is formed by three light covers, so that the number of the mask plates is reduced, and the process flow and the cost of the process are reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a preparation method of an array substrate and the array substrate.
Background
In the thin film transistor technology, an ordinary thin film transistor semiconductor, Indium Gallium Zinc Oxide (IGZO), has the characteristics of high electron mobility, small size of a thin film transistor, and the like, compared with amorphous silicon (a-si).
The common IGZO preparation process is divided into a Back Channel Etch (BCE)/Etch Stop Layer (ESL)/Coplanar (Coplanar) structure, and the corresponding exposure mask is 5 mask plates/6 mask plates/5 mask plates, respectively. In the preparation process, the production cost can be reduced by reducing the number of the mask plates.
Therefore, the array substrate provided by the invention can realize exposure preparation of the thin film transistor by using three mask plates, and further can reduce the production cost.
Disclosure of Invention
The invention aims to provide a preparation method of an array substrate and the array substrate.
In order to solve the above technical problems, the present invention provides a method for manufacturing an array substrate, including the steps of: providing a glass substrate; depositing a first metal layer on the glass substrate; patterning the first metal layer by adopting a first photomask process to obtain a grid; depositing an insulating layer on the grid and the glass substrate; depositing an active layer on one side of the insulating layer far away from the glass substrate; depositing a second metal layer on one side of the active layer far away from the insulating layer; patterning the second metal layer and the active layer by adopting a second photomask process to form a source drain metal layer, a channel and a semiconductor; depositing a passivation layer on the source drain metal layer and the insulating layer; and patterning the passivation layer by adopting a third photomask manufacturing process to form a contact hole and a transparent electrode pattern, and forming a transparent electrode on the passivation layer according to the transparent electrode pattern.
Further, the step of patterning the first metal layer by using the first photo-masking process specifically includes: coating a first photoresist on the first metal layer; providing a first mask plate above the first photoresist, and exposing and developing the first photoresist to form a first metal layer pattern; and removing the photoresist after etching the first metal layer corresponding to the first metal layer pattern to form the grid electrode.
Further, in the step of forming the source/drain metal layer, the channel, and the semiconductor by patterning the second metal layer and the active layer using a second photomask process, the method specifically includes: coating a second photoresist on the second metal layer; providing a second mask plate above the second light resistor, and exposing and developing the second light resistor to form a second metal layer pattern, wherein the second mask plate is a half-tone mask plate; and etching the second metal layer and the active layer corresponding to the second metal layer pattern, removing the photoresist to form the source and drain metal layer and the semiconductor, and forming the channel at the position of the source and drain metal layer corresponding to the grid.
Further, the step of patterning the passivation layer by using a third photo-masking process to form a contact hole and a transparent electrode pattern, and depositing a transparent electrode on the passivation layer according to the transparent electrode pattern specifically includes: coating a third light resistance on the passivation layer; providing a third mask over the third photoresist, the third mask comprising: a second full via and a second semi-permeable region; exposing and developing the third light resistance to form a passivation layer pattern, wherein the passivation layer pattern comprises a transparent electrode pattern corresponding to the second full-through hole contact hole pattern and the second semi-transparent area; etching the passivation layer corresponding to the passivation layer pattern, and forming the contact hole on the passivation layer; ashing the transparent electrode pattern by oxygen; depositing a transparent electrode on the passivation layer, the contact hole and the third photoresist which is not etched; and removing the transparent electrode corresponding to the third photoresist which is not etched away and the third photoresist which is not etched away.
Furthermore, the first mask plate is provided with a plurality of openings, and each opening corresponds to a gap between adjacent gates.
Further, the second mask includes: a first full via and a first semi-transparent region; the first half-penetration area corresponds to the channel, and the first full through hole corresponds to a gap of an adjacent grid electrode.
Further, the light transmittance of the first half-transmission area is 30% -50%; the light transmittance of the second semi-transparent area is 30% -50%.
Further, the first photoresist is a negative photoresist, and/or; the second photoresist is a negative photoresist, and/or the third photoresist is a negative photoresist.
Further, the material of the first metal layer comprises copper; and/or the material of the second metal layer comprises copper; and/or the material of the transparent electrode comprises indium tin oxide.
The invention also provides an array substrate prepared by the preparation method of the array substrate, which comprises the following steps: a glass substrate; the grid is arranged on the glass substrate; the insulating layer is arranged on the grid and the glass substrate; the semiconductor is arranged on one side, far away from the grid, of the insulating layer; the source-drain metal layer is arranged on one side of the semiconductor layer, which is far away from the insulating layer, is provided with a channel and corresponds to the grid; the passivation layer is arranged on the source drain metal layer, the channel and the insulation layer; and the transparent electrode is arranged on the passivation layer and is connected with the source drain electrode metal layer through a through hole.
The invention has the beneficial effects that: providing a preparation method of an array substrate and the array substrate, and patterning the first metal layer by adopting a first photomask process to obtain a grid electrode; patterning the second metal layer and the active layer by adopting a second photomask process to form a source drain metal layer, a channel and a semiconductor; and patterning the passivation layer by adopting a third photomask manufacturing process to form a contact hole and a transparent electrode pattern, and depositing a transparent electrode on the passivation layer according to the transparent electrode pattern. The array substrate of the thin film transistor is formed by three light covers, so that the number of the mask plates is reduced, and the process flow and the cost of the process are reduced.
Drawings
The invention is further described below with reference to the figures and examples.
Fig. 1 is a schematic structural view of the array substrate provided by the present invention exposed in a first photo-masking process.
Fig. 2 is a schematic structural diagram of the array substrate provided by the present invention developed in a first photo-masking process.
Fig. 3 is a schematic structural diagram of the array substrate provided by the present invention after etching in the first photo-masking process.
FIG. 4 is a schematic structural diagram of the array substrate provided by the present invention exposed in the second photo-masking process.
Fig. 5 is a schematic structural diagram of the array substrate provided by the invention developed in the second photo-masking process.
Fig. 6 is a schematic structural diagram of the array substrate provided by the invention after etching in the second photo-masking process.
Fig. 7 is a schematic structural diagram of the exposure of the array substrate provided by the invention in the third photo-masking process.
Fig. 8 is a schematic structural diagram of the array substrate provided by the invention developed in the third photo-masking process.
Fig. 9 is a schematic structural diagram of the array substrate provided by the invention after etching in the third photo-masking process.
Fig. 10 is a schematic structural diagram of the array substrate provided by the present invention in which transparent electrodes are deposited in a third photo-masking process.
Fig. 11 is a schematic structural diagram of the array substrate provided by the invention with a part of the transparent electrode removed in the third photo-masking process.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Directional phrases used herein, such as, for example, upper, lower, front, rear, left, right, inner, outer, lateral, etc., refer only to the orientation of the accompanying drawings. The names of the elements, such as the first, the second, etc., mentioned in the present invention are only used for distinguishing different elements and can be better expressed. In the drawings, elements having similar structures are denoted by the same reference numerals.
Embodiments of the present invention will be described in detail herein with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided to explain the practical application of the invention and to enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1 to 11, the present invention provides a method for manufacturing an array substrate, wherein in one embodiment, the method includes the following steps.
S1) is provided the glass substrate 101 as shown in fig. 1.
S2) depositing a first metal layer 102 on the glass substrate 101; the material of the first metal layer 102 includes copper.
S3) patterning the first metal layer 102 by a first photo-masking process to form a gate 102 a. Referring to fig. 1 to 3, the step S3) includes the following steps.
S31) coating a first photoresist 112 on the first metal layer 102; the first photoresist 112 is a negative photoresist. After the negative photoresist is irradiated by light, the negative photoresist is removed by a developing solution.
S32), a first mask 11 is provided over the first photoresist 112, and the first photoresist 112 is exposed and developed to form a first metal layer pattern 112a (see fig. 2). The first metal layer pattern 112a is a pattern structure formed by exposing the first photoresist and removing the first photoresist with a developing solution.
The first mask 11 has a plurality of openings 111 (see fig. 1), and a gap is formed between each of the openings 111 to form a gap between gates of the thin film transistors.
Specifically, when the first photoresist 112 on the glass substrate 101 is irradiated by light, the light 10 passes through the opening 111 to irradiate the first photoresist 112, and then the area of the first photoresist irradiated by the light 10 is removed by a developing solution to form a first metal layer pattern 112a (as shown in fig. 2).
S33) as shown in fig. 3, the photoresist is removed after etching the first metal layer corresponding to the first metal layer pattern 112a, thereby forming the gate electrode 102a, each opening corresponding to a gap between adjacent gate electrodes 102 a.
The gate electrode 102a mainly functions to control the electric field intensity at the cathode surface to change the emission of electrons from the cathode or to trap secondary emitted electrons.
S4) as shown in fig. 4, an insulating layer 103 is deposited on the gate electrode 102a and the glass substrate 101.
S5) depositing an active layer 104 on the side of the insulating layer 103 away from the glass substrate 101.
S6) depositing a second metal layer 105 on the side of the active layer 104 away from the insulating layer; the material of the second metal layer comprises copper.
S7) patterning the second metal layer 105 and the active layer 104 by using a second photo-masking process to form a source/drain metal layer 105a, a trench 1053a and a semiconductor 104 a; referring to fig. 4 to 6, the step S7) includes the following steps.
S71) coating a second photoresist 113 on the second metal layer 105; the second photoresist 113 is a negative photoresist, and the negative photoresist is removed by a developing solution after being irradiated by light.
S72), a second mask 12 is provided over the second photoresist 113, and the second photoresist 113 is exposed and developed to form a second metal layer pattern 113 a.
The second mask 12 is a halftone mask; the second mask includes: a first full via 121 and a first half-through region 122.
The first half-through region 122 corresponds to the channel 1053a, and the first full via 121 corresponds to a gap between adjacent gates 102 a. The light transmittance of the first half-transmission region 122 is 30% to 50%.
When the light 10 irradiates the second mask 12, the light 10 only passes through the first through hole 121 to irradiate the second photoresist 113, and a part of the light passes through the first semi-transparent region 122 to irradiate the corresponding second photoresist. Finally, the irradiated second photoresist region is removed by a developing solution, and a second metal layer pattern as shown in fig. 5 is formed. Since the first half-transmissive region 122 is not fully transmissive, the second photoresist corresponding to the first half-transmissive region 122 is not completely removed, but rather has a thinner photoresist, and then the thinner photoresist (i.e., the first half-transmissive region) is continuously ashed with oxygen to form the channel pattern.
S73) as shown in fig. 6, after the second metal layer 105 and the active layer 104 corresponding to the second metal layer pattern 113a are etched, the second photoresist that is not removed by the developing solution is removed, so as to form a source/drain metal layer 105a and a semiconductor 104a, and a trench 1053a is formed at the gate corresponding to the source/drain metal layer 105a by wet etching.
Source drain metal layer 105a forms source line 1051a and drain line 1052a due to channel 1053a, which is not shown in the right side of fig. 6.
S8) as shown in fig. 7, depositing a passivation layer 108 on the source/drain metal layer 105a and the insulating layer 103.
S9) patterning the passivation layer 108 by a third photo-masking process to form a contact hole 1081 and a transparent electrode pattern 1062a, and forming a transparent electrode 107 on the passivation layer 108 according to the transparent electrode pattern 1062 a. The step S9) specifically includes the following steps.
S91) with continued reference to fig. 7, a third photoresist 106 is applied over the passivation layer 108.
S92) providing a third mask 13 over the third photoresist 106, the second mask 13 comprising: a second full through hole 131 and a second semi-transparent region 132, wherein the light transmittance of the second semi-transparent region 132 is 30% -50%.
S93) exposing and developing the third photoresist 106 to form a passivation layer pattern 106a, as shown in fig. 8, wherein the passivation layer pattern 106a includes a transparent electrode pattern 1062a corresponding to the second full via contact hole pattern 1061a and corresponding to the second semi-transparent region.
The transparent electrode pattern 1062a is the third photoresist 106 corresponding to the second semi-transparent region 132, and since the second semi-transparent region 132 is not completely transparent, the third photoresist is not completely removed during development, and a thinner second photoresist is left in the photoresist region corresponding to the second semi-transparent region 132, which is to be distinguished from the second photoresist 1063a in the opaque region that is not removed by the developer.
S94) as shown in fig. 9, the passivation layer 108 corresponding to the passivation layer pattern 106a is etched, and a contact hole 1081 is formed on the passivation layer 108.
The second photoresist 1062a corresponding to the second semi-transparent area 132 and the second photoresist 1063a of the opaque area are used as an etching barrier layer of the etching contact hole 1081, and play roles of defining and protecting.
S95) ashing the transparent electrode pattern 1062a with oxygen, as shown in fig. 10.
S96) depositing a transparent electrode 1071 on the passivation layer 108, the contact hole 1081 and the third photoresist 1063a not etched away;
s97) as shown in fig. 11, the transparent electrode on the third photoresist 1063a that is not etched away and the third photoresist 1063 that is not etched away are removed.
With continued reference to fig. 11, in another embodiment, the present invention further provides an array substrate prepared by the method for preparing an array substrate, including: a glass substrate 101, a gate electrode 102a, an insulating layer 103, a semiconductor 104a, a source-drain metal layer 105a, a passivation layer 108, and a transparent electrode 107.
The gate electrode 102a is arranged on the glass substrate 101; the insulating layer 103 is disposed on the gate 102a and the glass substrate 101; the semiconductor 104a is arranged on one side of the insulating layer 103 far away from the glass substrate 101; the source-drain metal layer 105a is disposed on a side of the semiconductor layer 104a away from the insulating layer 103, and has a channel 1053a corresponding to the gate 102 a.
The passivation layer 108 is disposed on the source/drain metal layer 105a, the channel 1053a, and the insulating layer 103; the transparent electrode 107 is disposed on the passivation layer 108 and connected to the source/drain metal layer 105a through a contact hole 1081.
The invention provides a preparation method of an array substrate and the array substrate.A first photomask process is adopted to carry out patterning treatment on a first metal layer to obtain a grid; patterning the second metal layer and the active layer by adopting a second photomask process to form a source drain metal layer, a channel and a semiconductor; and patterning the passivation layer by adopting a third photomask manufacturing process to form a contact hole and a transparent electrode pattern, and depositing a transparent electrode on the passivation layer according to the transparent electrode pattern. The array substrate of the thin film transistor is formed by three light covers, so that the number of the mask plates is reduced, and the process flow and the cost of the process are reduced.
It should be noted that many variations and modifications of the embodiments of the present invention fully described are possible and are not to be considered as limited to the specific examples of the above embodiments. The above examples are intended to be illustrative of the invention and are not intended to be limiting. In conclusion, the scope of the present invention should include those changes or substitutions and modifications which are obvious to those of ordinary skill in the art.
Claims (10)
1. The preparation method of the array substrate is characterized by comprising the following steps:
providing a glass substrate;
depositing a first metal layer on the glass substrate;
patterning the first metal layer by adopting a first photomask process to obtain a grid;
depositing an insulating layer on the grid and the glass substrate;
depositing an active layer on one side of the insulating layer far away from the glass substrate;
depositing a second metal layer on one side of the active layer far away from the insulating layer;
patterning the second metal layer and the active layer by adopting a second photomask process to form a source drain metal layer, a channel and a semiconductor;
depositing a passivation layer on the source drain metal layer and the insulating layer;
and patterning the passivation layer by adopting a third photomask manufacturing process to form a contact hole and a transparent electrode pattern, and forming a transparent electrode on the passivation layer according to the transparent electrode pattern.
2. The method of manufacturing an array substrate according to claim 1,
in the step of patterning the first metal layer by using the first photomask process, the method specifically includes:
coating a first photoresist on the first metal layer;
providing a first mask plate above the first photoresist, and exposing and developing the first photoresist to form a first metal layer pattern;
and removing the photoresist after etching the first metal layer corresponding to the first metal layer pattern to form the grid electrode.
3. The method of manufacturing an array substrate according to claim 2,
in the step of forming the source/drain metal layer, the channel, and the semiconductor by patterning the second metal layer and the active layer using the second photomask process, the method specifically includes:
coating a second photoresist on the second metal layer;
providing a second mask plate above the second light resistor, and exposing and developing the second light resistor to form a second metal layer pattern, wherein the second mask plate is a half-tone mask plate;
and etching the second metal layer corresponding to the second metal layer pattern and the active layer, removing the second photoresist to form the source and drain metal layer and the semiconductor, and forming the channel at the position of the source and drain metal layer corresponding to the grid.
4. The method of claim 3, wherein the step of forming the array substrate comprises the steps of,
in the step of patterning the passivation layer by using the third photo-masking process to form the contact hole and the transparent electrode pattern, and depositing a transparent electrode on the passivation layer according to the transparent electrode pattern, the method specifically includes:
coating a third light resistance on the passivation layer;
providing a third mask over the third photoresist, the third mask comprising: a second full via and a second semi-permeable region;
exposing and developing the third light resistance to form a passivation layer pattern, wherein the passivation layer pattern comprises a transparent electrode pattern corresponding to the second full-through hole contact hole pattern and the second semi-transparent area;
etching the passivation layer corresponding to the passivation layer pattern, and forming the contact hole on the passivation layer;
ashing the transparent electrode pattern by oxygen;
depositing the transparent electrode on the passivation layer, in the contact hole and on the third photoresist which is not etched;
and removing the transparent electrode corresponding to the third photoresist which is not etched away and the third photoresist which is not etched away.
5. The method for manufacturing the array substrate according to claim 2, wherein the first mask has a plurality of openings, and each opening corresponds to a gap between adjacent gates.
6. The method for preparing the array substrate according to claim 4, wherein the second mask comprises: a first full via and a first semi-transparent region;
the first half-penetration area corresponds to the channel, and the first full through hole corresponds to a gap of an adjacent grid electrode.
7. The method for preparing the array substrate according to claim 6, wherein the first semi-transparent region has a light transmittance of 30% to 50%;
the light transmittance of the second semi-transparent area is 30% -50%.
8. The method for preparing the array substrate according to claim 4, wherein the first photoresist is a negative photoresist, and/or;
the second photoresist is a negative photoresist, and/or
The third photoresist is a negative photoresist.
9. The method for manufacturing an array substrate according to claim 1, wherein the material of the first metal layer comprises copper; and/or
The material of the second metal layer comprises copper; and/or
The material of the transparent electrode comprises indium tin oxide.
10. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 9, comprising:
a glass substrate;
the grid is arranged on the glass substrate;
the insulating layer is arranged on the grid and the glass substrate;
the semiconductor is arranged on one side, far away from the grid, of the insulating layer;
the source-drain metal layer is arranged on one side, far away from the insulating layer, of the semiconductor, is provided with a channel and corresponds to the grid;
the passivation layer is arranged on the source drain metal layer, the channel and the insulating layer;
and the transparent electrode is arranged on the passivation layer and is connected with the source drain electrode metal layer through a contact hole.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013096A (en) * | 2021-03-01 | 2021-06-22 | 重庆先进光电显示技术研究院 | Preparation method of array substrate and array substrate |
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| CN113013096B (en) * | 2021-03-01 | 2023-06-02 | 重庆先进光电显示技术研究院 | Array substrate preparation method and array substrate |
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