CN111048488A - Bare core with electromagnetic shielding structure - Google Patents
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- CN111048488A CN111048488A CN201911361119.0A CN201911361119A CN111048488A CN 111048488 A CN111048488 A CN 111048488A CN 201911361119 A CN201911361119 A CN 201911361119A CN 111048488 A CN111048488 A CN 111048488A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 132
- 239000002184 metal Substances 0.000 claims abstract description 132
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000010931 gold Substances 0.000 claims description 38
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 35
- 229910052737 gold Inorganic materials 0.000 claims description 32
- 239000010949 copper Substances 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 229910052709 silver Inorganic materials 0.000 claims description 17
- 239000004332 silver Substances 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 107
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a bare chip with an electromagnetic shielding structure, belongs to the technical field of integrated circuits, and aims to solve the problems of complex process and high cost of the electromagnetic shielding structure commonly used for the integrated circuits. The scheme of the invention is as follows: building an integrated circuit DEVICE on a P-type substrate; tightly and orderly constructing a plurality of layers of deep silicon through holes DSV around an integrated circuit DEVICE, wherein the deep silicon through holes DSV are filled with high-conductivity conductors, the bottom ends of the deep silicon through holes DSV penetrate through an active layer of a P-type substrate, and the top ends of the deep silicon through holes DSV are connected with a physically grounded intermediate metal layer; the middle metal layer and the top metal layer are connected through a plurality of rows of parallel metal layer through holes via; any two middle metal layers are connected through a plurality of parallel metal layer through holes via; the top metal layer is located directly above the integrated circuit DEVICE.
Description
Technical Field
The invention belongs to the technical field of integrated circuits.
Background
Basic devices DVICE with different functions are manufactured through multiple processes on a single substrate, and the basic devices are interconnected by using multiple layers of metal to form an analog integrated circuit, a digital integrated circuit or a digital-analog hybrid circuit. Some high-precision and high-sensitivity analog circuits are easily interfered by digital circuits, and electromagnetic waves generated by other high-frequency equipment outside a chip can damage the integrity of output signals of the analog circuits, so that the quality of the integrated circuits is reduced, and the design difficulty of the integrated circuits is improved. In order to isolate an integrated circuit susceptible to electromagnetic interference from other circuits or an external space, it is a common practice to add a fully-enclosed metal plate outside a packaged chip according to the faraday cage shielding principle, or add a shielding metal layer in a packaging cavity during a bare chip packaging process. When high-frequency signals are incident to the shielding metal plate or the shielding metal layer, electromagnetic waves are continuously reflected, and finally damage is reduced to the minimum. The method for adding the metal plate has high cost, and the method for adding the shielding metal layer has complex realization process.
Disclosure of Invention
The invention aims to solve the problems of complex process and high cost of the common electromagnetic shielding structure of the integrated circuit, and provides the electromagnetic shielding structure designed at the front end of the integrated circuit.
The bare core with the electromagnetic shielding structure provides two technical schemes:
the first scheme is as follows: building a shielding structure by adopting DSV (Deep Silicon Via) technology, wherein the bare chip with the electromagnetic shielding structure comprises a P-type substrate 1, an integrated circuit DEVICE DEVICE2, a Deep Silicon Via DSV3, a middle metal layer 4, a metal layer Via5 and a top metal layer 6, and the P-type substrate 1 is physically connected with the GND;
building an integrated circuit DEVICE2 on a P-type substrate 1; building a plurality of layers of deep silicon through holes DSV3 around the integrated circuit DEVICE DEVICE2 in a close and orderly manner, wherein the deep silicon through holes DSV3 are filled with high-conductivity conductors, the bottom end of the deep silicon through hole DSV3 penetrates through the active layer of the P-type substrate 1, and the top end of the deep silicon through hole DSV3 is connected with the intermediate metal layer 4 which is physically grounded; the top end of the deep silicon through hole DSV3 is connected to the top metal layer 6 through one or more middle metal layers 4, the middle metal layers 4 are connected with the top metal layer 6 through a plurality of parallel metal layer through holes via5, and any two middle metal layers 4 are connected through a plurality of parallel metal layer through holes via 5;
the coverage area of the middle metal layer 4 is matched with the occupied area of the multiple layers of deep silicon through holes DSV 3;
the top metal layer 6 is located right above the integrated circuit DEVICE2, and the coverage area of the top metal layer 6 matches the area enclosed by the outermost deep through-silicon via DSV 3.
Preferably, deep through-silicon vias DSV3 are fabricated in the open area in the middle of integrated circuit DEVICE DEVICE 2.
Preferably, the metal layer structure further comprises a second-level metal layer 7, and the second-level metal layer 7 is connected with the top-level metal layer 6 and the middle metal layer 4 through a plurality of parallel metal layer through holes via 5.
Preferably, the bottom end of the deep through-silicon via DSV3 penetrates the active layer of the P-type substrate 1 to an insertion depth of 20% -50% of the thickness of the P-type substrate 1.
Preferably, the high conductivity conductor filled in the deep through silicon via DSV3 comprises aluminum, gold, silver or copper; the high conductivity conductor filled in the metal layer via5 comprises aluminum, gold, silver, or copper.
Preferably, the back gold 8 is adhered to the back surface of the P-type substrate 1 through a prepared conductive resin layer.
Preferably, the back gold 8 is made of aluminum, gold, silver or copper material.
Scheme II: building a shielding structure by using RDL (Re-Distribution Lines) technology, wherein the bare core with the electromagnetic shielding structure comprises a P-type substrate 1, an integrated circuit DEVICE2 and a metal layer through hole via 5;
an integrated circuit DEVICE2 is built on a P-type substrate 1, and the P-type substrate 1 is physically connected with a ground GND;
a final passivation layer 10 is formed over the PAD, a separate metal layer 11 is disposed over the final passivation layer 10, and a metal layer via5 is formed in the final passivation layer 10 for connecting the separate metal layer 11 and a ground PAD GND PAD9 of the PAD.
Preferably, the back gold 8 is adhered to the back surface of the P-type substrate 1 through a prepared conductive resin layer.
Preferably, the high conductivity conductor filled in the metal layer via5 comprises aluminum, gold, silver, or copper.
Preferably, the back gold 8 is made of aluminum, gold, silver or copper material.
The invention has the beneficial effects that: the invention designs the electromagnetic shielding structure at the front end of the integrated circuit chip, has simple realization process and low cost, solves the problems that the common electromagnetic shielding structure is used for performing electromagnetic shielding operation in the packaging process and after the packaging is finished, and the common scheme has complex process and high cost, and passes the electromagnetic interference test verification.
Drawings
Fig. 1 is a schematic structural diagram of a die with an electromagnetic shielding structure according to an embodiment, which is constructed by using DSV technology;
FIG. 2 is a top view of FIG. 1, with the intermediate metal layer and metal layer vias via omitted;
FIG. 3 is a schematic diagram of the scheme of FIG. 1 with the addition of a back gold;
FIG. 4 is a schematic diagram of the structure of the embodiment of FIG. 1 with multiple intermediate metal layers;
FIG. 5 is a schematic diagram of the scheme of FIG. 1 with the addition of a second top metal layer;
fig. 6 is a schematic structural diagram of a bare chip with an electromagnetic shielding structure according to the fifth embodiment, which is constructed by using the RDL technique;
FIG. 7 is a top view of FIG. 6;
fig. 8 is a schematic diagram of the scheme of fig. 6 with the addition of back gold.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
The first embodiment is as follows: the following describes the present embodiment with reference to fig. 1, 2 and 4, the die with electromagnetic shielding structure according to the present embodiment is constructed by using DSV technology, and includes a P-type substrate 1, an integrated circuit DEVICE2, a deep through silicon via DSV3, an intermediate metal layer 4, a metal layer via5 and a top metal layer 6, the P-type substrate 1 is physically connected to the ground GND;
building an integrated circuit DEVICE2 on a P-type substrate 1; building a plurality of layers of deep silicon through holes DSV3 around the integrated circuit DEVICE DEVICE2 in a close and orderly manner, wherein the deep silicon through holes DSV3 are filled with high-conductivity conductors, the bottom end of the deep silicon through hole DSV3 penetrates through the active layer of the P-type substrate 1, and the top end of the deep silicon through hole DSV3 is connected with the intermediate metal layer 4 which is physically grounded; the top end of the deep silicon through hole DSV3 is connected to the top metal layer 6 through one or more middle metal layers 4, the middle metal layers 4 are connected with the top metal layer 6 through a plurality of parallel metal layer through holes via5, and any two middle metal layers 4 are connected through a plurality of parallel metal layer through holes via 5;
the coverage area of the middle metal layer 4 is matched with the occupied area of the multiple layers of deep silicon through holes DSV 3;
the top metal layer 6 is located right above the integrated circuit DEVICE2, and the coverage area of the top metal layer 6 matches the area enclosed by the outermost deep through-silicon via DSV 3.
The basic device is built on a P-type Substrate (P + + Substrate) through a multi-process, and the P-type Substrate 1 is made of materials such as but not limited to: silicon, germanium, gallium arsenide, elemental devices including but not limited to: MOS tube, bipolar transistor, resistance, capacitance, inductance. And then, constructing the basic devices into devices with specific functions by using a multilayer metal interconnection mode: an integrated circuit DEVICE2, the integrated circuit DEVICE2 such as but not limited to: Trans-Impedance Amplifier TIA (Trans-Impedance Amplifier), limiting Amplifier la (limiting Amplifier), Transceiver chip Transceiver, phase-locked loop pll (phase locked loop), clock Data recovery cdr (clock Data recovery), analog-to-digital converter adc (analog digital converter), and digital Logic. In an integrated circuit constructed by the above process, noise signals will be mutually transmitted to the integrated circuit DEVICE2 on the same substrate through the P-type substrate 1 or other media, and external electromagnetic interference will also affect various performances of the packaged integrated circuit DEVICE 2. It is therefore desirable to electromagnetically shield the vulnerable integrated circuit DEVICE 2.
The deep through-silicon vias DSV penetrate the active layer of the P-type substrate 1 and are inserted into the substrate by 20-50% of the thickness, and the deep through-silicon vias DSV need to be arranged in parallel in multiple rows, closely and orderly around the integrated circuit DEVICE 2. After the deep through-silicon vias DSV are built, the holes are filled with a high conductivity conductor (such as, but not limited to, aluminum (Al), gold (Au), silver (Ag), copper (Cu)).
The top end of the deep through-silicon via DSV connects to an intermediate metal layer 4 (the material of the intermediate metal layer is such as, but not limited to, aluminum (Al), gold (Au), silver (Ag), copper (Cu)) that has been physically connected to ground GND. The high conductivity conductor filled in the metal layer via5 comprises aluminum, gold, silver, or copper.
The intermediate Metal layer 4 is in turn connected to the Top Metal layer 6(Top Metal) of the semiconductor process used by multiple parallel, closely spaced and ordered Metal layer vias via. The top metal layer 6 must be as thick as possible and extend continuously with a smooth and flat surface that overlies the integrated circuit DEVICE 2. Therefore, the electromagnetic wave can be reflected to the maximum extent, the anti-interference capability is improved, and the electromagnetic wave penetrating through the metal can be continuously attenuated due to the thickness of the metal.
The number of the intermediate metal layers 4 is one or more, the implementation process supports 7 layers of metal at most (the total number of the intermediate metal layers and the top metal layer), and the number of the intermediate metal layers 4 is not hard to be specified under the limitation of the maximum level and can be determined according to the requirement.
Both Via and DSV described above need to be distributed as much as possible around the integrated circuit DEVICE DEVICE2 to improve immunity to electromagnetic interference.
Finally, the metal conductors in the whole structure are uniformly and densely connected to the ground GND. Therefore, a three-dimensional faraday cage with electromagnetic shielding function is formed through the above operation, and the integrated circuit DEVICE2 can be effectively protected from external electromagnetic interference.
The second embodiment is as follows: the present embodiment is described below with reference to fig. 3, and differs from the first embodiment in that a back gold 8 is bonded to the back surface of the P-type substrate 1 via a prepared conductive resin layer.
On the back of the P-type Substrate (P + + Substrate), a layer of conductive resin is formed and then a back gold 8 (backslidemetal) is adhered, wherein the back gold 8 is made of a metal material such as, but not limited to: aluminum (Al), gold (Au), silver (Ag) and copper (Cu), and the electromagnetic resistance of the structure can be further enhanced by adding the metal.
The third concrete implementation mode: the present embodiment will be described with reference to fig. 5, and is different from the first or second embodiment in that the present embodiment further includes a sub-top metal layer 7, and the sub-top metal layer 7, the top metal layer 6, and the middle metal layer 4 are connected by a plurality of parallel metal layer through holes via 5.
If the thickness of the top metal layer 6 cannot meet the minimum requirement of magnetic penetration depth at a high resonant frequency, a second top metal layer 7 can be reserved, an interlayer oxide ILO is arranged between the top metal layer 7 and the top metal layer 6(to prevent short circuit between the top metal layer 7 and the top metal layer 6), and a metal layer through hole via5 is built in the interlayer oxide layer to realize the electrical connection between the top metal layer 7 and the top metal layer 6; the deep through silicon via DSV3 is connected to the next-to-top metal layer 7 through one or more intermediate metal layers 4, and other connection relations are unchanged.
The fourth concrete implementation mode: this embodiment differs from embodiments one to three in that a deep through-silicon via DSV3 is built in the open area in the middle of the integrated circuit DEVICE 2.
Deep through-silicon vias DSV need to be built if there is also an open area inside the integrated circuit DEVICE2 (without affecting the normal function of the circuit), so as to further improve the anti-electromagnetic interference capability.
The fifth concrete implementation mode: the following describes the present embodiment with reference to fig. 6 and 7, the bare chip with the electromagnetic shielding structure in the present embodiment includes a P-type substrate 1, an integrated circuit DEVICE2, and a metal layer via 5;
an integrated circuit DEVICE2 is built on a P-type substrate 1, and the P-type substrate 1 is physically connected with a ground GND;
a final passivation layer 10 is formed over the PAD, a separate metal layer 11 is disposed over the final passivation layer 10, and a metal layer via5 is formed in the final passivation layer 10 for connecting the separate metal layer 11 and a ground PAD GND PAD9 of the PAD.
The high conductivity conductor filled in the metal layer via5 comprises aluminum, gold, silver, or copper.
The basic device is built on a P-type Substrate (P + + Substrate) through a multi-process, and the P-type Substrate 1 is made of materials such as but not limited to: silicon, germanium, gallium arsenide, elemental devices including but not limited to: MOS tube, bipolar transistor, resistance, capacitance, inductance. And then, constructing the basic devices into devices with specific functions by using a multilayer metal interconnection mode: an integrated circuit DEVICE2, the integrated circuit DEVICE2 such as but not limited to: Trans-Impedance Amplifier TIA (Trans-Impedance Amplifier), limiting Amplifier la (limiting Amplifier), Transceiver chip Transceiver, phase-locked loop pll (phase locked loop), clock Data recovery cdr (clock Data recovery), analog-to-digital converter adc (analog digital converter), and digital Logic. In an integrated circuit constructed by the above process, noise signals will be mutually transmitted to the integrated circuit DEVICE2 on the same substrate through the P-type substrate 1 or other media, and external electromagnetic interference will also affect various performances of the packaged integrated circuit DEVICE 2. It is therefore desirable to electromagnetically shield the vulnerable integrated circuit DEVICE 2.
The P-type substrate is physically connected to ground GND.
After the PAD is fully established, a final passivation layer 10 is fabricated above it to protect the underlying circuitry. The Final Passivation layer 10 above the ground PAD GND PAD builds a metal layer via5, the hole is filled with a high conductivity conductor (such as, but not limited to, aluminum (Al), gold (Au), silver (Ag), copper (Cu)), and finally a separate metal layer 11 (such as, but not limited to, aluminum (Al), gold (Au), silver (Ag), copper (Cu)) is fabricated above the Final Passivation layer Final footprint. The free-standing Metal layer Metal must be as thick as possible and extend continuously with a smooth and planar surface overlying the integrated circuit DEVICE 2. Therefore, the electromagnetic wave can be reflected to the maximum extent, the anti-interference capability is improved, and the electromagnetic wave penetrating through the metal can be continuously attenuated due to the thickness of the metal. From this structure, a faraday cage is formed to shield the surrounding electromagnetic interference.
The sixth specific implementation mode: the present embodiment, in which a back gold 8 is bonded to the back surface of the P-type substrate 1 via a prepared conductive resin layer, will be described below with reference to fig. 8.
On the back of the P-type Substrate (P + + Substrate), a layer of conductive resin is formed and then a back gold 8 (backslidemetal) is adhered, wherein the back gold 8 is made of a metal material such as, but not limited to: aluminum (Al), gold (Au), silver (Ag) and copper (Cu), and the electromagnetic resistance of the structure can be further enhanced by adding the metal.
Although the embodiments of the present invention have been described above, the above descriptions are only for the convenience of understanding the present invention, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. The bare core with the electromagnetic shielding structure is characterized by comprising a P-type substrate (1), an integrated circuit DEVICE (2), a deep silicon through hole DSV (3), a middle metal layer (4), a metal layer through hole via (5) and a top metal layer (6), wherein the P-type substrate (1) is physically connected with a ground GND;
building an integrated circuit DEVICE (2) on a P-type substrate (1); building a plurality of layers of deep silicon through holes DSV (3) in a close and ordered manner around an integrated circuit DEVICE DEVICE (2), wherein a high-conductivity conductor is filled in the deep silicon through holes DSV (3), the bottom ends of the deep silicon through holes DSV (3) penetrate through an active layer of a P-type substrate (1), and the top ends of the deep silicon through holes DSV (3) are connected with a physically-grounded middle metal layer (4); the top end of the deep silicon through hole DSV (3) is connected to the top metal layer (6) through one or more middle metal layers (4), the middle metal layers (4) are connected with the top metal layer (6) through a plurality of rows of parallel metal layer through holes via (5), and any two middle metal layers (4) are connected through a plurality of rows of parallel metal layer through holes via (5);
the coverage area of the middle metal layer (4) is matched with the occupied area of the multi-layer deep silicon through hole DSV (3);
the top metal layer (6) is located right above the integrated circuit DEVICE (2), and the coverage area of the top metal layer (6) is matched with the enclosed area of the outermost deep silicon through hole DSV (3).
2. The die with electromagnetic shielding structure as claimed in claim 1, characterized in that a deep through-silicon via DSV (3) is built in the open area in the middle of the integrated circuit DEVICE (2).
3. The die with the electromagnetic shielding structure as recited in claim 2, further comprising a secondary top metal layer (7), wherein the secondary top metal layer (7) is connected with the top metal layer (6) and the middle metal layer (4) through a plurality of parallel metal layer through holes via (5).
4. The die with electromagnetic shielding structure according to any of claims 1 to 3, wherein the bottom end of the deep through-silicon-via DSV (3) penetrates the active layer of the P-type substrate (1) to a depth of 20% to 50% of the thickness of the P-type substrate (1).
5. The die with the electromagnetic shielding structure as claimed in any of claims 1 to 3, wherein the high-conductivity conductor filled in the deep through-silicon-via DSV (3) comprises aluminum, gold, silver or copper; the high conductivity conductor filled in the metal layer via (5) comprises aluminum, gold, silver or copper.
6. The die with the electromagnetic shielding structure as recited in claim 4, characterized in that the back gold (8) is adhered to the back surface of the P-type substrate (1) through a prepared conductive resin layer.
7. The bare core with the electromagnetic shielding structure is characterized by comprising a P-type substrate (1), an integrated circuit DEVICE (2) and a metal layer through hole via (5);
an integrated circuit DEVICE (2) is built on a P-type substrate (1), and the P-type substrate (1) is physically connected with a ground GND;
a final passivation layer (10) is made above the PAD PAD, a separate metal layer (11) is arranged above the final passivation layer (10), and a metal layer via (5) is built in the final passivation layer (10) for connecting the separate metal layer (11) and a ground PAD GND PAD (9) in the PAD PAD.
8. The die with the electromagnetic shielding structure as recited in claim 7, characterized in that the back gold (8) is adhered to the back surface of the P-type substrate (1) through a prepared conductive resin layer.
9. The die with the electromagnetic shielding structure as recited in claim 7, wherein the high-conductivity conductor filled in the metal layer via (5) comprises aluminum, gold, silver or copper.
10. The die with the electromagnetic shielding structure as claimed in claim 6 or 8, characterized in that the back gold (8) is made of aluminum, gold, silver or copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911361119.0A CN111048488A (en) | 2019-12-25 | 2019-12-25 | Bare core with electromagnetic shielding structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911361119.0A CN111048488A (en) | 2019-12-25 | 2019-12-25 | Bare core with electromagnetic shielding structure |
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| CN111048488A true CN111048488A (en) | 2020-04-21 |
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| CN201911361119.0A Withdrawn CN111048488A (en) | 2019-12-25 | 2019-12-25 | Bare core with electromagnetic shielding structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883516A (en) * | 2020-07-24 | 2020-11-03 | 青岛歌尔智能传感器有限公司 | Packaging structure and packaging method of integrated module and electronic equipment |
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|---|---|---|---|---|
| DE10309614A1 (en) * | 2003-03-05 | 2004-09-23 | Infineon Technologies Ag | Semiconductor structure and production process for high frequency uses has screen between semiconductor elements passing through substrate to underside metallization |
| US20100078777A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip Radio Frequency Shield with Interconnect Metallization |
| US20120208320A1 (en) * | 2008-09-30 | 2012-08-16 | Infineon Technologies Ag | On-Chip RF Shields with Front Side Redistribution Lines |
| US9659877B2 (en) * | 2006-05-12 | 2017-05-23 | Infineon Technologies Ag | Shielding device |
-
2019
- 2019-12-25 CN CN201911361119.0A patent/CN111048488A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10309614A1 (en) * | 2003-03-05 | 2004-09-23 | Infineon Technologies Ag | Semiconductor structure and production process for high frequency uses has screen between semiconductor elements passing through substrate to underside metallization |
| US9659877B2 (en) * | 2006-05-12 | 2017-05-23 | Infineon Technologies Ag | Shielding device |
| US20100078777A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip Radio Frequency Shield with Interconnect Metallization |
| US20120208320A1 (en) * | 2008-09-30 | 2012-08-16 | Infineon Technologies Ag | On-Chip RF Shields with Front Side Redistribution Lines |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883516A (en) * | 2020-07-24 | 2020-11-03 | 青岛歌尔智能传感器有限公司 | Packaging structure and packaging method of integrated module and electronic equipment |
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Application publication date: 20200421 |