CN111048410A - VDMOS Pbody injection shadow elimination process - Google Patents
VDMOS Pbody injection shadow elimination process Download PDFInfo
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- CN111048410A CN111048410A CN201911342096.9A CN201911342096A CN111048410A CN 111048410 A CN111048410 A CN 111048410A CN 201911342096 A CN201911342096 A CN 201911342096A CN 111048410 A CN111048410 A CN 111048410A
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- pbody
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- 238000002347 injection Methods 0.000 title claims abstract description 23
- 239000007924 injection Substances 0.000 title claims abstract description 23
- 238000003379 elimination reaction Methods 0.000 title claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 238000002513 implantation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention discloses a VDMOS Pbody injection shadow elimination process, wherein a silicon wafer is positioned on a wafer carrier in a high vacuum chamber and is vertically placed, a beam is injected into the silicon wafer at an angle of 7 degrees relative to the silicon wafer and is scanned in the X direction, the wafer carrier moves up and down in the Y direction, and the beam is injected in a plurality of directions according to the total dose; the invention still adopts the 7-degree angle injection under the original injection condition, thereby preventing the occurrence of channel effect, but the invention divides the total dose into 4 directions for injection, thereby preventing the generation of shadow effect, improving the yield of the product from 95 percent to 98 percent and improving the yield by 3 percent. The uniformity of the Pbody structure is improved, the starting voltage is stabilized, and the starting voltage is stabilized to fluctuate from the initial fluctuation range of 2.8-3.2V to 2.9-3.0; the leakage of the MOS chip is reduced from the initial 50nA to 10nA, so that the yield of the finished silicon chip is improved.
Description
Technical Field
The invention relates to a VDMOS Pbody injection shadow elimination process.
Background
Developed rapidly since the 80 sVery large scale integrated circuitThe technology injects new vitality into a high-voltage heavy-current semiconductor, a batch of novel voice-operated power amplification devices are produced, and the most representative product is a VDMOS voice effect power transistor. Such a current vertically flowing double diffused MOS device is a voltage controlled device. Under the control of proper grid voltage, the surface of the semiconductor is inverted to form a conductive channel, so that proper current flows between the drain electrode and the source electrode
VDMOS combines the advantages of bipolar transistors and common MOS devices. Compared with a bipolar transistor, the switching speed and the switching loss of the bipolar transistor are small; the input impedance is high, and the driving power is low; the frequency characteristic is good; the transconductance is highly linear. Particularly, the device has a negative temperature coefficient, does not have the problem of secondary penetration of bipolar power, and has a large safe working area. Therefore, VDMOS is an ideal power device for both switching and linear applications.
VDMOS devices are now widely used in a variety of applications, includingMotor speed regulationAn inverter, an uninterruptible power supply,Opening device Power-offAn electronic switch,High-fidelity sound equipmentAutomotive electrical appliance andelectronic ballastAnd the like. Since the cost performance ratio of VDMOS is already superior to that of bipolar power devices, its share in the power device market has exceeded 40% and will continue to rise.
The VDMOS manufacturing process comprises repeated processing of diffusion, injection, photoetching, etching, sputtering … … and the like, the flow is as many as 200 steps, the time consumption is usually more than 40 days, the process is complex, the difficulty is high, and the yield of products is often abnormal. The VDMOSPbody is formed by mainly implanting doped P type ions B + by an ion implanter and then forming a Pbody structure by the process of a diffusion furnace tube. In the implantation process, in order to prevent the channel effect, the implantation of B + ions is usually performed at an angle of 7 degrees, because the gate oxide thickness + poly crystal is generally in
The step is too high. When 7 degrees are injected, the through plate is still, the shadow effect is easily generated at the 90 degrees position of the bottom of the step, ions cannot be injected into the position, and the uniformity of the whole Pbody structure is poor. The problems of unstable starting voltage, electric leakage and the like are easily caused, so that the device fails, and the yield of finished silicon wafers is reduced.
Disclosure of Invention
In order to solve the defect that the shadow effect is easily generated at the 90-degree position of the bottom of the step during VDMOS Pbody injection in the prior art, a novel injection process is provided.
A VDMOS Pbody injection shadow eliminating process is characterized in that a silicon wafer is placed on a wafer carrier in a high vacuum chamber and is vertically placed, beam current is injected into the silicon wafer at an angle of 7 degrees relative to the silicon wafer and is scanned in the X direction, meanwhile, the wafer carrier moves up and down in the Y direction, and the beam current is injected in a plurality of directions according to the total dose.
Preferably, the beam is implanted in four directions according to the total dose, and equal doses are implanted in each direction.
Further, the flat edge of the silicon chip faces downwards and anticlockwise by 0-30 degrees, and the silicon chip is used as a starting point to inject 25% of dosage and stop injecting; then the silicon chip rotates 90 degrees in the anticlockwise direction, 25 percent of dosage is injected for the 2 nd time, and the injection is suspended; the silicon chip continues to rotate 90 degrees in the anticlockwise direction, 25% of dosage is injected in the 3 rd time, and the injection is suspended; and (4) rotating the silicon wafer by 90 degrees in the counterclockwise direction, and implanting 25% of dose for the 4 th time to finish implantation.
Furthermore, the flat edge of the silicon wafer is used as the initial implantation position when the flat edge of the silicon wafer faces downwards and anticlockwise by 22.5 degrees.
During the Pbody implant process, the wafer is placed on a stage in a high vacuum chamber, standing upright. The beam current is injected into the silicon chip at an angle of 7 degrees relative to the silicon chip to scan in the X direction, and meanwhile, the slide holder moves up and down in the Y direction, and the silicon chip is not moved. The invention still adopts the 7-degree angle injection under the original injection condition, thereby preventing the occurrence of channel effect, but the invention divides the total dose into 4 directions for injection, thereby preventing the generation of shadow effect, improving the yield of the product from 95 percent to 98 percent and improving the yield by 3 percent. The uniformity of the Pbody structure is improved, the starting voltage is stabilized, and the starting voltage is stabilized to fluctuate from the initial fluctuation range of 2.8-3.2V to 2.9-3.0; the leakage of the MOS chip is reduced from the initial 50nA to 10nA, so that the yield of the finished silicon chip is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
In the drawings:
FIG. 1 shows an initial implant position;
FIG. 2 shows the 2 nd injection position;
FIG. 3 shows the 3 rd injection position;
FIG. 4 shows the 4 th injection position;
wherein 1 is Pbody, 2 is implant and 3 is shadow.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Examples
A VDMOS Pbody injection shadow elimination process is characterized by comprising the following steps:
1) the silicon chip is arranged on a chip carrying table in the high vacuum chamber and is vertically arranged. The beam current is injected into the silicon chip at an angle of 7 degrees relative to the silicon chip to scan in the X direction, and the slide holder moves up and down in the Y direction.
2) The flat edge of the silicon wafer faces downwards and anticlockwise by 22.5 degrees, 25% of dosage is implanted as the beginning, and the implantation is suspended.
3) The wafer is rotated 90 degrees counterclockwise, 25% of the dose is implanted in the 2 nd time, and the implantation is suspended.
4) The wafer continues to rotate 90 degrees counterclockwise, 25% dose is implanted for the 3 rd time, and the implantation is suspended.
5) And (4) rotating the silicon wafer by 90 degrees in the counterclockwise direction, and implanting 25% of dose for the 4 th time to finish implantation.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A VDMOS Pbody injection shadow elimination process is characterized in that a silicon wafer is placed on a wafer carrier in a high vacuum chamber and is vertically placed, beam current is injected into the silicon wafer at an angle of 7 degrees relative to the silicon wafer and is scanned in the X direction, the wafer carrier moves up and down in the Y direction, and the beam current is injected in multiple directions according to the total dose.
2. The VDMOS Pbody implant shadow removal process of claim 1, wherein the beam current is divided into four directions of implantation according to a total dose, with equal doses implanted in each direction.
3. The VDMOS Pbody implantation shadow elimination process of claim 2, wherein the wafer flat edge is oriented downward counter-clockwise 0-30 degrees, with 25% dose implanted as an initial, and implant is suspended; then the silicon chip rotates 90 degrees in the anticlockwise direction, 25 percent of dosage is injected for the 2 nd time, and the injection is suspended; the silicon chip continues to rotate 90 degrees in the anticlockwise direction, 25% of dosage is injected in the 3 rd time, and the injection is suspended; and (4) rotating the silicon wafer by 90 degrees in the counterclockwise direction, and implanting 25% of dose for the 4 th time to finish implantation.
4. The VDMOS Pbody implantation shadow elimination process of claim 3, wherein the wafer flat edge is positioned 22.5 degrees down counter-clockwise as a starting implantation position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911342096.9A CN111048410A (en) | 2019-12-24 | 2019-12-24 | VDMOS Pbody injection shadow elimination process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911342096.9A CN111048410A (en) | 2019-12-24 | 2019-12-24 | VDMOS Pbody injection shadow elimination process |
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| Publication Number | Publication Date |
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| CN111048410A true CN111048410A (en) | 2020-04-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911342096.9A Pending CN111048410A (en) | 2019-12-24 | 2019-12-24 | VDMOS Pbody injection shadow elimination process |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
| US4877962A (en) * | 1987-04-30 | 1989-10-31 | Mitsubishi Denki Kabushiki Kaisha | Ion implantation method |
| JPH02189850A (en) * | 1989-01-13 | 1990-07-25 | Tokyo Electron Ltd | Ion implantation method |
| CN1630047A (en) * | 2003-12-16 | 2005-06-22 | 松下电器产业株式会社 | Method and apparatus for fabricating semiconductor device |
-
2019
- 2019-12-24 CN CN201911342096.9A patent/CN111048410A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
| US4877962A (en) * | 1987-04-30 | 1989-10-31 | Mitsubishi Denki Kabushiki Kaisha | Ion implantation method |
| JPH02189850A (en) * | 1989-01-13 | 1990-07-25 | Tokyo Electron Ltd | Ion implantation method |
| CN1630047A (en) * | 2003-12-16 | 2005-06-22 | 松下电器产业株式会社 | Method and apparatus for fabricating semiconductor device |
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Application publication date: 20200421 |