CN111048130B - Magnetic random access memory - Google Patents
Magnetic random access memory Download PDFInfo
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- CN111048130B CN111048130B CN201811191866.XA CN201811191866A CN111048130B CN 111048130 B CN111048130 B CN 111048130B CN 201811191866 A CN201811191866 A CN 201811191866A CN 111048130 B CN111048130 B CN 111048130B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
Abstract
The present application provides a magnetic random access memory. The magnetic random access memory includes: a substrate; the driver groups are positioned on the surface of the substrate and are sequentially arranged along a direction far away from the substrate, each driver group comprises one or more drivers arranged at intervals along a first direction, the distance between the center of each driver in one driver group and the substrate is the same, the projection of at least one driver in each driver group on the substrate is overlapped with the projection of at least one driver in the adjacent driver group on the surface of the substrate, the driver group with the largest distance between the driver groups and the substrate is a top layer driver group, and the first direction is vertical to the thickness direction of the substrate; the MTJ bit cells are arranged at intervals along the first direction and are positioned on the side, far away from the substrate, of the top driver group, and one or more MTJ bit cells are correspondingly and electrically connected with one or more drivers. The storage density of the magnetic random access memory is large.
Description
Technical Field
The present application relates to the field of memory, and more particularly, to a magnetic random access memory.
Background
Because the current write current of the MTJ bit cell is large, in the conventional 1T1R-MRAM memory, the width of the MOS transistor as the driver must be made large enough to ensure the write power supply capability, resulting in that the area of the transistor in the IT1R structure is significantly larger than that of the MTJ, which limits the MRAM storage density. The above 1T1R indicates that one transistor corresponds to one memory bit.
The MTJ bit in the MRAM memory is complex in structure and material, the MTJ film is high in preparation cost, the requirement on the roughness of the substrate surface is high, and the MTJ magnetoelectric property is sensitive to temperature, so that the MRAM is not suitable for improving the storage density in a 3D stacking mode.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a magnetic random access memory, so as to solve the problem of low storage density of the magnetic random access memory in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a magnetic random access memory including: a substrate; a plurality of driver groups, each of the driver groups being located on a surface of the substrate, the plurality of driver groups being sequentially arranged in a direction away from the substrate, each of the driver groups including one or more drivers arranged at intervals in a first direction, centers of the drivers in one of the driver groups being located at the same distance from the substrate, projections of at least one of the drivers in each of the driver groups on the substrate overlapping projections of at least one of the drivers in an adjacent one of the driver groups on the surface of the substrate, the driver group of the plurality of driver groups having the largest distance from the substrate being a top driver group, the first direction being perpendicular to a thickness direction of the substrate; a plurality of MTJ bits spaced along the first direction are located on a side of the top driver group away from the substrate, and one or more of the MTJ bits are electrically connected to one or more of the drivers.
Further, each of the driver groups includes a plurality of identical drivers, a projection of the driver of each of the driver groups on the substrate is overlapped with a projection of the driver of an adjacent driver group on the substrate in a one-to-one correspondence, the drivers are electrically connected to the MTJ bit cells in a one-to-one correspondence, and two of the MTJ bit cells electrically connected to the two drivers of which projections on the substrate are overlapped in a one-to-one correspondence are adjacent to each other.
Further, the projections of the drivers in each of the driver groups on the substrate are overlapped with the projections of the drivers in the adjacent driver groups on the substrate in a one-to-one correspondence.
Furthermore, the magnetic random access memory further includes a plurality of isolation medium layers, each isolation medium layer is disposed on the surface of the substrate, the isolation medium layers are sequentially stacked along a direction away from the substrate, each driver group is located in at least one isolation medium layer, and the MTJ bits are located in at least one isolation medium layer.
Further, the magnetic random access memory further includes a plurality of via groups, each of the via groups includes at least one via, the height of the via in at least two of the via groups is different, each of the vias is located in the isolation dielectric layer, at least some of the via groups are in one-to-one correspondence with the driver group, and the via in one of the via groups corresponding to the driver group is used to electrically connect one of the MTJ bit cells and one of the drivers in one of the driver groups.
Further, the mram includes at least one driving interconnection group, the driving interconnection group is located in the isolation dielectric layer, the driving interconnection group includes a plurality of driving interconnection metal portions arranged at intervals along the first direction, and at least one of the driving interconnection metal portions in the driving interconnection group is used for electrically connecting the through holes and the drivers in a one-to-one correspondence.
Further, the two driver groups are a first driver group and a second driver group, respectively, the first driver group is located on the surface of the substrate, the second driver group is located on a side of the first driver group away from the substrate, the first driver group includes a plurality of first drivers, and the second driver group includes a plurality of second drivers.
Further, the driver is a MOSFET including a source, a gate, and a drain, the magnetic random access memory further includes a plurality of source lines provided at intervals, a plurality of word lines provided at intervals, and a plurality of bit lines provided at intervals, the source lines are electrically connected to the sources in a one-to-one correspondence, the word lines are electrically connected to the driver groups in a one-to-one correspondence, one of the word lines is electrically connected to the gate of each of the drivers of the driver groups, and the bit lines are electrically connected to the MTJ bit cells in a one-to-one correspondence.
Further, a projection of each of the MTJ bits on the surface of the substrate is located inside a projection of the corresponding electrically connected driver on the surface of the substrate, and each of the MTJ bits is located inside a bottom electrode, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode, which are sequentially stacked.
Further, all the via holes for electrically connecting the MTJ bit cell and the driver have the same resistance value.
By applying the technical scheme of the application, the plurality of stacked driver groups are arranged in the magnetic random access memory, and the projections of the drivers in the adjacent driver groups on the surface of the substrate have overlapped parts, so that compared with the prior art, the drivers are arranged in a layered mode in a vertical space, the areal density of the drivers in the vertical direction is improved, the areal density of the corresponding MTJ storage bit is correspondingly improved, and finally the storage density of the magnetic random access memory is improved compared with the prior art. Moreover, while the memory density is increased, the processing difficulty of the most challenging MTJ memory bit is not increased, so that the high-density magnetic random access memory has a simple manufacturing process and low manufacturing cost.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a circuit schematic of an embodiment of a magnetic random access memory according to the present application;
fig. 2 shows a schematic structural diagram of a magnetic random access memory in embodiment 1 of the present application;
fig. 3 shows a schematic structural diagram of the magnetic random access memory in embodiment 2 of the present application.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a driver group; 21. a first driver group; 22. a second driver group; 200. a driver; 210. a first driver; 220. a second driver; 30. isolating the dielectric layer; 40. a group of through holes; 50. driving the interconnect group; 500. a drive interconnect metal portion; 60. an MTJ bit; 70. a source line; 80. a word line; 90. a bit line; 81. a first word line; 82. a second word line; 41. a first through hole; 42. a second through hole; 43. a third through hole; 44. a fourth via hole; 45. a fifth through hole; 46. a sixth through hole; 47. a seventh via hole; 48. an eighth through hole; 810. a first word line extraction electrode; 820. a second word line extraction electrode; 61. a bottom electrode; 62. an MTJ portion; 63. a top electrode; 100. and other interconnection metal portions.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the prior art, due to the large write current of the MTJ bit cell, in the conventional 1T1R-MRAM magnetic random access memory device, the width of the MOS transistor must be made large enough to ensure the power supply capability, and as a result, the area of the transistor in the IT1R structure is significantly larger than that of the MTJ, which limits the MRAM storage density and makes the storage density of the magnetic random access memory small.
In an exemplary embodiment of the present application, a magnetic random access memory is provided, as shown in fig. 2 and 3, which includes a substrate 10, a plurality of driver groups 20, and a plurality of MTJ bits 60 spaced along the first direction. Wherein each of the driver groups 20 is located on the surface of the substrate 10, the plurality of driver groups 20 are sequentially arranged along a direction away from the substrate 10, each of the driver groups 20 includes one or more drivers 200 spaced apart along a first direction, that is, each of the driver groups includes at least one driver, when a driver group includes a plurality of drivers, the plurality of drivers are sequentially arranged and spaced apart along the first direction, the center of each of the drivers 200 in one of the driver groups 20 is at the same distance from the substrate 10, that is, at the same distance from the same surface of the substrate, the projection of at least one of the drivers 200 in each of the driver groups 20 on the substrate 10 overlaps the projection of at least one of the drivers 200 in an adjacent one of the driver groups 20 on the surface of the substrate 10, and, in the plurality of the driver groups 20, the driver group 20 having the largest distance from the substrate 10 is a top driver group, and the first direction is perpendicular to the thickness direction of the substrate. As shown in fig. 2 and 3, and the first direction in these two figures is also perpendicular to the page or computer screen. A plurality of MTJ bits 60 arranged at intervals along a first direction, that is, a plurality of MTJ bits 60 arranged sequentially and at intervals along the first direction, the MTJ bits 60 being located at a side of the top driver group away from the substrate 10, one or more of the MTJ bits 60 being electrically connected to one or more of the drivers 200, that is, one driver being electrically connected to one MTJ bit, that is, 1T 1R; one driver can be electrically connected with a plurality of MTJ bit cells correspondingly, namely 1 TNR; alternatively, a plurality of drivers are electrically connected to one MTJ bit, NT1R, respectively.
In the magnetic random access memory, a plurality of stacked driver groups are arranged, and projections of drivers in adjacent driver groups on the surface of a substrate have overlapped parts, so that compared with the prior art, the drivers are arranged in a layered mode in a vertical space, the areal density of the drivers in the vertical direction is improved, the areal density of corresponding MTJ storage bits is correspondingly improved, and finally the storage density of the magnetic random access memory is improved compared with the prior art. Moreover, while the memory density is increased, the processing difficulty of the most challenging MTJ memory bit is not increased, so that the high-density magnetic random access memory has a simple manufacturing process and low manufacturing cost.
The magnetic random access memory of the invention can be RRAM, PCRAM or MRAM, etc.
In order to further increase the storage density of the magnetic random access memory, in an embodiment of the present application, as shown in fig. 2 and 3, each of the driver groups 20 includes a plurality of identical drivers 200, a projection of the driver 200 in each of the driver groups 20 on the substrate 10 is overlapped with a projection of the driver 200 in an adjacent driver group 20 on the substrate 10 in a one-to-one correspondence, and two electrically connected MTJ bit cells 60 of two correspondingly overlapped drivers 200 in a one-to-one correspondence are adjacent to each other in a projection on the substrate 10.
In the present application, "overlapping" means that there is an overlapping portion, and specifically, only a portion may be overlapped, or all of them may be overlapped, that is, overlapped.
As shown in fig. 3, in an embodiment of the present application, a projection of the driver 200 in each of the driver groups 20 on the substrate 10 is overlapped with a projection of the driver 200 in an adjacent driver group 20 on the substrate 10 in a one-to-one correspondence. This minimizes the width of the plurality of drivers, thereby further increasing the storage density of the magnetic random access memory.
Specifically, as shown in fig. 2 and 3, the magnetic random access memory of the present application further includes a plurality of isolation medium layers 30, each isolation medium layer 30 is disposed on a surface of the substrate 10, the isolation medium layers 30 are sequentially stacked along a direction away from the substrate 10, each driver group 20 is located in at least one isolation medium layer 30, and a plurality of MTJ bits 60 are located in at least one isolation medium layer 30. The number of the isolation dielectric layers is different for different processes, and those skilled in the art can set an appropriate number of isolation dielectric layers according to actual conditions as long as the number of the isolation dielectric layers is larger than that of the driver groups.
In another embodiment of the present application, as shown in fig. 2 and 3, the magnetic random access memory further includes a plurality of via groups 40, each of the via groups 40 includes at least one via, and the height of the via in at least two of the via groups 40 is different, such as a first via 41 and a second via 42 shown in fig. 2 and 3, each of the vias is located in one of the isolation dielectric layers 30, and may be located in one of the isolation dielectric layers, such as the via with the smaller height of fig. 2 and 3; it is also possible to locate in multiple isolation dielectric layers, such as the highly larger vias in fig. 2 and 3. At least some of the plurality of via groups 40 are in one-to-one correspondence with the driver groups 20, and the via in one of the via groups 40 corresponding to the driver groups 20 is used to electrically connect one of the MTJ bit cells and one of the drivers 200 in one of the driver groups 20.
It should be noted that the through hole in this application is a so-called through hole in a semiconductor, and the through hole is actually a conductive through hole, that is, a hollow through hole is filled with a conductor, and the conductor may be a metal such as copper or tungsten.
In still another embodiment of the present application, as shown in fig. 3, the magnetic random access memory includes at least one driving interconnection group 50, the driving interconnection group 50 is located in the isolation dielectric layer 30, the driving interconnection group 50 includes a plurality of driving interconnection metal portions 500 spaced apart along the first direction, and the driving interconnection metal portions 500 in at least one of the driving interconnection groups 50 are used for electrically connecting the through holes and the drivers 200 in a one-to-one correspondence.
In order to simplify the result of the magnetic random access memory and simplify the manufacturing process thereof, in an embodiment of the present invention, as shown in fig. 2 and 3, the two driver sets 20 are respectively a first driver set 21 and a second driver set 22, the first driver set 21 is located on the surface of the substrate 10, the second driver set 22 is located on a side of the first driver set 21 away from the substrate 10, the first driver set 21 includes a plurality of first drivers 210 spaced along a first direction, and the second driver set 22 includes a plurality of second drivers 220 spaced along the first direction.
The driver in the present application may be any driver available in the prior art, and may be a diode, or a triode, and those skilled in the art may select an appropriate device as the driver according to the actual situation.
In still another embodiment of the present invention, as shown in fig. 1, the driver 200 is a MOSFET including a source, a gate, and a drain, and as shown in fig. 2 and 3, the magnetic random access memory further includes a plurality of spaced source lines 70, a plurality of spaced word lines 80, and a plurality of spaced bit lines 90, the source lines 70 are electrically connected to the sources in a one-to-one correspondence, the word lines 80 are electrically connected to the driver group 20 in a one-to-one correspondence, one of the word lines 80 is electrically connected to the gate of each of the drivers 200 of the driver group 20, and the bit line 90 is electrically connected to the MTJ bit cell 60 in a one-to-one correspondence.
Note that, in fig. 2 and 3, the source line 70 and the word line 80 are indicated by broken lines because they are not in the current cross section but in a direction perpendicular to the paper surface or the screen or in an outward cross section.
In a specific embodiment, as shown in fig. 2 and 3, a projection of each of the MTJ bits on the surface of the substrate 10 is located inside a projection of the corresponding electrically connected driver 200 on the surface of the substrate 10, and in an embodiment of the present application, each of the MTJ bits 60 is located inside a bottom electrode 61, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode 63, which are sequentially stacked, wherein the free magnetic layer, the insulating layer, and the fixed magnetic layer are shown as a whole and are referred to as an MTJ portion 62.
In order to maintain the electrical uniformity of each memory cell, in one embodiment of the present invention, all the via holes for electrically connecting the MTJ bit cell and the driver have the same resistance value. In the embodiments shown in fig. 2 and 3, all the first vias for electrically connecting the first driver and the MTJ bit cell have the same resistance value and all the second vias for electrically connecting the second driver and the MTJ bit cell have the same resistance value, and in particular, since the first vias are longer, the diameters thereof may be slightly larger in order to have the same resistance value as the second vias.
In order to make the technical solutions and technical effects of the present application more clearly understood by those skilled in the art, the following description will be given with reference to specific embodiments.
Example 1
As shown in fig. 2, the magnetic random access memory includes a substrate 10, two driver groups 20, a plurality of identical MTJ bit cells 60, a plurality of isolation dielectric layers 30, six via groups 40, a plurality of identical source lines 70, two word lines 80, a plurality of identical bit lines 90, and a plurality of other interconnection metal portions 100. The positional relationship of the respective structures is described above with reference to fig. 2.
The two driver groups are a first driver group 21 and a second driver group 22, respectively, the first driver group 21 is located on the surface of the substrate 10, the second driver group 22 is located on a side of the first driver group 21 away from the substrate 10, the first driver group 21 includes a plurality of first drivers 210, and the second driver group 22 includes a plurality of second drivers 220. The first driver 210 and the second driver 220 are the same, and the projection of the first driver 210 on the substrate 10 overlaps the projection of the corresponding second driver 220 on the substrate 10 in a one-to-one correspondence.
Each MTJ bit cell includes a bottom electrode, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode stacked in that order, with the free magnetic layer, the insulating layer, and the fixed magnetic layer shown as a whole in fig. 2 as MTJ portion 62.
The six through hole groups are respectively a first through hole group, a second through hole group, a third through hole group, a fourth through hole group, a fifth through hole group, a sixth through hole group and a seventh through hole group, wherein the first through hole group comprises a plurality of identical first through holes 41, the second through hole group comprises a plurality of identical second through holes 42, the first through holes 41 in the first through hole group correspond to the first drivers 210 in the first driver group one by one and are electrically connected with one MTJ bit element 60 and one first driver 210, and the second through holes 42 in the second through hole group correspond to the second drivers 220 in the second driver group one by one and are electrically connected with one MTJ bit element 60 and one second driver 220. The third through hole group, the fourth through hole group and the fifth through hole group respectively comprise a through hole which is respectively a third through hole 43, a fourth through hole 44 and a fifth through hole 45, the sixth through hole group comprises two identical sixth through holes 46, the first word line 81 is led out from the first word line leading-out electrode 810 by the third through hole 43, the fourth through hole 44, the sixth through hole 46 and metal interconnection parts among the through holes, the second word line 82 is led out from the second word line leading-out electrode 820 by the fifth through hole 45, the sixth through hole 46 and other interconnection metal interconnection parts 100 among the through holes, and the seventh through hole group comprises a plurality of identical seventh through holes 47 which are arranged at intervals.
Each of the via groups 40 includes at least one via, the via holes in at least two of the via groups 40 have different heights, each of the via holes is located in the insulating medium layer 30, at least some of the via groups 40 are in one-to-one correspondence with the driver group 20, and the via hole in one of the via groups 40 corresponding to the driver group 20 is used to electrically connect one MTJ bit cell and one driver 200 in one of the driver groups 20.
The driver 200 is a MOSFET including a source, a gate, and a drain, the source line 70 is electrically connected to the source in a one-to-one correspondence, the two word lines are a first word line 81 and a second word line 82, respectively, the first word line 81 is electrically connected to the gate of each first driver 210 in the first driver group 21, the second word line 82 is electrically connected to the gate of each second driver 220 in the second driver group 22, and the bit line 90 is electrically connected to the MTJ bit cell 60 in a one-to-one correspondence and is electrically connected to the top electrode 63 through the seventh via 47.
Example 2
As shown in fig. 3, the difference from embodiment 1 is that: the projections of the first drivers 210 on the substrate 10 and the projections of the corresponding second drivers 220 on the substrate 10 are coincided in a one-to-one correspondence, that is, all are coincided.
The magnetic random access memory further includes an eighth via group and a driving interconnection group 50, the eighth via group includes a plurality of identical eighth vias 48 disposed at intervals, each of the eighth vias 48 is disposed on a surface of each of the first drivers 210 away from the substrate 10, the driving interconnection group 50 is disposed in the isolation dielectric layer 30, the driving interconnection group 50 includes a plurality of identical driving interconnection metal portions 500 disposed at intervals along the first direction, and the driving interconnection metal portions 500 in the driving interconnection group 50 are configured to electrically connect the first vias 41 and the eighth vias 48 in a one-to-one correspondence manner, so as to electrically connect the bit cells 60 and the first MTJ drivers 210.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
according to the magnetic random access memory, the plurality of stacked driver groups are arranged, and projections of drivers in adjacent driver groups on the surface of the substrate have overlapped parts, so that compared with the prior art, the drivers are arranged in a layered mode in a vertical space, the areal density of the drivers in the vertical direction is improved, the areal density of corresponding MTJ storage bits is correspondingly improved, and finally the storage density of the magnetic random access memory is improved compared with the prior art. Moreover, while the memory density is increased, the processing difficulty of the most challenging MTJ memory bit is not increased, so that the high-density magnetic random access memory has a simple manufacturing process and low manufacturing cost.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A magnetic random access memory, comprising:
a substrate (10);
a plurality of driver groups (20), each driver group (20) is located on the surface of the substrate (10), the plurality of driver groups (20) are sequentially arranged along the direction far away from the substrate (10), each driver group (20) comprises one or more drivers (200) arranged at intervals along the first direction, the center of each driver (200) in one driver group (20) is the same as the distance of the substrate (10), the projection of at least one driver (200) in each driver group (20) on the substrate (10) is overlapped with the projection of at least one driver (200) in the adjacent driver group (20) on the surface of the substrate (10), and the driver group (20) with the largest distance to the substrate (10) in the plurality of driver groups (20) is the top driver group, the first direction is perpendicular to a thickness direction of the substrate (10);
a plurality of MTJ bit cells (60) spaced along the first direction and located on a side of the top driver group away from the substrate (10), one or more of the MTJ bit cells (60) being electrically connected to one or more of the drivers (200);
the projection of each MTJ bit cell (60) on the surface of the substrate (10) is positioned inside the projection of the corresponding electrically connected driver (200) on the surface of the substrate (10), and each MTJ bit cell (60) is positioned to include a bottom electrode, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode, which are sequentially stacked.
2. The magnetic random access memory according to claim 1, wherein each of the driver groups (20) comprises a plurality of identical drivers (200), a projection of the driver (200) in each of the driver groups (20) on the substrate (10) is overlapped with a projection of the driver (200) in an adjacent driver group (20) on the substrate (10) in a one-to-one correspondence, the drivers (200) are electrically connected with the MTJ bit cells (60) in a one-to-one correspondence, and two of the MTJ bit cells (60) electrically connected with two of the drivers (200) overlapped in a one-to-one correspondence are adjacent to each other in a projection on the substrate (10).
3. The magnetic random access memory according to claim 2, wherein the projections of the drivers (200) in each of the driver groups (20) on the substrate (10) coincide with the projections of the drivers (200) in an adjacent driver group (20) on the substrate (10) in a one-to-one correspondence.
4. The MRAM of claim 1, further comprising a plurality of isolation dielectric layers (30), wherein each isolation dielectric layer (30) is disposed on a surface of the substrate (10), and wherein the isolation dielectric layers (30) are sequentially stacked in a direction away from the substrate (10), wherein each driver group (20) is disposed in at least one of the isolation dielectric layers (30), and wherein the MTJ bit cells (60) are disposed in at least one of the isolation dielectric layers (30).
5. The MRAM of claim 4, further comprising a plurality of via groups (40), each via group (40) comprising at least one via, the height of the vias in at least two of the via groups (40) being different, each via being located in the isolation dielectric layer (30), at least some of the via groups (40) corresponding to the driver groups (20) one-to-one, the vias in one of the via groups (40) corresponding to the driver groups (20) being configured to electrically connect one of the MTJ bit cells (60) and one of the drivers (200) in one of the driver groups (20).
6. The MRAM of claim 5, wherein the MRAM comprises at least one driving interconnect group (50), the driving interconnect group (50) is located in the isolation dielectric layer (30), the driving interconnect group (50) comprises a plurality of driving interconnect metal portions (500) spaced along the first direction, and the driving interconnect metal portions (500) in at least one of the driving interconnect groups (50) are configured to electrically connect the via and the driver (200) in a one-to-one correspondence.
7. The magnetic random access memory according to any of claims 1 to 6, wherein there are two driver groups (20), respectively a first driver group (21) and a second driver group (22), the first driver group (21) being located on the surface of the substrate (10), the second driver group (22) being located on a side of the first driver group (21) remote from the substrate (10), the first driver group (21) comprising a plurality of first drivers (210), the second driver group (22) comprising a plurality of second drivers (220).
8. The MRAM of any of claims 1 to 6, wherein the drivers (200) are MOSFETs, the MOSFETs comprising source, gate and drain electrodes, the MRAM further comprising a plurality of spaced apart source lines (70), a plurality of spaced apart word lines (80) and a plurality of spaced apart bit lines (90), the source lines (70) being electrically connected to the source electrodes in a one-to-one correspondence, the word lines (80) being in a one-to-one correspondence with the driver group (20), one of the word lines (80) being electrically connected to the gate of each of the drivers (200) of the driver group (20), and the bit line (90) being electrically connected to the MTJ bit cell (60) in a one-to-one correspondence.
9. The magnetic random access memory according to claim 5, wherein all of the vias for electrically connecting the MTJ bit cell (60) and the driver (200) have equal resistance values.
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| CN201811191866.XA CN111048130B (en) | 2018-10-12 | 2018-10-12 | Magnetic random access memory |
| PCT/CN2019/110672 WO2020073995A1 (en) | 2018-10-12 | 2019-10-11 | Magnetic random access memory |
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| CN201811191866.XA CN111048130B (en) | 2018-10-12 | 2018-10-12 | Magnetic random access memory |
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| TW594727B (en) * | 2002-02-22 | 2004-06-21 | Toshiba Corp | Magnetic random access memory |
| US6940748B2 (en) * | 2002-05-16 | 2005-09-06 | Micron Technology, Inc. | Stacked 1T-nMTJ MRAM structure |
| JP2011023476A (en) * | 2009-07-14 | 2011-02-03 | Toshiba Corp | Magnetic memory device |
| WO2013095540A1 (en) * | 2011-12-22 | 2013-06-27 | Intel Corporation | Memory with elements having two stacked magnetic tunneling junction (mtj) devices |
| US10403627B2 (en) * | 2016-10-11 | 2019-09-03 | Imec Vzw | Memory device for a dynamic random access memory |
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