CN111047500A - Test method of ultra-long graphic assembly line - Google Patents
Test method of ultra-long graphic assembly line Download PDFInfo
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- CN111047500A CN111047500A CN201911125800.5A CN201911125800A CN111047500A CN 111047500 A CN111047500 A CN 111047500A CN 201911125800 A CN201911125800 A CN 201911125800A CN 111047500 A CN111047500 A CN 111047500A
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- 238000010998 test method Methods 0.000 title description 5
- 238000012360 testing method Methods 0.000 claims abstract description 52
- 238000012545 processing Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 claims abstract description 13
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 239000000284 extract Substances 0.000 abstract 1
- 230000011218 segmentation Effects 0.000 abstract 1
- 238000013461 design Methods 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
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Abstract
The invention belongs to the field of computer graphics, and particularly relates to a super-long graphic assembly line testing method. The method comprises the steps of (1) analyzing the image processing function to form an image pipeline modular diagram, (2) dividing an image pipeline aiming at different tasks, (3) segmenting a task processing pipeline, (4) testing in a segmented pipeline segment, (5) testing between the segmented pipeline segments, and (6) testing the whole pipeline. The method extracts the main branches of the ultra-long assembly line, carries out assembly line segmentation, and synchronously verifies the data flow and the control flow between the segment assembly line and the segments, thereby completing the test of the ultra-long pattern assembly line.
Description
Technical Field
The invention belongs to the field of computer graphics, and particularly relates to a super-long graphic assembly line testing method.
Background
The graphic pipeline is an ultra-long pipeline with multiple pipeline stages and multiple processing branches, and is complex in test and high in redundancy. The qualification of the graphics pipeline is related to the design and implementation of the graphics processor, and a complete set of test method for the ultra-long graphics pipeline is not available in the currently disclosed research.
Disclosure of Invention
The purpose of the invention is:
the invention mainly provides a test method of an ultra-long graphic assembly line, which is used for testing the qualification of the ultra-long graphic assembly line.
The solution of the invention is:
the invention provides a method for testing an ultra-long graphic assembly line, which comprises the following steps:
(1) analyzing graphics processing functions to form a graphics pipeline block diagram
(2) Dividing a graphic pipeline aiming at different tasks,
(3) A task processing pipeline is segmented,
(4) The test in the segment flow line segment,
(5) The test between the segments of the segment flow line,
(6) And (6) carrying out overall test on the assembly line.
Further, the step (1) comprises: the graphics pipeline processing path includes all possible branch paths to form a graphics pipeline block diagram.
Further, the step (2) comprises: partitioning the pipeline from the data source and covering all pipeline branches according to the graph pipeline block diagram formed in step (1).
Further, the step (3) comprises: and (3) according to the task pipeline divided in the step (2), taking the section without the branch nodes as a section, wherein one task pipeline is composed of a plurality of sections, and one section of the task pipeline can be multiplexed by a plurality of branch pipelines.
Further, the step (4) comprises: and (4) designing an intra-segment test scheme according to the segmented assembly line in the step (3), wherein the test scheme comprises the correctness of intra-segment functions and the synchronization of the intra-segment functions.
Further, the step (5) comprises: and (4) according to the subsection assembly line in the step (3), carrying out synchronous test on command streams, data streams and control streams among the sections.
Further, the step (6) comprises: and (5) drawing in a combined manner according to the test scenes of the internal test of the pipeline in the step (4) and the test between the pipelines in the step (5) to finish the test of the super-long graphic pipeline.
The invention has the beneficial effects that:
by reasonable planning, the test method of the ultra-long graphic assembly line is provided, the test efficiency is effectively improved, repeated tests are reduced, the correctness and comprehensiveness of the tests are ensured, and the design and implementation of the graphic processor are guaranteed.
Drawings
FIG. 1 is a block diagram of a method of the present invention;
FIG. 2 is a block diagram of a graphics pipeline in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, a method for testing an ultra-long graphics pipeline is characterized in that the method comprises (1) analyzing graphics processing functions to form a graphics pipeline module diagram, (2) dividing graphics pipelines aiming at different tasks, (3) segmenting the task processing pipeline, (4) testing in a segmented pipeline segment, (5) testing between the segmented pipeline segments, and (6) testing the whole pipeline.
(1) Analyzing the graphics processing function to form a graphics pipeline block diagram, wherein the graphics pipeline block diagram is formed by counting graphics data sources and graphics pipeline processing paths, wherein the graphics pipeline processing paths include all possible branch paths, as shown in FIG. 2;
(2) dividing a graphics pipeline aiming at different tasks, wherein according to a graphics pipeline module diagram formed in the step (1), pipelines are divided from different data sources, and all pipeline branches are covered, such as ① graphics data generation, ② display list analysis and ③ buffer data transmission three different data sources shown in fig. 2;
(3) a task processing pipeline segment, wherein the task pipeline segment divided according to (2) takes the section without branch nodes as a segment, one task pipeline is composed of a plurality of segments, and one segment of the task pipeline may be multiplexed by a plurality of branch pipelines, for example, one task pipeline of the data source 1 shown in fig. 2 may be divided into C, P, R three segments;
(4) the subsection pipeline in-line test is characterized in that an in-line test scheme is designed according to the subsection pipeline in the step (3), wherein the in-line test scheme comprises correctness of in-line functions, synchronization of in-line functions and the like;
(5) the subsection pipeline inter-section test is characterized in that synchronous test is carried out on command streams, data streams and control streams among sections according to the subsection pipeline in the step (3);
(6) the whole assembly line test is characterized in that drawing is carried out in a combined mode according to the test scenes of the (4) section assembly line internal test and the (5) section assembly line test, and the test of the ultra-long graphic assembly line is completed.
Claims (7)
1. A method for testing an ultra-long graphics pipeline, the method comprising:
(1) analyzing graphics processing functions to form a graphics pipeline block diagram
(2) Dividing a graphic pipeline aiming at different tasks,
(3) A task processing pipeline is segmented,
(4) The test in the segment flow line segment,
(5) The test between the segments of the segment flow line,
(6) And (6) carrying out overall test on the assembly line.
2. The method for testing the pipeline of very long graphics according to claim 1, wherein the step (1) comprises: the graphics pipeline processing path includes all possible branch paths to form a graphics pipeline block diagram.
3. The method for testing an ultralong graphics pipeline according to claim 1, wherein the step (2) comprises: partitioning the pipeline from the data source and covering all pipeline branches according to the graph pipeline block diagram formed in step (1).
4. The method for testing the pipeline of very long graphics according to claim 1, wherein the step (3) comprises: and (3) according to the task pipeline divided in the step (2), taking the section without the branch nodes as a section, wherein one task pipeline is composed of a plurality of sections, and one section of the task pipeline can be multiplexed by a plurality of branch pipelines.
5. The method for testing the pipeline of very long graphics according to claim 1, wherein the step (4) comprises: and (4) designing an intra-segment test scheme according to the segmented assembly line in the step (3), wherein the test scheme comprises the correctness of intra-segment functions and the synchronization of the intra-segment functions.
6. The method for testing an ultralong graphics pipeline according to claim 1, wherein the step (5) comprises: and (4) according to the subsection assembly line in the step (3), carrying out synchronous test on command streams, data streams and control streams among the sections.
7. The method of claim 1, wherein the step (6) comprises: and (5) drawing in a combined manner according to the test scenes of the internal test of the pipeline in the step (4) and the test between the pipelines in the step (5) to finish the test of the super-long graphic pipeline.
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| CN201911125800.5A CN111047500A (en) | 2019-11-18 | 2019-11-18 | Test method of ultra-long graphic assembly line |
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Citations (6)
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|---|---|---|---|---|
| CN102789521A (en) * | 2012-06-27 | 2012-11-21 | 北京大学深圳研究生院 | Method and system for verifying integrated circuit pipeline design, and model implementation method of integrated circuit pipeline |
| US20160239939A1 (en) * | 2015-02-18 | 2016-08-18 | Arm Limited | Graphics processing systems |
| CN106326047A (en) * | 2015-07-02 | 2017-01-11 | 超威半导体(上海)有限公司 | Method for predicting GPU performance and corresponding computer system |
| CN108021487A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of GPU graphics process performance monitoring and analysis method |
| US20180286101A1 (en) * | 2017-04-01 | 2018-10-04 | Intel Corporation | Graphics apparatus including a parallelized macro-pipeline |
| CN110160455A (en) * | 2019-06-24 | 2019-08-23 | 易思维（杭州）科技有限公司 | Clearance surface difference detection system |
-
2019
- 2019-11-18 CN CN201911125800.5A patent/CN111047500A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789521A (en) * | 2012-06-27 | 2012-11-21 | 北京大学深圳研究生院 | Method and system for verifying integrated circuit pipeline design, and model implementation method of integrated circuit pipeline |
| US20160239939A1 (en) * | 2015-02-18 | 2016-08-18 | Arm Limited | Graphics processing systems |
| CN106326047A (en) * | 2015-07-02 | 2017-01-11 | 超威半导体(上海)有限公司 | Method for predicting GPU performance and corresponding computer system |
| US20180286101A1 (en) * | 2017-04-01 | 2018-10-04 | Intel Corporation | Graphics apparatus including a parallelized macro-pipeline |
| CN108021487A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of GPU graphics process performance monitoring and analysis method |
| CN110160455A (en) * | 2019-06-24 | 2019-08-23 | 易思维（杭州）科技有限公司 | Clearance surface difference detection system |
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Application publication date: 20200421 |
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