CN111046395A - EC updates firmware protection circuit and electronic equipment - Google Patents
EC updates firmware protection circuit and electronic equipment Download PDFInfo
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- CN111046395A CN111046395A CN201911291619.1A CN201911291619A CN111046395A CN 111046395 A CN111046395 A CN 111046395A CN 201911291619 A CN201911291619 A CN 201911291619A CN 111046395 A CN111046395 A CN 111046395A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Abstract
The invention discloses an EC (embedded control) updating firmware protection circuit, which relates to the technical field of electronic circuits and comprises a system on chip, a power supply chip, a system stable output circuit, a reset circuit and a first enabling circuit; when the system-on-chip stably runs, the output end of the system-on-chip sends a system stabilization signal to the detection input end through the system stabilization output circuit; when the EC needs to update the firmware, the EC sends a non-shutdown signal to the system on chip through a second output end; when the EC finishes updating the firmware, the EC sends a reset signal to the system stable output circuit through the first output end via the reset circuit; when the EC is forcibly turned off in the firmware updating process, the EC sends a first enabling signal to an enabling end of the power supply chip through a third output end of the EC via a first enabling circuit. The embodiment of the invention also discloses electronic equipment comprising the EC updating firmware protection circuit. The embodiment of the invention ensures the stability of the system when the EC is executed to update the firmware.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to an EC (embedded control) update firmware protection circuit and electronic equipment.
Background
EC (embedded Controller) is widely used in notebook computers, tablet computers and various industrial personal computers, and is also called KBC (Keyboard Controller) in notebook computers and tablet computers. The EC is high in the system. The EC controls the timing of most important signals during system start-up. After the computer is started, the EC controls equipment such as a keyboard, an indicator light, a fan, a touch panel and the like. In addition, the EC controls the standby, sleep, etc. states of the system.
During use, the firmware of the EC is often updated to solve problems or to add new functions. If the EC is suddenly powered off due to system problems in the firmware updating process, the EC firmware can be damaged, so that the EC loses functions, the functions of the system are influenced, and even the system cannot be started.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an EC update firmware protection circuit and an electronic device, which can ensure the stability of a system when EC update firmware is executed.
In a first aspect, an embodiment of the present invention provides an EC update firmware protection circuit, which includes a system on chip, a power chip, a system stable output circuit, a reset circuit, and a first enable circuit; wherein:
the EC has a detection input, a first output, a second output, and a third output;
when the system on chip stably runs, the output end of the system on chip sends a system stable signal to the detection input end through a system stable output circuit;
when the EC needs to update the firmware, the EC sends a non-shutdown signal to the system on chip through a second output end so that the detection input end continues to receive a system stabilization signal;
when the EC finishes updating the firmware, the EC sends a reset signal to the system on chip through the second output end, or the EC sends a reset signal to the system stable output circuit through the first output end via the reset circuit so as to reset the system stable output circuit;
when the EC is forcibly turned off in the firmware updating process, the EC sends a first enabling signal to an enabling end of the power supply chip through a third output end of the EC via a first enabling circuit so as to enable the power supply chip to work.
In a preferred embodiment, the system stabilization output circuit comprises a first electronic switch and a resistor R1, wherein a control terminal of the first electronic switch is connected to an output terminal of the system on chip, and an input terminal of the first electronic switch is connected to an output terminal of the power supply chip through a resistor R1; the output end of the first electronic switch is grounded, and the detection input end is connected between the resistor R1 and the input end of the first electronic switch;
when the system on chip stably runs, the output end of the system on chip controls the first electronic switch to be conducted, so that the detection input end receives a low level signal.
In a preferred embodiment, the first electronic switch is an NMOS transistor Q1, and the gate, the drain, and the source of the NMOS transistor Q1 correspond to the control terminal, the input terminal, and the output terminal of the first electronic switch, respectively;
when the system on chip operates stably, the output end of the system on chip outputs high level to control the conduction of the NMOS pipe Q1, so that the detection input end receives low level signals.
In a preferred embodiment, the reset circuit comprises an NMOS transistor Q2, the gate of the NMOS transistor Q2 is connected to the first output terminal, the source of the NMOS transistor Q2 is grounded, and the drain of the NMOS transistor Q2 is connected between the gate of the NMOS transistor Q1 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a high level through the first output end, the NMOS tube Q2 is conducted, so that the output signal of the output end of the system on chip is pulled down, the NMOS tube Q1 is cut off, and the detection input end receives a high level signal.
In a preferred embodiment, the reset circuit comprises a PMOS transistor Q3, the gate of the PMOS transistor Q3 is connected to the first output terminal, the drain of the PMOS transistor Q3 is grounded, and the source of the PMOS transistor Q3 is connected between the gate of the NMOS transistor Q1 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a low level through the first output end, the PMOS tube Q3 is conducted, so that the output signal of the output end of the system on chip is pulled down, the NMOS tube Q1 is cut off, and the detection input end receives a high level signal.
In a preferred embodiment, the first electronic switch is a PMOS transistor Q4, and the gate, the source and the drain of the PMOS transistor Q4 correspond to the control terminal, the input terminal and the output terminal of the first electronic switch, respectively;
when the system on chip operates stably, the output end of the system on chip outputs low level to control the conduction of the PMOS pipe Q4, so that the detection input end receives a low level signal.
In a preferred embodiment, the reset circuit includes an NMOS transistor Q5, the gate of the NMOS transistor Q5 is connected to the first output terminal, the drain of the NMOS transistor Q5 is connected to the output terminal of the power chip, and the source of the NMOS transistor Q5 is connected between the gate of the PMOS transistor Q4 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a high level through the first output end, the NMOS tube Q5 is conducted, so that the output signal of the output end of the system on chip is raised, the PMOS tube Q4 is cut off, and the detection input end receives a high level signal.
In a preferred embodiment, the reset circuit includes a PMOS transistor Q6, the gate of the PMOS transistor Q6 is connected to the first output terminal, the source of the PMOS transistor Q6 is connected to the output terminal of the power chip, and the drain of the PMOS transistor Q6 is connected between the gate of the PMOS transistor Q4 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a low level through the first output end, the PMOS transistor Q6 is conducted, so that the output signal of the output end of the system on chip is raised, the PMOS transistor Q4 is cut off, and the detection input end receives a high level signal.
In a preferred embodiment, the first enabling circuit comprises a diode D1 and a capacitor C1, the anode of the diode D1 is connected to the third output terminal, the cathode of the diode D1 is connected to the enabling terminal of the power chip, one end of the capacitor C1 is connected between the cathode of the diode D1 and the enabling terminal of the power chip, and the other end of the capacitor C1 is grounded;
when the EC is forcibly turned off in the firmware updating process, the EC outputs a high level through a third output end of the EC, and sends a first enabling signal of the high level to the power supply chip through a first enabling circuit so as to enable the power supply chip to work;
the EC update firmware protection circuit further comprises a second enable circuit comprising a diode D2, an anode of the diode D2 receiving a second enable signal, a cathode of the diode D2 connected between a cathode of the diode D1 and one end of a capacitor C1; the second enable signal is generated by the system-on-chip or by a power-on key signal.
In a second aspect, an embodiment of the present invention provides an electronic device, which includes the EC update firmware protection circuit according to the first aspect of the present invention.
Compared with the prior art, the embodiment of the invention ensures the stability of the system when the EC updates the firmware through the interaction of the system on the chip and the EC, and the mode is convenient to realize and has strong interference resistance.
Drawings
FIG. 1 is a schematic block diagram of an EC update firmware protection circuit of embodiment 1;
FIG. 2 is a schematic block diagram of an EC update firmware protection circuit of embodiment 2;
FIG. 3 is a schematic block diagram of an EC update firmware protection circuit of embodiment 3;
fig. 4 is a schematic block diagram of an EC update firmware protection circuit of embodiment 4.
In the figure: 10. EC; 20. a system on a chip; 30. and a power supply chip.
Detailed description of the preferred embodiments
The embodiments of the present invention are further described below with reference to the drawings and the specific embodiments, and it should be noted that, in the premise of no conflict, any combination between the embodiments or technical features described below may form a new embodiment. Except as specifically noted, the materials and equipment used in this example are commercially available.
Example 1:
referring to fig. 1, an EC update firmware protection circuit includes a system on chip (SoC)20, a power chip 30, a system stable output circuit, a reset circuit, and a first enable circuit.
EC 10 has a detection input, a first output, a second output, and a third output;
when the system-on-chip stably runs, the output end of the system-on-chip sends a system stabilization signal to the detection input end through the system stabilization output circuit; and when the EC receives the system stabilization signal, the starting is considered to be completed and the system is stable.
When the EC needs to update the firmware, the EC sends a non-shutdown signal to the system on chip through the second output end so that the detection input end continuously receives a system stabilization signal; and if the EC continuously receives the system stable signal, the system is determined to be stable, and the updating work of the firmware can be started.
In the updating process, an EC can continuously send a non-shutdown signal to the system on chip in a preset period, and simultaneously detects that an input end continuously receives a system stable signal; of course, before the system on chip receives the reset signal, the system on chip may continuously send the system stabilization signal to the detection input terminal through the system stabilization output circuit until the EC completes the firmware update, and the EC transmits the reset signal to the system on chip through the second output terminal, or the EC directly adjusts the signal output by the output terminal of the system on chip through the first output terminal without passing through the system on chip, and the adjustment mode is pull-down or lift-up).
In a preferred embodiment of the present invention, when the EC completes firmware update, the EC sends a reset signal to the system stabilization output circuit through the first output terminal via the reset circuit to reset the system stabilization output circuit, the reset system stabilization output circuit is a signal that is output by the output terminal of the system on chip, after the firmware update is completed, forced shutdown occurs, and the EC does not perform corresponding operation on the first enable circuit.
And when the EC updates the firmware and is forcibly turned off, the EC sends a first enabling signal to an enabling end of the power chip through a third output end of the EC via the first enabling circuit so as to enable the power chip to work for a short time.
The system stability of the EC in the firmware updating process is guaranteed through the interaction of the EC, the system on the chip and the power supply chip, namely the firmware updating process of the EC cannot be interrupted, and if forced shutdown occurs, the function of the EC cannot be influenced.
The system stable output circuit comprises a first electronic switch and a resistor R1, wherein the control end of the first electronic switch is connected to the output end of the system on chip, and the input end of the first electronic switch is connected to the output end of the power supply chip through a resistor R1; the output end of the first electronic switch is grounded, and the detection input end is connected between the resistor R1 and the input end of the first electronic switch; when the system on chip stably runs, the output end of the system on chip controls the first electronic switch to be conducted, so that the detection input end receives a low level signal.
In this embodiment 1, the first electronic switch employs an NMOS transistor Q1, wherein a gate, a drain, and a source of the NMOS transistor Q1 correspond to a control terminal, an input terminal, and an output terminal of the first electronic switch, respectively; when the system on chip stably operates, the output end of the system on chip outputs a high level (SOC _ PS _ HOLD is high level) to control the NMOS transistor Q1 to be turned on, so that the detection input end receives a low level signal (EC _ PS _ HOLD _ N is low level). In addition, a pull-down resistor R2 is further arranged between the gate of the NMOS transistor Q1 and the output end of the system on chip, one end of the pull-down resistor R2 is connected between the gate of the NMOS transistor Q1 and the output end of the system on chip, and the other end of the pull-down resistor R3526 is grounded.
The reset circuit comprises an NMOS tube Q2, the grid electrode of the NMOS tube Q2 is connected to the first output end, the source electrode of the NMOS tube Q2 is grounded, and the drain electrode of the NMOS tube Q2 is connected between the grid electrode of the NMOS tube Q1 and the output end of the system on chip through a resistor R3. In addition, a pull-down resistor R2 is further disposed between the gate of the NMOS transistor Q2 and the first output terminal, one end of the pull-down resistor R2 is connected between the gate of the NMOS transistor Q2 and the first output terminal, and the other end is grounded. When the EC finishes updating the firmware, the EC outputs a high level (EC _ RST _ PS _ HOLD) through the first output terminal, the NMOS transistor Q2 is turned on, so as to pull down the output signal of the output terminal of the system on chip (system reset), so that the NMOS transistor Q1 is turned off, and the detection input terminal receives a high level signal.
The first enabling circuit comprises a diode D1 and a capacitor C1, wherein the anode of the diode D1 is connected to the third output end, the cathode of the diode D1 is connected with the enabling end of the power supply chip, one end of the capacitor C1 is connected between the cathode of the diode D1 and the enabling end of the power supply chip, and the other end of the capacitor C1 is grounded;
when the EC is forced to be shut down in the firmware updating process, the EC outputs a high level through the third output end of the EC, a first enabling signal of the high level is sent to the power supply chip through the first enabling circuit so as to enable the power supply chip to work, and the cooperation of the diode D1 and the capacitor C1 can ensure that the first enabling signal continuously keeps the high level state for a relatively long time, so that enough time is provided for the EC to restore the original firmware.
In addition, the EC also has a conventional power chip enable signal, which is denoted as a second enable signal, and in the EC update firmware protection circuit, the EC further includes a second enable circuit, the second enable circuit includes a diode D2, an anode of the diode D2 receives the second enable signal, and a cathode of the diode D2 is connected between the cathode of the diode D1 and one end of the capacitor C1; the second enable signal is generated by the system on chip or by the power-on key signal, and obviously, when the power-off is forced, the second enable signal disappears, and the power chip needs to be maintained to temporarily work by the first enable signal.
Example 2:
embodiment 2 is an improvement over embodiment 1, and in embodiment 2, the reset circuit uses a PMOS transistor Q3, and the rest is basically the same as embodiment 1. The grid electrode of the PMOS tube Q3 is connected to the first output end, the drain electrode of the PMOS tube Q3 is grounded, and the source electrode of the PMOS tube Q3 is connected between the grid electrode of the NMOS tube Q1 and the output end of the system-on-chip 20 through a resistor R3; when the firmware updating of the EC 10 is completed, the EC outputs a low level through the first output terminal, the PMOS transistor Q3 is turned on, and thus the output signal of the output terminal of the system on chip is pulled down (system reset), so that the NMOS transistor Q1 is turned off, and the detection input terminal receives a high level signal.
Example 3
Embodiment 3 is an improvement on embodiment 1, in which the first electronic switch employs a PMOS transistor Q4, and the gate, source and drain of the PMOS transistor Q4 correspond to the control terminal, input terminal and output terminal of the first electronic switch, respectively; when the system-on-chip 20 stably operates, the output end of the system-on-chip outputs a low level to control the conduction of the PMOS transistor Q4, so that the detection input end receives a low level signal.
The reset circuit adopts an NMOS tube Q5, the grid electrode of the NMOS tube Q5 is connected to the first output end, the drain electrode of the NMOS tube Q5 is connected to the output end of the power supply chip 30, and the source electrode of the NMOS tube Q5 is connected between the grid electrode of the PMOS tube Q4 and the output end of the system on chip through a resistor R3; when the firmware updating of the EC 10 is completed, the EC outputs a high level through the first output terminal, and the NMOS transistor Q5 is turned on, so as to raise the output signal of the output terminal of the system on chip (system reset), so that the PMOS transistor Q4 is turned off, and the detection input terminal receives a high level signal.
Example 4:
embodiment 4 is an improvement on embodiment 3, in which a reset circuit uses a PMOS transistor Q6, and the rest is substantially the same as embodiment 3. The gate of the PMOS transistor Q6 is connected to the first output terminal, the source of the PMOS transistor Q6 is connected to the output terminal of the power chip 30, and the drain of the PMOS transistor Q6 is connected between the gate of the PMOS transistor Q4 and the output terminal of the system-on-chip 20 through the resistor R3; when the firmware updating of the EC 10 is completed, the EC outputs a low level through the first output terminal, and the PMOS transistor Q6 is turned on, so as to raise the output signal of the output terminal of the system on chip (system reset), so that the PMOS transistor Q4 is turned off, and the detection input terminal receives a high level signal.
Example 5:
embodiment 5 discloses an electronic device, which may be a notebook computer, a tablet computer, an industrial control device, or the like, and which has an EC and a system on a chip; in addition to the EC update firmware protection circuit in any of embodiments 1 to 4, the electronic device further includes necessary components, such as a PCB board on which components of the EC update firmware protection circuit are mounted and a housing on which the PCB board, an output interface, an indicator light, a display screen, and the like are mounted, and of course, other components, such as a heat sink, and the like, may be included as needed.
The above embodiments are only preferred embodiments of the present invention, and the scope of the embodiments of the present invention should not be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the embodiments of the present invention are within the scope of the claims of the embodiments of the present invention.
Claims (10)
1. An EC updating firmware protection circuit is characterized by comprising a system on chip, a power supply chip, a system stable output circuit, a reset circuit and a first enabling circuit; wherein:
the EC has a detection input, a first output, a second output, and a third output;
when the system on chip stably runs, the output end of the system on chip sends a system stable signal to the detection input end through a system stable output circuit;
when the EC needs to update the firmware, the EC sends a non-shutdown signal to the system on chip through a second output end so that the detection input end continues to receive a system stabilization signal;
when the EC finishes updating the firmware, the EC sends a reset signal to the system on chip through the second output end, or the EC sends a reset signal to the system stable output circuit through the first output end via the reset circuit so as to reset the system stable output circuit;
when the EC is forcibly turned off in the firmware updating process, the EC sends a first enabling signal to an enabling end of the power supply chip through a third output end of the EC via a first enabling circuit so as to enable the power supply chip to work.
2. The EC-update-firmware-protection circuit of claim 1, wherein the system-stabilization-output circuit comprises a first electronic switch, a resistor R1, a control terminal of the first electronic switch being connected to an output terminal of the system-on-chip, an input terminal of the first electronic switch being connected to an output terminal of the power chip through a resistor R1; the output end of the first electronic switch is grounded, and the detection input end is connected between the resistor R1 and the input end of the first electronic switch;
when the system on chip stably runs, the output end of the system on chip controls the first electronic switch to be conducted, so that the detection input end receives a low level signal.
3. The EC-update-firmware-protection circuit of claim 2, wherein the first electronic switch is an NMOS transistor Q1, and the gate, drain, and source of the NMOS transistor Q1 correspond to the control terminal, the input terminal, and the output terminal of the first electronic switch, respectively;
when the system on chip operates stably, the output end of the system on chip outputs high level to control the conduction of the NMOS pipe Q1, so that the detection input end receives low level signals.
4. The EC update firmware protection circuit of claim 3, wherein the reset circuit comprises an NMOS transistor Q2, the gate of the NMOS transistor Q2 is connected to the first output terminal, the source of the NMOS transistor Q2 is grounded, the drain of the NMOS transistor Q2 is connected between the gate of the NMOS transistor Q1 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a high level through the first output end, the NMOS tube Q2 is conducted, so that the output signal of the output end of the system on chip is pulled down, the NMOS tube Q1 is cut off, and the detection input end receives a high level signal.
5. The EC update firmware protection circuit of claim 3, wherein the reset circuit comprises a PMOS transistor Q3, the gate of the PMOS transistor Q3 is connected to the first output terminal, the drain of the PMOS transistor Q3 is grounded, the source of the PMOS transistor Q3 is connected between the gate of the NMOS transistor Q1 and the output terminal of the system-on-chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a low level through the first output end, the PMOS tube Q3 is conducted, so that the output signal of the output end of the system on chip is pulled down, the NMOS tube Q1 is cut off, and the detection input end receives a high level signal.
6. The EC update firmware protection circuit of claim 2, wherein the first electronic switch is a PMOS transistor Q4, the gate, source and drain of the PMOS transistor Q4 corresponding to the control terminal, input terminal and output terminal of the first electronic switch, respectively;
when the system on chip operates stably, the output end of the system on chip outputs low level to control the conduction of the PMOS pipe Q4, so that the detection input end receives a low level signal.
7. The EC update firmware protection circuit of claim 6, wherein the reset circuit comprises an NMOS transistor Q5, the gate of the NMOS transistor Q5 is connected to the first output terminal, the drain of the NMOS transistor Q5 is connected to the output terminal of the power chip, the source of the NMOS transistor Q5 is connected between the gate of the PMOS transistor Q4 and the output terminal of the system on chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a high level through the first output end, the NMOS tube Q5 is conducted, so that the output signal of the output end of the system on chip is raised, the PMOS tube Q4 is cut off, and the detection input end receives a high level signal.
8. The EC update firmware protection circuit of claim 7, wherein the reset circuit comprises a PMOS transistor Q6, the gate of the PMOS transistor Q6 is connected to the first output terminal, the source of the PMOS transistor Q6 is connected to the output terminal of the power chip, the drain of the PMOS transistor Q6 is connected between the gate of the PMOS transistor Q4 and the output terminal of the system-on-chip through a resistor R3;
when the EC finishes updating the firmware, the EC outputs a low level through the first output end, the PMOS transistor Q6 is conducted, so that the output signal of the output end of the system on chip is raised, the PMOS transistor Q4 is cut off, and the detection input end receives a high level signal.
9. The EC-update firmware protection circuit of any one of claims 1-8, wherein the first enabling circuit comprises a diode D1 and a capacitor C1, an anode of the diode D1 is connected to the third output terminal, a cathode of the diode D1 is connected to an enabling terminal of the power chip, one end of the capacitor C1 is connected between a cathode of the diode D1 and the enabling terminal of the power chip, and the other end of the capacitor C1 is grounded;
when the EC is forcibly turned off in the firmware updating process, the EC outputs a high level through a third output end of the EC, and sends a first enabling signal of the high level to the power supply chip through a first enabling circuit so as to enable the power supply chip to work;
the EC update firmware protection circuit further comprises a second enable circuit comprising a diode D2, an anode of the diode D2 receiving a second enable signal, a cathode of the diode D2 connected between a cathode of the diode D1 and one end of a capacitor C1; the second enable signal is generated by the system-on-chip or by a power-on key signal.
10. An electronic device comprising the EC update firmware protection circuit of any of claims 1-9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116774638A (en) * | 2023-08-21 | 2023-09-19 | 北京领创医谷科技发展有限责任公司 | Switching circuit applied to external energy controller |
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| CN108762789A (en) * | 2018-06-01 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of server node firmware update and relevant apparatus |
| CN109597701A (en) * | 2018-10-23 | 2019-04-09 | 上海移远通信技术股份有限公司 | A kind of device that communication module is restarted automatically |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108762789A (en) * | 2018-06-01 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of server node firmware update and relevant apparatus |
| CN109597701A (en) * | 2018-10-23 | 2019-04-09 | 上海移远通信技术股份有限公司 | A kind of device that communication module is restarted automatically |
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| CN116774638A (en) * | 2023-08-21 | 2023-09-19 | 北京领创医谷科技发展有限责任公司 | Switching circuit applied to external energy controller |
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