TWI521336B - Display device - Google Patents

Description

Display device

The present invention relates to a display device used in connection with an external device such as a computer device.

A display device such as a liquid crystal display that is connected to an external device such as a computer device has a power saving function based on a display power management signal (DPMS) standard. The DPMS specification refers to the specifications regarding the power management of the display device. The DPMS specification is based on the Video Electronics Standards Association (VESA), a specification standardization group for image devices related to computer equipment.

The display device corresponding to the DPMS standard is switched from the normal mode to the energy saving mode (hereinafter, also referred to as "energy saving mode") or the self-saving mode is switched to the normal mode in response to the state of the connected external device. The switching operation of the normal mode and the energy saving mode is controlled based on the presence or absence of a video signal (hereinafter also referred to as a "video input signal") input from the external device to the display device. In the following description, the state of the display device operating in the energy saving mode is referred to as "standby state".

Power consumption in standby state (hereinafter, also referred to as "standby Most of the goals of electricity" apply to the International Energy Star program specifications. According to the "Monitor Standard Ver 5.1 Revision (November 14, 2011)", the International Energy Star Program specifications are set to "No more than 2.0W in sleep mode and no more than 1.0W in shutdown mode". This requirement is considered to be more stringent in the future, in other words, switching to a smaller power consumption target value. The return from the shutdown mode of the display device to the normal mode is performed by the operation of a mechanical switch.

In addition, based on environmental care, it has improved the energy-saving mode for home electrical products such as TV receivers and video equipment, as well as information system machines such as office automation (OA) machines, computer devices, and liquid crystal displays. The requirements for standby power. Specifically, it is required to suppress standby power to 0 watts (W) as much as possible.

A technique for suppressing power consumption of a display device has been disclosed in, for example, Patent Document 1. Patent Document 1 discloses a display device that is connected to a computer device and that can operate in a power saving mode that suppresses a power consumption operation in a normal mode. The power saving mode is equivalent to the aforementioned energy saving mode.

The display device disclosed in Patent Document 1 detects the brightness of the environment provided by the display device by the illuminance sensor and inputs it to the control unit. The control unit determines whether to switch the display device to the power saving mode in response to the information input by the self-illumination sensor. The control unit stops the operation of the backlight driving signal generating unit in the power saving mode, and also stops the supply of power and display signals to the liquid crystal display panel.

Previous technical literature: Patent literature:

Patent Document 1: Japanese Patent No. 4819353

As described above, the display device such as a liquid crystal display connected to an external device monitors the presence or absence of a video input signal from the external device, and switches from the normal mode to the energy saving mode when there is no video input signal.

In order to revert to the normal mode, even in the energy saving mode, it is necessary to monitor whether or not there is a video input signal and control it according to the monitoring result. Since power is required to monitor the presence or absence of a video input signal, it is difficult to suppress the standby power in the power saving mode to 0W.

Further, when the display device disclosed in the above Patent Document 1 is returned to the normal mode in the power saving mode corresponding to the energy saving mode, the user must perform a predetermined operation by pressing a predetermined button or the like. Therefore, there is a problem that the operation is complicated for the user.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device which suppresses power consumption of a power saving mode to a small extent as much as possible, and can also easily return to an ordinary mode by introspecting an energy mode.

The display device of the present invention is connected to an external device, and The first signal detecting means is configured to detect whether or not the input is capable of the first signal detecting means when the energy saving mode is operated in a normal mode. a virtual input signal for inputting a video input signal from the external device; a second signal detecting means for detecting whether the video input signal is input from the external device; and a power mode switching control means according to the foregoing The normal signal and the energy saving mode are switched between the detection result of the second signal detecting means; and the display signal processing means is configured to display the video input signal input from the external device to display the video input signal. And an electronic switch control means for switching to a supply state in which power is supplied to the second signal detecting means, the power mode switching control means, and the display signal processing means; and stopping supply of the supply of the power is stopped State, the aforementioned power mode switching control When the segment is operated in the normal mode, if the second signal detecting means detects that the video input signal is not input, the mode is switched from the normal mode to the energy saving mode, and when the energy saving mode is operated, When the second signal detecting means detects that the video input signal has been input, the second signal detecting means switches from the energy saving mode to the normal mode, and when the second signal detecting means detects that the video input signal is not input, the energy saving is maintained. Mode, the aforementioned electricity When the sub-switch control means switches from the normal mode to the energy-saving mode by the power mode switching control means, the slave switching control means switches from the supply state to the supply stop state, and when operating in the energy saving mode, When the first signal detecting means detects that the virtual input signal has been input, the first signal detecting means switches from the supply stop state to the supply state.

According to the display device of the present invention, when the power mode switching control means switches from the normal mode to the energy saving mode, the electronic switch control means switches from the supply state to the supply stop state, and stops the second signal detecting means and the power. The mode switching control means and the supply of power for displaying the signal processing means. When the first signal detecting means detects that the virtual input signal has been input when operating in the energy saving mode, the electronic switch control means switches from the supply stop state to the supply state, and supplies the electric power to the second signal detecting means and the electric power. The mode switching control means and the display signal processing means.

As described above, when the energy saving mode is operated, since the first signal detecting means detects whether or not the virtual input signal has been input, it is not necessary to detect whether or not the video input signal has been input by the second signal detecting means in order to return to the normal mode. According to this, since the power supply to the second signal detecting means can be stopped until the virtual signal input is detected by the first signal detecting means, the electric power supplied to the second signal detecting means can be reduced. Further, since the supply of the power mode switching control means and the display signal processing means is stopped in the energy saving mode, the supply of the power mode switching control means and the display signal processing means can be reduced. Part of the electricity. Therefore, the power consumption of the energy saving mode can be suppressed to a small extent as much as possible.

Further, when it is detected by the first signal detecting means that the virtual input signal has been input, the power is supplied to the second signal detecting means to detect whether or not the video input signal has been input. Then, if it is detected by the second signal detecting means that the video input signal has been input, the intrinsic energy mode is switched to the normal mode. Therefore, for example, the user can easily return to the normal mode by introspecting the energy mode without performing an operation such as pressing a predetermined button.

1, 2‧‧‧ display devices

11‧‧‧1st signal detection means

12‧‧‧Electronic switch control

13‧‧‧Power mode switching control means

14‧‧‧2nd signal detection means

15‧‧‧Electronic switch (1st electronic switch)

16‧‧‧Power tact switch

17‧‧‧Power light

18‧‧‧Display Signal Processing Department

19‧‧‧ Display panel

81‧‧‧Power storage circuit

82‧‧‧ Storage level detection/control means

83‧‧‧2nd electronic switch

PS1‧‧‧1st power supply

PS2‧‧‧2nd power supply

PS3‧‧‧3rd power supply

Fig. 1 is a block diagram showing the configuration of a display device 1 according to the first embodiment of the present invention.

Fig. 2 is a view for explaining state transition of a power mode of a display device of the prior art of the present invention.

Fig. 3 is a view for explaining state transition of the power mode of the display device 1 according to the first embodiment of the present invention.

Fig. 4 is a circuit diagram showing a configuration of a display device 1 according to the first embodiment of the present invention.

Fig. 5 is a flow chart showing the processing procedure of the AC conduction processing of the display device 1.

Fig. 6 is a flow chart showing the processing procedure of the DC ON/OFF processing of the display device 1.

Fig. 7 is a flow chart showing the processing procedure of the normal mode processing of the display device 1.

Fig. 8 is a flow chart showing the processing procedure of the energy saving mode processing of the display device 1.

Fig. 9 is a block diagram showing an example of a specific configuration of the first signal detecting means 11.

Fig. 10 is a block diagram showing another example of the specific configuration of the first signal detecting means 11.

Fig. 11 is a block diagram showing the configuration of a display device 2 according to a second embodiment of the present invention.

Fig. 12 is a circuit diagram showing a configuration of a display device 2 according to a second embodiment of the present invention.

<First embodiment>

Fig. 1 is a block diagram showing the configuration of a display device 1 according to the first embodiment of the present invention. The display device 1 is connected to an external device, and is specifically connected to an external computer device (hereinafter also referred to as an "external computer device"). The external device is not limited to a computer device, and may be an electronic device other than the computer device.

The display device 1 can be configured to operate in a power saving mode (hereinafter also referred to as "energy saving mode") that suppresses the power consumption operation in a normal mode. Here, the normal mode refers to an operation state in which characters and images are displayed in a state recognizable by the user in response to a signal supplied from a computer device using a power supply voltage supplied from a power source. The power saving mode is an operation state in which the power supply voltage supplied from the power source is suppressed or the power consumption of the display device is suppressed without using the power supply voltage.

In the present embodiment, the display device 1 is a liquid crystal display device. The display device 1 includes a first signal detecting means 11, an electronic switch control means 12, a power mode switching control means 13, a second signal detecting means 14, an electronic switch 15, a power tap switch 16, a power source lamp 17, and a display signal processing unit. 18. The display panel unit 19, the first power source PS1, and the second power source PS2 are formed. The display signal processing unit 18 corresponds to a display signal processing means, and the display panel unit 19 corresponds to a display means.

The first signal detecting means 11 is electrically connected to the first power source PS1, the electronic switch control means 12, and the power mode switching control means 13. The electronic switch control means 12 is electrically connected to the first power source PS1, and also electrically connects the electronic switch 15 to the second power source PS2. Further, the electronic switch control means 12 is electrically connected to the power mode switching control means 13. The power mode switching control means 13 is electrically connected to the second power source PS2, the second signal detecting means 14, the power source tact switch 16, and the power source lamp 17. The second signal detecting means 14 is electrically connected to the second power source PS2.

The first signal detecting means detects whether or not a virtual input signal has been input from the external computer device. The virtual input signal refers to a signal that can be analogized from an input signal input from an external computer device. When detecting that the virtual input signal has been input, the first signal detecting means 11 supplies the first conduction control signal (ONCS1) to the electronic switch control means 12 and the power mode switching control means 13. The first conduction control signal (ONCS1) is a high level (Hi) pulse signal.

Electronic switch control means 12 is the first signal detection hand The first conduction control signal (ONCS1) supplied from the segment 11 serves as a trigger, and the electronic switch 15 is turned on. As a result, the second power source PS2 is turned on, and electric power is supplied to the power mode switching control means 13, the second signal detecting means 14, and the display signal processing unit 18 in the subsequent stage. In this way, the electronic switch control means 12 switches to the supply state in which the power mode switching control means 13, the second signal detecting means 14, and the display signal processing unit 18 supply electric power and the supply stop state in which the supply of the electric power is stopped. In the supply state, power is also supplied to the power lamp 17 and the display panel unit 19, and the supply of power to the power lamp 17 and the display panel unit 19 is also stopped in the supply stop state.

The second signal detecting means 14 detects the presence or absence of the input of the so-called video input signal, that is, whether or not the video input signal has been input from the external computer device. When detecting the presence or absence of the input of the video input signal, the second signal detecting means 14 supplies the second on/off control signal (ON/OFF CS2) to the power mode switching control means 13.

The video input signal includes an RGB image signal, a horizontal synchronization signal, and a vertical synchronization signal composed of a red (Red; R for short) signal, a green (Green; abbreviated as G) signal, and a blue (Blue; B) signal. Composition. The second signal detecting means 14 detects the presence or absence of the input of the video input signal by performing the horizontal synchronizing signal and the frequency detecting of the vertical synchronizing signal.

The power mode switching control means 13 switches between the normal mode and the energy saving mode based on the detection result of the second signal detecting means 14. specific When the power mode switching control means 13 receives the second on/off control signal (ON/OFFCS2) indicating that the video input signal has been supplied from the second signal detecting means 14, the power source lamp 17 is turned on, and The electric power is supplied to the display panel unit 19, and the screen display of the display panel unit 19 is turned on. According to this, the introspection mode is switched to the normal mode. Here, "the screen display is turned on" means that the display screen is in the state of the displayed image, and "the screen display is turned off" means that the display screen is not displayed.

When the power mode switching control means 13 receives the second on/off control signal (ON/OFFCS2) indicating that the video input signal is not supplied from the second signal detecting means 14, the detection result of the first signal detecting means 11 is obtained. As the error detection, the shutdown control signal (OFFCS) is supplied to the electronic switch control means 12. The shutdown control signal (OFFCS) is a high level pulse signal.

When the electronic switch control means 12 receives the shutdown control signal (OFFCS) provided by the power mode switching control means 13, the shutdown control signal (OFFCS), that is, the high level pulse signal is used as a trigger, and the electronic switch 15 is turned off. In the off state, the second power source PS2 is turned off. As a result, the electronic switch control means 12 stops the supply of electric power to the power mode switching control means 13, the second signal detecting means 14, and the display signal processing unit 18 in the subsequent stage, and maintains the energy saving mode to become the first signal detection again. The signal of the means 11 is in a state of waiting for the state.

When the power mode switching control means 13 is in the ON state of the AC to be described later, the third conduction control signal (ONCS3) is supplied to the power. Sub-switch control means 12. The third conduction control signal (ONCS3) is a high-level pulse signal.

When receiving the third conduction control signal (ONCS3) supplied from the power mode switching control means 13, the electronic switch control means 12 uses the third conduction control signal (ONCS3), that is, the high-level pulse signal as a trigger, and the electronic switch 15 In the on state, the second power source PS2 is turned on. Accordingly, the electronic switch control means 12 supplies electric power to the power mode switching control means 13 and initializes the main microcomputer.

The power lamp 17 indicates the state of the power source of the display device 1 itself. The display signal processing unit 18 performs processing for displaying an image indicated by the video input signal on the display panel unit 19 for the video input signal input from the external computer device. The display panel unit 19 displays an image on a display screen based on a video input signal processed by the display signal processing unit 18.

When the first power source PS1 is connected to an alternating current (AC) power source (hereinafter referred to as "AC conduction"), normal power is supplied. The second power source PS2 is capable of supplying and blocking power by the electronic switch 15. In the display device 1, the electronic switch 15 is turned off by the electronic switch control means 12, thereby blocking the second power supply PS2, and stopping the power mode switching control means 13, the second signal detecting means 14, the power supply lamp 17, and the display. The supply of electric power to the signal processing unit 18 and the display panel unit 19 operates in such a manner as to be in an off state.

In this way, the power mode switching control means 13, the second The signal detecting means 14, the power source lamp 17, the display signal processing unit 18, and the display panel unit 19 stop the supply of electric power, and the state in which these are turned off is referred to as a standby state. The operation mode of the display device 1 in the standby state is the energy saving mode (hereinafter also referred to as "energy saving mode") in the present invention. In other words, the state of the display device operating in the energy saving mode is the standby state. In the standby state, the above-described supply stop state is obtained.

Fig. 2 is a view for explaining state transition of a power mode of a display device of the prior art of the present invention. Fig. 3 is a view for explaining state transition of the power mode of the display device 1 according to the first embodiment of the present invention. Power mode refers to an action mode that is classified according to different power supply states.

As shown in FIG. 2, in the premise technique, when it is determined that there is no input of a video signal from the state in which the power is supplied from the power source, that is, the normal mode 21, the sleep mode 22 is switched. In the sleep mode 22, if it is determined that there is an input of a video signal, the mode is switched to the normal mode 21. Further, in the sleep mode 22, when the power switch is turned off (hereinafter also referred to as "DC OFF"), the power is turned off to the shutdown mode 23 for stopping the supply of power to all the operating units. In the shutdown mode 23, when the power switch is turned on (hereinafter also referred to as "DC on"), the mode is switched to the normal mode 21. In the normal mode 21, when the DC is turned off, the mode is switched to the shutdown mode 23.

The sleep mode refers to a situation in which the display device can be returned to the normal mode based on the reception of a signal supplied from an external device connected or the cause of the internal function of the sensor or the like. The shutdown mode refers to a state of waiting for activation by the power switch.

As shown in FIG. 3, in the display device 1 of the present embodiment, any of the sleep mode 22 and the shutdown mode 23 in the premise technology is in the "energy saving mode", and the standby power is also the same. The difference from the premise technology is that the display device 1 of the present embodiment includes a non-volatile memory, and the operation of the power switch is stored in the non-volatile memory. In the display device 1 of the present embodiment, the operation state is shifted by the operation in which the power switch is turned on in the ON state or the power switch is turned off in the OFF state.

Specifically, in the normal mode 21, if it is determined that there is no input of the video signal, that is, if there is no video input signal, the mode is switched to the energy saving mode 25. At this time, the DC is on. When it is determined that there is a video signal input in the power saving mode 25 in the DC ON state, it is determined that there is a video input signal, and the mode is switched to the normal mode 21. Further, in the power saving mode 25 in the DC ON state, when the DC OFF state is reached, the energy saving mode 26 in the DC OFF state is switched. When the power-saving mode 26 of the DC OFF state is reached, the mode is switched to the normal mode 21 when the DC-on state is reached. In the normal mode 21, if it is in the DC OFF state, it is switched to the energy saving mode 26 of the DC OFF state.

The display device 1 of the present embodiment includes a power tap switch 16 as a power switch. By repeatedly performing the pressing operation of the power switch, the DC-on and DC-off states, that is, the on and off states of the power switch, are called, so-called switching.

Fig. 4 is a circuit diagram showing a configuration of a display device 1 according to the first embodiment of the present invention. Display device 1 is provided with first signal detection The means 11, the electronic switch control means 12, the power mode switching control means 13, the second signal detecting means 14, the electronic switch 15, the power tap switch 16, the first power source PS1, the second power source PS2, the thirteenth resistor 48, and the 14th The resistor 50, the fifteenth resistor 52, the sixteenth resistor 54, the seventeenth resistor 56, the fifth bipolar transistor 49, the sixth bipolar transistor 55, the second diode 53, and the capacitor 51 are formed.

The electronic switch control means 12 includes a first resistor 31, a second resistor 33, a third resistor 34, a fourth resistor 35, a fifth resistor 36, a sixth resistor 38, a seventh resistor 39, an eighth resistor 42, and a ninth resistor. 43. The tenth resistor 44, the eleventh resistor 45, the twelfth resistor 47, the first bipolar transistor 32, the second bipolar transistor 37, the third bipolar transistor 41, the fourth bipolar transistor 46, and The first diode 40.

The first, second, fourth, fifth, and sixth bipolar transistors 32, 37, 46, 49, and 55 are NPN type bipolar transistors. The third bipolar transistor 41 is a PNP type bipolar transistor. The following description also refers to the case where the bipolar transistor is simply referred to as a "transistor." The electronic switch 15 is a P-channel Field Effect Transistor (FET). The following description also refers to the case where the electronic switch 15 is referred to as "FET 15".

The first signal detecting means 11 is connected to one ends of the first resistor 31 and the thirteenth resistor 48, respectively. The other end of the thirteenth resistor 48 is connected to the power mode switching control means 13. The other end of the first resistor 31 is connected to the base of the first transistor 32. The emitter of the first transistor 32 is connected to the ground line. The collector of the first transistor 32 is connected to the first power source PS1 by interposing the second resistor 33. The collector of the first transistor 32 and the fifth transistor The collector connection point of 49 is connected to one end of the power tap switch 16. The other end of the power tact switch 16 is connected to the ground line.

The first power source PS1 is connected to the power mode switching control means 13 by interposing the third resistor 34 and the fourth resistor 35. One end of the power tact switch 16, the other end of the third resistor 34, and a connection point of one end of the fourth resistor 35 are connected to one end of the fifth resistor 36. The other end of the fifth resistor 36 is connected to the base of the second transistor 37. The emitter of the second transistor 37 is connected to the ground line. The collector of the second transistor 37 is connected to the first power source PS1 via the sixth resistor 38.

The other end of the sixth resistor 38 and the collector of the second transistor 37 are connected to one end of the seventh resistor 39. The other end of the seventh resistor 39 is connected to the fourth transistor 46 by interposing the eleventh resistor 45. The emitter of the fourth transistor 46 is connected to the ground line.

A connection point between the other end of the seventh resistor 39 and one end of the eleventh resistor 45 is connected to the cathode of the first diode 40. The anode of the first diode 40 is connected to the collector of the third transistor 41 and one end of the eighth resistor 42. The other end of the eighth resistor 42 is connected to the ground line.

The base of the third transistor 41 is connected to one end of the ninth resistor 43. The other end of the ninth resistor 43 and the collector of the fourth transistor 46 are connected to the other end of the tenth resistor 44. A connection point between the emitter of the third transistor 41 and one end of the tenth resistor 44 is connected to the gate of the FET 15.

A connection point between one end of the tenth resistor 44 and the gate of the FET 15 is connected to the other end of the twelfth resistor 47. FET15 source and 12th A connection point of one end of the resistor 47 is connected to the first power source PS1. The drain of the FET 15 is connected to the second power source PS2.

The other end of the seventh resistor 39, the cathode of the first diode 40, and the connection point of one end of the eleventh resistor 45 are connected to one end of the seventeenth resistor 56 and the collector of the sixth transistor 55. The other end of the 17th resistor 56 is connected to the ground line. The emitter of the sixth transistor 55 is connected to the ground line. The base of the sixth transistor 55 is connected to the power mode switching control means 13 by interposing the 16th resistor 54.

The power mode switching control means 13 is connected to the second power source PS2. Further, the power mode switching control means 13 is connected to the first signal detecting means 11 and the power source lamp 17. The power mode switching control means 13 is connected to the base of the fifth transistor 49 by interposing the 14th resistor 50. The emitter of the fifth transistor 49 is connected to the ground line.

The first power source PS1 is connected to the positive terminal of the capacitor 51. The negative terminal of the capacitor 51 is connected to one end of the fifteenth resistor 52. The other end of the fifteenth resistor 52 is connected to the ground line.

A connection point between the negative electrode terminal of the capacitor 51 and one end of the fifteenth resistor 52 is connected to the cathode of the second diode 53 and the other end of the 14th resistor 50. The anode of the second diode 53 is connected to the ground line. The second signal detecting means 14 is connected to the power mode switching control means 13.

The power mode switching control means 13 is configured by including peripheral circuits such as a main microcomputer and a non-volatile memory. In the present embodiment, the power mode switching control means 13 is configured to operate by the software control of the main microcomputer.

In the present embodiment, the electronic switch control means 12 is composed of a hardware. Unlike the present embodiment, the electronic switch control means 12 can be operated by software control of a sub-microcomputer in the same manner as the power mode switching control means 13.

Fig. 5 is a flow chart showing the processing procedure of the AC conduction processing of the display device 1. Each processing of the flowchart shown in FIG. 5 is executed by the first signal detecting means 11, the electronic switch control means 12, the power mode switching control means 13, and the second signal detecting means 14. The processing of the flowchart shown in FIG. 5 is started when the AC power supply of the display device 1 is introduced and the AC is turned on, and the process proceeds to step a1.

In the step a1, the power mode switching control means 13 outputs the third ON control signal (ONCS3), that is, the Hi pulse signal, once the AC is turned on. In the present embodiment, as shown in Fig. 4, a Hi pulse signal is generated by the rising waveform of the first power source PS1.

In the step a2, the electronic switch control means 12 uses the Hi pulse signal outputted in the step a1 as a trigger, and turns the second power supply PS2 into an ON state by turning the electronic switch 15 into an ON state. As a result, the electronic switch control means 12 activates the power of the power mode switching control means 13 in the step a3, and initializes the main microcomputer in the power mode switching control means 13 to start.

After the main microcomputer is started, the power mode switching control means 13 outputs the masking control signal (MKCS) to the first signal detecting means 11 in step a4, thereby stopping the output of the first signal detecting means 11 which is no longer necessary. The first signal detecting means 11 is based on the power mode The occlusion control signal (MKCS) input by the switching control means 13 stops the output of the first pulsation control signal (ONCS1), that is, the Hi pulse signal.

In step a5, the power mode switching control means 13 performs a state check. The state check refers to an operation of reading information (hereinafter, also referred to as "DC ON/OFF information") in which the previous non-volatile memory in the power mode switching control means 13 is DC-on or DC-off. The DC turn-on/turn-off information is stored in non-volatile memory and represents the state of the power switch.

In the step a6, the power mode switching control means 13 determines whether or not the DC OFF state is based on the result of the state check in the step a5. In step a6, when it is determined that the DC is off state, the process proceeds to step a7, and when it is determined to be the non-DC off state, that is, when it is determined to be the DC conduction state, the process proceeds to step a9.

In step a7, the power mode switching control means 13 outputs a shutdown control signal (OFFCS), that is, a Hi pulse signal, to the electronic switch control means 12. In the step a8, the electronic switch control means 12 causes the electronic switch 15 to be turned off by using the Hi pulse signal which is the OFF control signal (OFFCS) input from the power mode switching control means 13 as a trigger. After the processing of step a8 is completed, the entire processing sequence is ended.

In step a9, the power mode switching control means 13 lights the power lamp 17. After the processing of step a9 is completed, the entire processing sequence is ended.

Fig. 6 is a flow chart showing the processing procedure of the DC ON/OFF processing of the display device 1. The processing of the flowchart shown in Fig. 6 The first signal detecting means 11, the electronic switch control means 12, the power mode switching control means 13, the second signal detecting means 14, and the power tap switch 16 are executed. The processing of the flowchart shown in Fig. 6 is started when the user of the display device 1 presses the power tap switch 16, and switches to step b1.

In step b1, the power tap switch 16 outputs a second level ON signal (ONCS2), that is, a low level (Lo) pulse signal, to the electronic switch control means 12. Further, the power tap switch 16 outputs a first ON/OFF control signal (ON/OFF CS1), that is, a Lo pulse signal, to the power mode switching control means 13.

In the step b2, the electronic switch control means 12 uses the Lo pulse signal of the second ON control signal (ONCS2) outputted in the step b1 as a trigger, and turns the second power supply PS2 into conduction by turning the electronic switch 15 into an ON state. status.

In step b3, the electronic switch control means 12 determines whether or not the first ON/OFF control signal (ON/OFFCS1), that is, the Lo pulse signal, has been input to the power mode switching control means 13. When the DC is on, the first ON/OFF control signal (ON/OFFCS1) is input to the power mode switching control means 13, but is not input when the DC is off.

When it is determined in step b3 that the electronic switch control means 12 has been input, the electronic switch control means 12 switches to step b4, and turns on the power of the power mode switching control means 13 to initialize the main microcomputer. After the startup of the main microcomputer, the process proceeds to step b5, and the power mode switching control means 13 stops the first letter that is no longer needed by outputting the mask control signal (MKCS). The output of the number detecting means 11.

When the DC microcomputer is turned off, the main microcomputer is activated. Therefore, when the input of the Lo pulse signal is detected in the first ON/OFF control signal (ON/OFFCS1) of the power mode switching control means 13 in step a3, The initial processing of the main microcomputer is not executed, and the process proceeds to step b6.

Next, in step b6, the power mode switching control means 13 performs a state check. Specifically, the power mode switching control means 13 reads, from the non-volatile memory, DC ON/OFF information which is DC ON or DC OFF before the power tap switch 16 is pressed.

Then, in step b7, the power mode switching control means 13 determines whether or not it is the DC OFF state. In the DC OFF state, the power mode switching control means 13 switches to step b8 to illuminate the power lamp 17. Then, in step b9, the power mode switching control means 13 changes the state of the non-volatile memory, specifically the state of the power switch of the DC on/off information, to the state of the DC conduction state. Write non-volatile memory and end DC conduction processing.

In step b7, if it is in the DC conduction state, the power mode switching control means 13 switches to step b10, and turns off the power lamp 17, and in step b11, changes the data of the non-volatile memory to the state. The DC is turned off and written to the non-volatile memory. Then, in step b12, the power mode switching control means 13 outputs a shutdown control signal (OFFCS), that is, a Hi pulse signal, to the electronic switch control means 12. In step b13, the electronic switch control means 12 is an electronic switch 15 is made to be in the off state, and the processing of the DC off state is ended.

Fig. 7 is a flow chart showing the processing procedure of the normal mode processing of the display device 1. In the normal mode processing, in step c1, the power mode switching control means 13 determines whether or not the video input signal has been input based on the second on/off control signal (ON/OFFCS2) input by the second signal detecting means 14. That is, the display device 1 monitors the video input signal by the second on/off control signal (ON/OFFCS2) input by the second signal detecting means 14 in the normal mode.

When there is no video input signal, in step c1, the power mode switching control means 13 determines that the second ON/OFF control signal (ON/OFF CS2) is not input, and switches to step c2, and supplies the power lamp 17 Extinguished. Then, in step c3, the power mode switching control means 13 outputs a shutdown control signal (OFFCS), that is, a Hi pulse signal. In step c4, the electronic switch control means 12 switches the electronic switch 15 to the off state and switches to the energy saving mode process, specifically, to step c5 of Fig. 8.

Fig. 8 is a flow chart showing the processing procedure of the energy saving mode processing of the display device 1. In the power saving mode processing, in step c5, the power mode switching control means 13 determines whether or not the input analog video input signal has been input based on the first conduction control signal (ONCS1) input by the first signal detecting means 11. Virtual input signal. That is, the display device 1 monitors the virtual input signal to which the analog video input signal can be input by the first ON control signal (ONCS1) input by the first signal detecting means 11 in the power saving mode.

When there is a virtual input signal, the first signal detecting means 11 outputs a first ON control signal (ONCS1), that is, a Hi pulse signal. Accordingly, in step c5, it is determined that the input has been made, and the process proceeds to step c6.

In the step c6, the electronic switch control means 12 uses the Hi-pulse signal, which is the first ON-control signal (ONCS1) input from the first signal detecting means 11, as a trigger, and turns the electronic switch 15 into an ON state, thereby making the power supply PS2. On state. As a result, the electronic switch control means 12 sets the power of the power mode switching control means 13 to the on state in step c7, and initializes the main microcomputer. After the main microcomputer is started, in step c8, the power mode switching control means 13 stops the output of the first signal detecting means 11 which is no longer necessary by outputting the masking control signal (MKCS).

Then, in step c9, the power mode switching control means 13 performs a state check. Specifically, the power mode switching control means 13 reads information of DC conduction or DC OFF by the non-volatile memory.

In step c10, the power mode switching control means 13 determines whether or not the DC ON state is present, and if it is in the DC ON state, the process proceeds to step c11, and if it is in the DC OFF state, the process proceeds to step c13.

In step c11, the power mode switching control means 13 determines whether or not the second on/off control signal (ON/OFF CS2) has been input by the second signal detecting means 14, thereby checking for the presence or absence of the video input signal.

When there is a video input signal, in step c11, the power mode switching control means 13 determines that it has been input and switches to step. At step c12, the power lamp 17 is turned on. After the process of step c12 ends, the process returns to step c1 to switch to the normal mode process. In step c11, when it is determined that the input is not made, the process proceeds to step c13.

In step c13, the power mode switching control means 13 outputs a turn-off control signal (OFFCS), that is, a Hi pulse signal, to the electronic switch control means 12. In step c14, the electronic switch control means 12 sets the electronic switch 15 to the off state. After the process of step c14 is completed, the process returns to step c5 to operate in the manner of continuing the process of the energy saving mode. Although it is not the same as FIG. 8, but it is also desired to return to the DC OFF state, the processes of step c9 and step c10 may not be performed, and step c8 may be switched to step c11.

As described above, according to the present embodiment, when the first signal detecting means 11 detects whether or not the virtual input signal has been input when operating in the energy saving mode, it is not necessary to detect whether or not the second signal detecting means is used to return to the normal mode. The video input signal has been input. According to this, since the power supply to the second signal detecting means 14 can be stopped until the virtual signal input is detected by the first signal detecting means 11, the electric power supplied to the second signal detecting means 14 can be reduced.

Further, since the power supply to the power mode switching control means 13 and the display signal processing unit 17 is stopped in the energy saving mode, the power supplied to the power mode switching control means 13 and the display signal processing unit 17 can be reduced. Therefore, the power consumption of the energy saving mode can be suppressed to a small extent as much as possible.

Further, if detected by the first signal detecting means 11, When the virtual input signal has been input, power is supplied to the second signal detecting means 14 to detect whether or not the video input signal has been input. Then, when the second signal detecting means 14 detects that the video input signal has been input, the intrinsic energy mode is switched to the normal mode. Therefore, for example, the user can easily return to the normal mode by introspecting the energy mode without performing an operation such as pressing a predetermined button.

Further, in the present embodiment, the display device 1 operates as follows. When it is determined that there is no input of the video signal from the external computer device, that is, when it is determined that the video input signal is not input, the display device 1 turns off the power source lamp 17 and turns off the screen display of the display panel unit 19 to the off state. When it is determined that there is an input of a video signal from an external computer device, that is, when it is determined that the video input signal has been input, the display device 1 turns on the power source lamp 17 and turns on the screen display of the display panel unit 19. By doing so, the power consumption in the energy saving mode can be further reduced.

Fig. 9 is a block diagram showing an example of a specific configuration of the first signal detecting means 11. In the ninth diagram, the first signal detecting means 11 includes a first diode 61, a second diode 62, a non-volatile memory 63, an edge detecting means 64, and an amplifier 65. The non-volatile memory 63 is equivalent to a memory means.

The anode of the first diode 61 receives supply of a power supply potential Vcc from an external computer device. The anode of the second diode 62 is connected to the first power source PS1. The connection point between the cathode of the first diode 61 and the cathode of the second diode 62 is connected to the non-volatile memory 63. Non-volatile record The memory 63 is connected to the edge detecting means 64. The edge detecting means 64 is connected to the amplifier 65. The non-volatile memory 63 and the edge detecting means 64 are respectively connected with a serial communication bus, specifically, an I2C serial communication bus, and input a serial timing signal (SCL) and a serial data signal ( SDA).

The non-volatile memory 63 is the same as the external display device (Extended Display Identification Data; hereinafter referred to as "EDID data") for reading the display device 1 according to the display device 1.

Non-volatile memory 63 is a memory EDID data. The non-volatile memory 63 is constructed by an external computer device capable of reading EDID data from the non-volatile memory 63. The EDID data is equivalent to identifying the identification information of the display device 1 itself.

The first signal detecting means 11 receives a read signal for reading EDID data (hereinafter referred to as "read signal of EDID data") from an external device. The first signal detecting means 11 uses the read signal of the EDID data as a virtual input signal, and the edge detecting means 64 detects the reading of the existing EDID data between the external computer device and the display device 1. The read signal of the EDID data used as the dummy input signal is specifically the serial clock signal (SCL) and the serial data signal (SDA) input from the aforementioned I2C serial communication bus.

The first signal detecting means 11 outputs a first conduction control signal (ONCS1) indicating that the virtual input signal is output by the amplifier 65 after the edge detecting means 64 detects the reading of the existing EDID data. That is, the Hi pulse signal operates in a manner.

The occlusion control signal (MKCS) from the power mode switching control means 13 is a signal required for the first conduction control signal (ONCS1), that is, a signal that is not required for the Hi pulse signal, during the activation or operation of the main microcomputer. action. In other words, during the startup or operation of the main microcomputer, the power mode switching control means 13 inputs the masking control signal (MKCS), thereby stopping the first conduction control signal (ONCS1), that is, the Hi pulse signal from the first signal detecting means 11. Output.

By configuring the first signal detecting means 11 as described above, it is possible to realize the display device 1 in which the power consumption of the energy saving mode is suppressed to a small extent as much as possible, and the energy mode can be easily restored to the normal mode.

Fig. 10 is a block diagram showing another example of the specific configuration of the first signal detecting means 11. The first signal detecting means 11 shown in Fig. 10 is similar to the first signal detecting means 11 shown in the ninth drawing. Therefore, the same portions as those of the first signal detecting means 11 shown in Fig. 9 are denoted by the same reference numerals, and their description will be omitted. In the tenth diagram, the first signal detecting means 11 is provided with an edge detecting means 64, an amplifier 65, an antenna 66, and a receiving means 67. The antenna 66 is connected to the receiving means 67. The receiving means 67 is connected to the first power source PS1 and the edge detecting means 64.

The external computer device 71 includes a transfer means 72 and an input means (hereinafter also referred to as "console") 73. The input device 73 is provided with a mouse 74 and a keyboard 75. The external computer device 71 is connected by means 72 The presence or absence of the operation of the own apparatus is specifically the first signal detecting means 11 for indicating whether or not the operation of the operation of the input means 73 is transmitted to the display means 1.

The antenna 66 of the first signal detecting means 11 extracts an operation presence/absence signal transmitted from the external computer device 71, and supplies it to the receiving means 67. The receiving means 67 receives the information on whether or not the operation signal supplied from the antenna 66 is received, and reads and acquires information on the presence or absence of the operation of the input device 73. The first signal detecting means 11 uses a read signal which is an operation presence/absence signal read by the receiving means 67 as a virtual input signal.

The receiving means 67 operates to decode the read signal as a virtual input signal, and when the user operates the input device 73, it can operate as a signal having an edge component. When the edge detecting means 64 in the subsequent stage detects a signal having the edge component, the first signal detecting means 11 outputs a Hi pulse signal indicating that the first ON control signal (ONCS1) having the virtual input signal is outputted by the amplifier 65. And the action.

The occlusion control signal (MKCS) from the power mode switching control means 13 is a signal required for the first conduction control signal (ONCS1), that is, a signal that is not required for the Hi pulse signal, during the activation or operation of the main microcomputer. action. In other words, during the startup or operation of the main microcomputer, the power mode switching control means 13 inputs the masking control signal (MKCS), thereby stopping the first on-control signal (ONCS1), that is, the Hi pulse signal from the first signal detecting means 11. Output.

The receiving means 67 can be, for example, a connection between machines. A wireless means such as Bluetooth (registered trademark) or ZigBee (registered trademark) of the short-range wireless communication technology used.

By configuring the first signal detecting means 11 as described above, as in the case of Fig. 9, it is possible to suppress the power consumption of the energy saving mode as small as possible, and to easily return to the introspective energy mode. Display device 1 in the normal mode.

Further, in the tenth diagram, although the wireless receiving means 67 is taken as an example, the same effect can be obtained even by the wired receiving means.

<Second embodiment>

Fig. 11 is a block diagram showing the configuration of a display device 2 according to a second embodiment of the present invention. The display device 2 of the present embodiment is similar to the configuration of the display device 1 of the first embodiment described above. Therefore, in the embodiment, the same portions as those in the first embodiment are denoted by the same reference numerals, and their common description will be omitted.

The display device 2 of the present embodiment is a liquid crystal display device. The display device 2 includes a first signal detecting means 11, an electronic switch control means 12, a power mode switching control means 13, a second signal detecting means 14, a first electronic switch 15, a power tap switch 16, a power source lamp 17, and a display signal. The processing unit 18, the display panel unit 19, the power storage circuit 81, the storage level detecting/controlling means 82, the second electronic switch 83, the first power source PS1, the second power source PS2, and the third power source PS3 are configured. The first electronic switch 15 of the present embodiment corresponds to the electronic switch 15 of the first embodiment.

Fig. 12 is a circuit diagram showing a configuration of a display device 2 according to a second embodiment of the present invention. The configuration of the circuit diagram of the display device 2 of the present embodiment is similar to the configuration of the electrical circuit diagram of the display device 1 of the first embodiment. Therefore, in the embodiment, the same components as those in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted. The display device 2 of the present embodiment considers the configuration of power suppression when the power saving function is achieved by the power storage function.

The display device 2 includes a first signal detecting means 11, an electronic switch control means 12, a power mode switching control means 13, a second signal detecting means 14, a first electronic switch 15, a power tap switch 16, and a second electronic switch 83. The first power source PS1, the second power source PS2, the third power source PS3, the 13th resistor 48, the 14th resistor 50, the 15th resistor 52, the 16th resistor 54, the 17th resistor 56, the 18th resistor 84, and the 19th resistor 86, 20th resistor 87, 21st resistor 91, 22nd resistor 93, 23rd resistor 94, 24th resistor 95, 25th resistor 96, fifth transistor 49, sixth transistor 55, seventh transistor 85, capacitor 51 The second diode 53 and the third diode 88 are formed.

The electronic switch control means 12 includes a first resistor 31, a second resistor 33, a third resistor 34, a fourth resistor 35, a fifth resistor 36, a sixth resistor 38, a seventh resistor 39, an eighth resistor 42, and a ninth resistor. 43. The tenth resistor 44, the eleventh resistor 45, the twelfth resistor 47, the first transistor 32, the second transistor 37, the third transistor 41, the fourth transistor 46, and the first diode 40.

Power storage circuit 81 includes a 21st resistor 91 and a power source 92. The power source 92 is realized by a secondary battery. The storage level detection/control means 82 includes a 22nd resistor 93, a 23rd resistor 94, a 24th resistor 95, a 25th resistor 96, a 1st amplifier 97, and a 2nd amplifier 98.

Similarly to the first, second, fourth, fifth, and sixth transistors 32, 37, 46, 49, and 55, the seventh transistor 85 is an NPN-type bipolar transistor. The first and second electronic switches 15 and 83 are P-channel FETs. In the following description, the first electronic switch 15 will be referred to as "first FET 15", and the second electronic switch 83 will be referred to as "second FET 83".

The first power source PS1 is connected to one end of the 22nd resistor 93. The other end of the 22nd resistor 93 is connected to the second input terminal of the first amplifier 97 and one end of the 23rd resistor 94. The other end of the 23rd resistor 94 is connected to the ground line.

One end of the 22nd resistor 93 is connected to one end of the 24th resistor 95. One end of the 24th resistor 95 is connected to the first power source PS1. The other end of the 24th resistor 95 is connected to the first input terminal of the second amplifier 98 and one end of the 25th resistor 96. The other end of the 25th resistor 96 is connected to the ground line.

One end of the 24th resistor 95 is connected to the power supply terminal of the first amplifier 97. The first amplifier 97 is connected to the second amplifier 98. The second input terminal of the second amplifier 98 is connected to one end of the 21st resistor 91 of the electric storage circuit 81. The other end of the 21st resistor 91 is connected to the positive electrode of the power source 92. The negative electrode of the power source 92 is connected to the ground line. The first input terminal of the first amplifier 97 is connected to one end of the second resistor 33.

An output terminal of the first amplifier 97 and an output terminal of the second amplifier 98 are connected to one end of the 18th resistor 84. The other end of the 18th resistor 84 is connected to the base of the seventh transistor. The emitter of the seventh transistor 85 is connected to the ground line. The collector of the seventh transistor 85 is connected to one end of the 19th resistor 86. The other end of the 19th resistor 86 is connected to one end of the twentieth resistor 87 and the gate of the second FET 83.

The power supply terminal of the first amplifier 97 is connected to the other end of the twentieth resistor 87. The source of the second FET 83 is connected to the other end of the twentieth resistor 87. The drain of the second FET 83 is connected to the anode of the third diode 88. The cathode of the third diode 88 is connected to a connection point between the third power source PS3 and one end of the sixth resistor 38.

The power supply terminal of the first amplifier 97 and the other end of the twentieth resistor 87 are connected to the connection point between the source of the first FET 15 and one end of the twelfth resistor 47.

The collector of the first transistor 32 is connected to the third power source PS3 via the second resistor 33. The third power source PS3 is connected to the power mode switching control means 13 by interposing the third resistor 34 and the fourth resistor 35. The collector of the second transistor 37 is connected to the third power source PS3 via the sixth resistor 38.

Power storage circuit 81 supplies electric power to first signal detecting means 11 and electronic switch control means 12. The electric storage level detection/control means 82 detects the electric storage level of the electric storage circuit 81, and controls the electric storage circuit 81 based on the detection result. When the electric storage level detection/control means 82 determines that the electric storage level of the electric storage circuit 81 has decreased, the second electronic switch 83 is turned on, and the electric storage circuit 81 is charged.

As described above, in the present embodiment, the "third power source PS3" includes the power storage circuit 81 as the power source of the first signal detecting means 11 and the electronic switch control means 12. According to this, since electric power is supplied from the electric storage circuit 81, power consumption can be suppressed.

Further, when the electric storage level detecting/control means 82 determines that the electric storage level has decreased, the display device 2 turns on the second electronic switch 83 from the "first power source PS1" to the "third power source PS3". The power storage circuit 81 performs charging. Accordingly, the display device 2 can be operated to have a function of returning the power storage level of the power storage circuit 81.

In the present embodiment, the electric storage circuit 81 is a storage circuit using a secondary battery. However, the present invention is not limited thereto, and a storage circuit such as a large-capacity capacitor may be used. As described above, the power storage circuit 81 can be realized by using a storage circuit of a secondary battery or a large-capacity capacitor.

In the first and second embodiments described above, the display devices 1 and 2 are described by way of example of a liquid crystal display device. However, the use of the invention is not limited thereto. The present invention can also be applied to other display devices such as a plasma display device and an organic EL display device.

Further, in the first and second embodiments, the first signal detecting means 11 is described by taking a means of using the first input virtual input signal as an example, but the present invention is not limited thereto. The first signal detecting means 11 may be a means of using a logical sum (OR) or an logical product (AND) of a virtual input signal of a different type of complex input. According to this, it is possible to more reliably prevent erroneous judgments and erroneous actions.

1‧‧‧ display device

11‧‧‧1st signal detection means

12‧‧‧Electronic switch control

13‧‧‧Power mode switching control means

14‧‧‧2nd signal detection means

15‧‧‧Electronic switch (1st electronic switch)

16‧‧‧Power tact switch

17‧‧‧Power light

18‧‧‧Display Signal Processing Department

19‧‧‧ Display panel

PS1‧‧‧1st power supply

PS2‧‧‧2nd power supply

Claims (6)

A display device that is connected to an external device and that is operable in a power saving mode in which operation is suppressed in a normal mode by suppressing power consumption, and is characterized in that: the first signal detecting means is provided to operate in the energy saving mode The first signal detecting means detects whether or not the virtual input signal from which the video input signal is input from the external device is input, and the second signal detecting means detects whether or not the video input signal is input from the external device. a power mode switching control means for switching between the normal mode and the energy saving mode based on a detection result of the second signal detecting means; and a display signal processing means for the video input signal input from the external device; a process for displaying an image represented by the video input signal; and an electronic switch control means for switching a supply state of power supplied to the second signal detecting means, the power mode switching control means, and the display signal processing means And stopping the supply of the aforementioned power supply Stop state, the power mode control means for switching the system to the normal mode when the operation by the second signal when the detecting means detects that the input video signal is not input, then from the P When the mode is switched to the energy saving mode, when the second signal detecting means detects that the video input signal has been input, the mode is switched from the energy saving mode to the normal mode. When the second signal detecting means detects that the video input signal is not input, the energy saving mode is maintained, and the electronic switch control means switches from the normal mode to the energy saving mode by the power mode switching control means. When the supply state is switched to the supply stop state, when the first signal detecting means detects that the virtual input signal has been input, the supply state is switched from the supply stop state to the supply state. The power mode switching control means, when the first signal detecting means detects that the virtual input signal has been input, and the second signal detecting means detects that the video input signal is not input, the first signal is obtained The detection result of the detection means is regarded as false detection, and the shutdown control will be The signal is supplied to the electronic switch control means, and the electronic switch control means switches from the supply state to the supply stop state when receiving the shutdown control signal supplied from the power mode switching control means to maintain the foregoing province Energy mode. The display device according to claim 1, wherein The first signal detecting means is provided with a memory means configured to memorize the identification information for identifying the display device itself, and the external device can read the identification information, and the virtual input signal is used to read from the foregoing The read signal of the aforementioned identification information input by the external device. The display device according to claim 1, wherein the first signal detecting means includes receiving means for receiving an operation signal indicating whether or not there is an operation of the external device from the external device, and the virtual input signal Whether there is a signal in the foregoing operation. The display device according to any one of claims 1 to 3, further comprising: a power lamp, which is a state of a power source of the display device itself; and a display means based on the display signal The processing means performs the processed video input signal to display an image on the display screen, and when the electronic switch control means operates in the normal mode, the second signal detecting means detects that the video input signal is not input. And the power lamp is turned off, and the supply of power to the display means is stopped. When the energy saving mode is operated, when the second signal detecting means detects that the video input signal has been input, the foregoing The power lamp is lit and power is supplied to the aforementioned display means. The display device according to any one of claims 1 to 3, further comprising: a power storage circuit that supplies power to the first signal detecting means and the electronic switch control means; and a power storage level The detection/control means detects the electric storage level of the electric storage circuit, and controls the electric storage circuit based on the detection result, and the electric storage level detecting/control means determines the electric storage circuit if the electric storage level of the electric storage circuit is lowered. Charge it. The display device according to claim 4, further comprising: a storage circuit that supplies electric power to the first signal detecting means and the electronic switch control means; and a storage level detecting/control means for detecting The electric storage circuit of the electric storage circuit controls the electric storage circuit based on the detection result, and the electric storage level detecting/controlling means charges the electric storage circuit when it is determined that the electric storage level of the electric storage circuit has decreased.