CN111045729A

CN111045729A - Operation method, device and related product

Info

Publication number: CN111045729A
Application number: CN201910402787.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-10-12
Filing date: 2019-05-15
Publication date: 2020-04-21

Abstract

The disclosure relates to an operation method, an operation device and a related product. The machine learning device comprises one or more instruction processing devices, is used for acquiring data to be operated and control information from other processing devices, executes specified machine learning operation and transmits the execution result to other processing devices through an I/O interface; when the machine learning arithmetic device includes a plurality of instruction processing devices, the plurality of instruction processing devices can be connected to each other by a specific configuration to transfer data. The command processing devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data; the plurality of instruction processing devices share the same control system or own control system and share the memory or own memory; the interconnection mode of the plurality of instruction processing apparatuses is an arbitrary interconnection topology. The operation method, the operation device and the related products provided by the embodiment of the disclosure have the advantages of wide application range, high operation processing efficiency and high processing speed.

Description

Operation method, device and related product

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to an operation method, an operation device, and a related product.

Background

With the continuous development of science and technology, machine learning, especially neural network algorithms, are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the types and the number of involved data operations are increasing. In the related art, the activation operation performed by data is inefficient and slow.

Disclosure of Invention

In view of the above, the present disclosure provides an operation method, an operation device and a related product, so as to improve efficiency and speed of performing activation operation on data.

According to a first aspect of the present disclosure, there is provided an activation instruction processing apparatus, the apparatus including:

the control module is used for analyzing the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and acquiring data to be operated and a target address required by executing the activation instruction according to the operation code and the operation domain;

the operation module is used for carrying out activation operation on the data to be operated to obtain an operation result and storing the operation result into the target address,

the operation code is used for indicating that the operation performed on data by the activation instruction is an activation operation, and the operation domain comprises a data address to be operated and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more of the activation instruction processing apparatuses according to the first aspect described above, configured to acquire data to be operated and control information from another processing apparatus, execute a specified machine learning operation, and transmit an execution result to the other processing apparatus through an I/O interface;

when the machine learning arithmetic device comprises a plurality of the activation instruction processing devices, the plurality of the activation instruction processing devices can be connected through a specific structure and transmit data;

the plurality of activation instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of the activation instruction processing devices share the same control system or own respective control systems; the plurality of the activation instruction processing devices share a memory or own respective memories; the interconnection mode of the plurality of activation instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided an activation instruction processing method applied to an activation instruction processing apparatus, the method including:

analyzing the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and acquiring data to be operated, an activation table, a constant table and a target address required by executing the activation instruction according to the operation code and the operation domain;

according to the activation table and the constant table, performing activation operation on the data to be operated to obtain an operation result, storing the operation result into the target address,

the operation code is used for indicating that the operation performed on data by the activation instruction is an activation operation, and the operation domain comprises a data address to be operated, an activation table address, a constant table address and the target address.

The device comprises a control module and an operation module, wherein the control module is used for analyzing the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and acquiring data to be operated and a target address required by executing the activation instruction according to the operation code and the operation domain; the operation module is used for performing activation operation on data to be operated to obtain an operation result, and storing the operation result into a target address. The method and the device for processing the activation instruction and the related products provided by the embodiment of the disclosure have the advantages of wide application range, high processing efficiency and high processing speed for the activation instruction, and high processing efficiency and high processing speed for performing activation operation.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 2 a-2 f show block diagrams of an activation instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of an application scenario of an activation instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 shows a flow diagram of an activate instruction processing method according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a control module 11 and an operation module 12.

The control module 11 is configured to analyze the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and acquire data to be operated and a target address, which are required for executing the activation instruction, according to the operation code and the operation domain. The operation code is used for indicating that the operation performed on the data by the activation instruction is activation operation, and the operation domain comprises a data address to be operated and a target address.

And the operation module 12 is configured to perform activation operation on data to be operated to obtain an operation result, and store the operation result in the target address.

In this embodiment, the control module may obtain the data to be operated from the data address to be operated. The control module may obtain instructions and data through a data input output unit, which may be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be a part of an instruction or a field (usually indicated by a code) specified in the computer program to perform an operation, and is an instruction sequence number used to inform a device executing the instruction which instruction needs to be executed specifically. The operation field may be a source of all data required for executing the corresponding instruction, such as the corresponding address, all data required for executing the corresponding instruction including data to be operated on, and the corresponding operation method. For an activate instruction it must comprise an opcode and an operation field, wherein the operation field comprises at least the data address to be calculated and the target address.

It should be understood that the instruction format of the activate instruction and the contained opcode and operation field may be set as desired by those skilled in the art, and the disclosure is not limited thereto.

In this embodiment, the apparatus may include one or more control modules and one or more operation modules, and the number of the control modules and the number of the operation modules may be set according to actual needs, which is not limited in this disclosure. When the device comprises a control module, the control module can receive the linear rectification function activation instruction and control one or more processing modules to perform linear rectification function activation operation. When the device comprises a plurality of control modules, the plurality of control modules can respectively receive the linear rectification function activation instruction and control the corresponding one or more processing modules to perform linear rectification function activation operation.

The disclosed embodiment provides an activation instruction processing device, which comprises a control module and an operation module, wherein the control module is used for analyzing an acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and acquiring data to be operated and a target address required by execution of the activation instruction according to the operation code and the operation domain; the operation module is used for performing activation operation on data to be operated to obtain an operation result, and storing the operation result into a target address. The activation instruction processing device provided by the embodiment of the disclosure has a wide application range, and is high in processing efficiency and processing speed of activation instructions, and high in processing efficiency and processing speed of activation operations.

In one possible implementation, the activation function utilized by the activation operation may include at least one of: linear rectification function (Rectified Linear Unit, ReLU, also called ReLU function), S-shaped growth curve function (Sigmoid function, also called Sigmoid function), hyperbolic tangent function (tanh, also called tanh function), Leaky Linear rectification function (leakage ReLU, a variation of ReLU function), max function (maxout function, which outputs the maximum value in the layer), and power function (power function).

In this implementation, the activation function used for performing the activation operation may also be other functions that can be used for the activation operation and have at least one of the characteristics of nonlinearity, continuous micromanipulation, as unsaturated as possible in range, monotonicity, approximate straight line at a circular point, and the like, and the disclosure does not limit this.

In a possible implementation, the control module 11 may be further configured to obtain the activation parameter table according to the operation code and/or the operation domain.

The operation module 12 may also be configured to perform activation operation on the data to be operated according to the activation parameter table to obtain an operation result.

The activation parameter table may include an activation table and a constant table, among others.

In this implementation, the activation parameter table address may be included in the operational domain to facilitate the control module obtaining the activation parameter table address from the activation parameter table address. Or, the control module may directly obtain the activation parameter table from a predetermined storage address of the activation parameter table when determining that the activation parameter table is needed to be activated when executing the activation instruction according to the operation code. Or, the control module may determine that the activation parameter table is required to be activated when executing the activation instruction according to the operation code, and may directly obtain the activation parameter table corresponding to the activation instruction from a predetermined storage address of the parameter table. The person skilled in the art can set the obtaining manner of the activation parameter table according to actual needs, and the disclosure does not limit this.

In a possible implementation manner, the control module may further obtain an activation function corresponding to the activation instruction, so that the operation module may perform activation operation on the data to be operated according to the activation function and the corresponding operator.

It should be noted that, a person skilled in the art may set a manner of implementing the activation operation by the operation module according to actual needs, and the disclosure does not limit this.

In this implementation, the activation table and constant table required for the activation operation using different activation functions may be predetermined. The activation tables and the constant tables corresponding to different activation functions are different.

Fig. 2a shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2a, the arithmetic module 12 may include a plurality of activation operators 120. The plurality of activation operators 120 are used for performing activation operation on data to be operated.

In this implementation, the arithmetic module may also include an activation operator. The number of active operators may be set according to the data size of the active operation required, the processing speed, efficiency and the like of the active operation, which is not limited by the present disclosure.

Fig. 2b shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2b, the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122, wherein the master operation sub-module 121 includes a plurality of activation operators 120 (not shown).

And the main operation sub-module 121 is configured to perform activation operation on data to be operated by using multiple activation operators to obtain an operation result, and store the operation result in a target address.

In a possible implementation manner, the control module 11 is further configured to compile the obtained calculation instruction to obtain a compiled calculation instruction, and obtain data to be operated, which is required for executing the compiled calculation instruction.

The operation module 12 is further configured to perform an operation on the data to be operated according to the compiled calculation instruction, so as to obtain an operation result. The operation module 12 may include a plurality of operators 120. The plurality of operators 120 are for performing operations corresponding to operation types of the computation instructions.

In this implementation, the calculation instruction may be an instruction that performs arithmetic operation, logical operation, and other operations on data such as scalars, vectors, matrices, tensors, and the like, different from the linear rectification function activation instruction, for example, a scalar calculation instruction, a convolution calculation instruction, and the like. The calculation instruction obtained by the control module is an uncompiled software instruction which cannot be directly executed by hardware, and the control module needs to compile the calculation instruction (uncompiled) first. The compiled computing instructions are hardware instructions that can be directly executed by hardware.

In this implementation manner, the control module is further configured to analyze the compiled calculation instruction to obtain an operation code and an operation domain of the calculation instruction, and obtain data to be calculated according to the operation code and the operation domain.

In this implementation, the operator may include an adder, a divider, a multiplier, a comparator, and the like capable of performing arithmetic operations, logical operations, and the like on data. The type and number of the arithmetic units may be set according to the requirements of the size of the data amount of the arithmetic operation to be performed, the type of the arithmetic operation, the processing speed and efficiency of the arithmetic operation on the data, and the like, which is not limited by the present disclosure.

In a possible implementation manner, the control module 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the data to be operated and the plurality of operation instructions to the main operation sub-module 121.

The master operation sub-module 121 is configured to perform preamble processing on data to be operated, and transmit data and operation instructions with the plurality of slave operation sub-modules 122.

The slave operation submodule 122 is configured to execute an intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation submodule 121 to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master operation submodule 122.

The main operation sub-module 121 is further configured to perform subsequent processing on the plurality of intermediate results to obtain an operation result.

In this implementation, when the computation instruction is an operation performed on scalar or vector data, the apparatus may control the main operation sub-module to perform an operation corresponding to the computation instruction by using an operator therein. When the calculation instruction is to perform an operation on data having a dimension greater than or equal to 2, such as a matrix, a tensor, or the like, the device may control the slave operation submodule to perform an operation corresponding to the calculation instruction by using an operator therein.

It should be noted that, a person skilled in the art may set the connection manner between the master operation submodule and the plurality of slave operation submodules according to actual needs to implement the configuration setting of the operation module, for example, the configuration of the operation module may be an "H" configuration, an array configuration, a tree configuration, and the like, which is not limited in the present disclosure.

Fig. 2c shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2c, the operation module 12 may further include one or more branch operation sub-modules 123, and the branch operation sub-module 123 is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. The main operation sub-module 121 is connected to one or more branch operation sub-modules 123. Therefore, the main operation sub-module, the branch operation sub-module and the slave operation sub-module in the operation module are connected by adopting an H-shaped structure, and data and/or operation instructions are forwarded by the branch operation sub-module, so that the resource occupation of the main operation sub-module is saved, and the instruction processing speed is further improved.

Fig. 2d shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in FIG. 2d, a plurality of slave operation sub-modules 122 are distributed in an array.

Each slave operation submodule 122 is connected to another adjacent slave operation submodule 122, the master operation submodule 121 is connected to k slave operation submodules 122 of the plurality of slave operation submodules 122, and the k slave operation submodules 122 are: n slave operator sub-modules 122 of row 1, n slave operator sub-modules 122 of row m, and m slave operator sub-modules 122 of column 1.

As shown in fig. 2d, the k slave operator modules include only the n slave operator modules in the 1 st row, the n slave operator modules in the m th row, and the m slave operator modules in the 1 st column, that is, the k slave operator modules are slave operator modules directly connected to the master operator module among the plurality of slave operator modules. The k slave operation submodules are used for forwarding data and instructions between the master operation submodules and the plurality of slave operation submodules. Therefore, the plurality of slave operation sub-modules are distributed in an array, the speed of sending data and/or operation instructions to the slave operation sub-modules by the master operation sub-module can be increased, and the instruction processing speed is further increased.

Fig. 2e shows a block diagram of an activation instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2e, the operation module may further include a tree sub-module 124. The tree submodule 124 includes a root port 401 and a plurality of branch ports 402. The root port 401 is connected to the master operation submodule 121, and the plurality of branch ports 402 are connected to the plurality of slave operation submodules 122, respectively. The tree sub-module 124 has a transceiving function, and is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. Therefore, the operation modules are connected in a tree-shaped structure under the action of the tree-shaped sub-modules, and the speed of sending data and/or operation instructions from the main operation sub-module to the auxiliary operation sub-module can be increased by utilizing the forwarding function of the tree-shaped sub-modules, so that the instruction processing speed is increased.

In one possible implementation, the tree submodule 124 may be an optional result of the apparatus, which may include at least one level of nodes. The nodes are line structures with forwarding functions, and the nodes do not have operation functions. The lowest level node is connected to the slave operation sub-module to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. In particular, if the tree submodule has zero level nodes, the apparatus does not require the tree submodule.

In one possible implementation, the tree submodule 124 may include a plurality of nodes of an n-ary tree structure, and the plurality of nodes of the n-ary tree structure may have a plurality of layers.

For example, fig. 2f shows a block diagram of an activation instruction processing device according to an embodiment of the present disclosure. As shown in FIG. 2f, the n-ary tree structure may be a binary tree structure with tree-type sub-modules including 2 levels of nodes 01. The lowest level node 01 is connected with the slave operation sub-module 122 to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122.

In this implementation, the n-ary tree structure may also be a ternary tree structure or the like, where n is a positive integer greater than or equal to 2. The number of n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure may be set by those skilled in the art as needed, and the disclosure is not limited thereto.

In one possible implementation, the operation domain may also include a read-in amount or a memory address of the read-in amount. The control module 11 is further configured to obtain a read amount, and obtain a plurality of data to be calculated according to the read amount. The data volume of the plurality of data to be operated can be smaller than or equal to the read-in volume.

In this implementation, the read-in amount may be a data amount of the acquired plurality of data to be operated on, and may be a size of the acquired data to be operated on. When the operation field directly contains a specific numerical value of the read amount, the numerical value may be determined as the read amount. When the memory address of the read amount is included in the operation field, the read amount can be acquired from the memory address.

In one possible implementation manner, when the read-in amount is not included in the operation domain, the plurality of data to be operated may be acquired according to a preset default read-in amount. The acquired data amount of the plurality of data to be operated can be smaller than or equal to the default read-in amount.

By the mode, the data size and the size of the data to be operated can be limited, the accuracy of the operation result is ensured, and the device can execute the activation instruction.

In one possible implementation, as shown in fig. 2 a-2 f, the apparatus may further include a storage module 13. The storage module 13 is used for storing data to be operated. The storage module 13 may also be used to store an activation table and a constant table.

In this implementation, the storage module may include a memory, such as one or more of a cache and a register, and the cache may include a scratch pad cache. The data to be operated, the activation table and the constant table may be stored in the cache and/or the register of the storage module as needed, which is not limited by the present disclosure.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112, and a queue storage sub-module 113.

The instruction storage submodule 111 is used for storing an activation instruction.

The instruction processing sub-module 112 is configured to parse the activation instruction to obtain an operation code and an operation domain of the activation instruction.

The queue storage submodule 113 is configured to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are sequentially arranged according to an execution order, and the plurality of instructions to be executed include an activation instruction.

In this implementation manner, the execution order of the multiple instructions to be executed may be arranged according to the receiving time, the priority level, and the like of the instructions to be executed to obtain an instruction queue, so that the multiple instructions to be executed are sequentially executed according to the instruction queue.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may further include a dependency processing sub-module 114.

The dependency relationship processing submodule 117 is configured to, when it is determined that a first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, cache the first to-be-executed instruction in the instruction storage submodule 114, and after the zeroth to-be-executed instruction is executed, extract the first to-be-executed instruction from the instruction storage submodule 114 and send the first to-be-executed instruction to the operation module 12.

The method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area. On the contrary, there is no association relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, which may be that there is no overlapping area between the first storage address interval and the zeroth storage address interval.

By the method, according to the dependency relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, the subsequent first to-be-executed instruction is executed after the execution of the previous zeroth to-be-executed instruction is finished, and the accuracy of the operation result is ensured

In one possible implementation, the instruction format of the activation instruction may be:

active dst src0active_table const_table size

active is the operation code of the active instruction, dst, src0, active _ table, const _ table, and size are the operation domain of the active instruction. Wherein dst is a target address, src0 is a data address to be calculated, active _ table is an active table address, const _ table is a constant table address, and size is a read-in amount.

In one possible implementation, the instruction format of the activation instruction may also be:

active dst src0size

where active is the operation code of the activate instruction, dst, src0, and size are the operation domains of the activate instruction. Wherein dst is the target address, src0 is the data address to be calculated, and size is the read-in amount.

It should be understood that the position of the operation code of the activation instruction, the operation code in the instruction format, and the operation field may be set as needed by those skilled in the art, and the present disclosure does not limit this.

In one possible implementation manner, the apparatus may be disposed in one or more of a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and an embedded Neural Network Processor (NPU).

It should be noted that, although the activation instruction processing device is described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application example

An application example according to the embodiment of the present disclosure is given below in conjunction with "performing activation operation with an activation instruction processing apparatus" as one exemplary application scenario to facilitate understanding of the flow of activating the instruction processing apparatus. It is understood by those skilled in the art that the following application examples are merely for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be construed as limiting the embodiments of the present disclosure

Fig. 3 shows a schematic diagram of an application scenario of an activation instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3, the process of processing the activation instruction by the activation instruction processing means is as follows:

in example 1, the control module 11 analyzes the acquired activation instruction 1 (for example, the activation instruction 1 is active 50010020030064), and obtains an operation code and an operation domain of the activation instruction 1. The operation code of the activate instruction 1 is active, the target address is 500, the address of the data to be calculated is 100, the address of the activate table is 200, the address of the constant table is 300, and the read-in amount is 64. The control module 11 acquires data to be operated with a data amount of 64 (read amount) from the data address 100 to be operated, acquires an active table from the active table address 200, and acquires a constant table from the constant table address 300. The operation module 12 performs activation operation on the data to be operated according to the activation table and the constant table to obtain an operation result, and stores the operation result in the target address 500.

Example 2 differs from example 1 in that the activation instruction 1 is active 50010064, and assuming that activation operation needs to be performed according to the activation parameter table, the control module 11 needs to acquire the activation parameter table (see the above description for a specific implementation process).

The working process of the above modules can refer to the above related description.

Therefore, the activation instruction processing device can efficiently and quickly process the activation instruction, and realize efficient and quick processing of activation operation.

The present disclosure provides a machine learning arithmetic device, which may include one or more of the above-described activation instruction processing devices, and is configured to acquire data to be operated and control information from other processing devices, and perform a specified machine learning operation. The machine learning arithmetic device can obtain an activation instruction from other machine learning arithmetic devices or non-machine learning arithmetic devices, and transmit an execution result to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one activation command processing device is included, the activation command processing devices can be linked and transmit data through a specific structure, for example, a PCIE bus is used for interconnection and data transmission, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DDR4 controllers therein, where 64bit is used for data transmission and 8bit is used for ECC check in the 72-bit DDR4 controller. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600 MB/s.

In one embodiment, each group 393 of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transmission between the machine learning chip 389 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to a machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operation states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 shows a flow diagram of an activate instruction processing method according to an embodiment of the present disclosure. As shown in fig. 6, the method is applied to the above-described activation instruction processing apparatus, and includes step S51 and step S52.

In step S51, the control module is used to analyze the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction, and obtain data to be operated and a target address required for executing the activation instruction according to the operation code and the operation domain. The operation code is used for indicating that the operation performed on the data by the activation instruction is activation operation, and the operation domain comprises a data address to be operated and a target address.

In step S52, the operation module performs an activation operation on the data to be operated to obtain an operation result, and stores the operation result in the target address.

In one possible implementation, the method may further include:

acquiring an activation parameter table according to the operation code and/or the operation domain;

the method for activating and operating the data to be operated by using the operation module to obtain an operation result comprises the following steps:

performing activation operation on the data to be operated according to the activation parameter table to obtain an operation result,

In a possible implementation manner, performing activation operation on data to be operated by using an operation module to obtain an operation result may include: and performing activation operation on the data to be operated by using a plurality of activation operators.

In one possible implementation, the arithmetic module may include a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the master arithmetic sub-module may include a plurality of active operators,

the activating operation is performed on the data to be operated by using the operation module to obtain an operation result, and the activating operation may include:

and performing activation operation on the data to be operated by using a plurality of activation operators in the main operation sub-module to obtain an operation result, and storing the operation result into a target address.

In one possible implementation, the operation domain may also include a read-in amount or a memory address of the read-in amount. The obtaining, according to the operation code and the operation domain, the data to be operated, the activation table, the constant table, and the target address, which are required for executing the activation instruction, may include: and acquiring the read amount, and acquiring a plurality of data to be calculated according to the read amount.

In one possible implementation, the method may further include: and storing the data to be operated.

In a possible implementation manner, analyzing the acquired activation instruction to obtain an operation code and an operation domain of the activation instruction may include:

storing the activation instruction;

analyzing the activation instruction to obtain an operation code and an operation domain of the activation instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise activation instructions.

In one possible implementation, the method may further include: when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions has an association relation with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the execution of the zeroth to-be-executed instruction is finished, controlling the execution of the first to-be-executed instruction,

the method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps:

the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area.

In one possible implementation, the activation function utilized by the activation operation may include at least one of:

a linear rectification function, an S-shaped growth curve function, a hyperbolic tangent function, a leaky linear rectification function, a maximum function, and a power function.

It should be noted that, although the activation instruction processing method is described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

The method for processing the activation instruction provided by the embodiment of the disclosure has the advantages of wide application range, high processing efficiency and high processing speed for the activation instruction, and high processing efficiency and high processing speed for performing activation operation.

A1, an activation instruction processing apparatus, comprising:

A2, the device of claim A1,

the control module is further used for acquiring an activation parameter table according to the operation code and/or the operation domain;

the operation module is also used for performing activation operation on the data to be operated according to the activation parameter table to obtain an operation result,

wherein the activation parameter table includes an activation table and a constant table.

A3, the device according to claim A1, wherein the operation module comprises:

and the plurality of activation calculators are used for performing activation calculation on the data to be calculated.

A4, the device of claim A3, wherein the arithmetic module comprises a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the master arithmetic sub-module comprises the plurality of activation operators,

and the main operation sub-module is used for performing activation operation on the data to be operated by using the plurality of activation operators to obtain an operation result, and storing the operation result into the target address.

A5, the device according to claim A1, wherein the operation domain includes a read-in amount or a storage address of the read-in amount,

the control module is further configured to obtain the read-in amount and obtain the data to be calculated according to the read-in amount.

A6, the device of claim a1, further comprising:

and the storage module is used for storing the data to be operated.

A7, the device of claim a1, wherein the control module comprises:

the instruction storage submodule is used for storing the activation instruction;

the instruction processing submodule is used for analyzing the activation instruction to obtain an operation code and an operation domain of the activation instruction;

and the queue storage submodule is used for storing an instruction queue, the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the activation instruction.

A8, the device of claim a7, wherein the control module further comprises:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the fact that the first instruction to be executed in the plurality of instructions to be executed is associated with a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the operation module,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

A9, the device according to any one of claims A1 to A8, wherein the activation function utilized by the activation operation includes at least one of:

A10, a machine learning arithmetic device, comprising:

one or more active instruction processing devices as claimed in any one of claims a1-a9, configured to obtain data and control information to be operated on from other processing devices, execute a specified machine learning operation, and transmit the execution result to other processing devices through an I/O interface;

A11, wherein the combination processing device comprises:

the machine learning computing device, the universal interconnect interface, and the other processing devices of claim a 10;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

A12, a machine learning chip, comprising:

the machine learning computing device of claim a10 or the combined processing device of claim a 11.

A13, an electronic device, comprising:

the machine learning chip of claim a 12.

A14, a board card, characterized in that, the board card includes: a memory device, an interface device and a control device and a machine learning chip as claimed in claim a 12;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

A15, an activation instruction processing method, wherein the method is applied to an activation instruction processing device, and the method comprises:

analyzing the acquired activation instruction by using a control module to obtain an operation code and an operation domain of the activation instruction, and acquiring data to be operated and a target address required by executing the activation instruction according to the operation code and the operation domain;

activating operation is carried out on the data to be operated by using an operation module to obtain an operation result, the operation result is stored in the target address,

A16, the method of claim a15, wherein the method further comprises:

A17, the method according to claim A15, wherein the activating operation is performed on the data to be operated by using an operation module to obtain an operation result, the method comprises:

and performing activation operation on the data to be operated by using a plurality of activation operators.

A18, the method according to claim A15, wherein the operation module comprises a master operation sub-module and a plurality of slave operation sub-modules, the master operation sub-module comprises the plurality of activation operators,

and performing activation operation on the data to be operated by using a plurality of activation operators in the main operation sub-module to obtain an operation result, and storing the operation result into the target address.

A19, the method according to claim A15, wherein the operation domain further comprises a read-in amount or a storage address of the read-in amount,

acquiring data to be operated, an activation table, a constant table and a target address required for executing the activation instruction according to the operation code and the operation domain, wherein the method comprises the following steps:

and acquiring the read-in amount, and acquiring the data to be calculated according to the read-in amount.

A20, the method of claim a15, wherein the method further comprises:

and storing the data to be operated.

The method of claim a15, as denoted by a21, in which the parsing the acquired activation instruction by the control module to obtain the operation code and the operation domain of the activation instruction includes:

storing the activation instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the activation instruction.

A22, the method of claim a21, wherein the method further comprises:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction,

A23, the method according to any of claims a15 to a22, wherein the activation functions utilized by the activation operations include at least one of:

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present disclosure, it should be understood that the disclosed system and apparatus may be implemented in other ways. For example, the above-described embodiments of systems and apparatuses are merely illustrative, and for example, a division of a device, an apparatus, and a module is merely a logical division, and an actual implementation may have another division, for example, a plurality of modules may be combined or integrated into another system or apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices, apparatuses or modules, and may be an electrical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present disclosure may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a form of hardware or a form of a software program module.

The integrated modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An activation instruction processing apparatus, characterized in that the apparatus comprises:

2. The apparatus of claim 1,

3. The apparatus of claim 1, wherein the computing module comprises:

4. The apparatus of claim 3, wherein the arithmetic module comprises a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the master arithmetic sub-module comprising the plurality of active operators,

5. A machine learning arithmetic device, the device comprising:

one or more activated instruction processing devices as claimed in any one of claims 1 to 4, configured to obtain data to be operated and control information from other processing devices, perform specified machine learning operation, and transmit the execution result to other processing devices through the I/O interface;

6. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 5;

7. A machine learning chip, the machine learning chip comprising:

the machine learning arithmetic device according to claim 5 or the combined processing device according to claim 6.

8. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 7.

9. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface apparatus and a control device and a machine learning chip according to claim 7;

the storage device is used for storing data;

10. An active instruction processing method, applied to an active instruction processing apparatus, includes: