CN111044887A

CN111044887A - Method for generating test vectors of DDR2/3PHY BIST command channel

Info

Publication number: CN111044887A
Application number: CN201911252694.7A
Authority: CN
Inventors: 马杰; 乐立鹏; 张建军; 马城城; 闫昕; 刘亚鹏
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2019-12-09
Filing date: 2019-12-09
Publication date: 2020-04-21
Anticipated expiration: 2039-12-09
Also published as: CN111044887B

Abstract

The invention discloses a method for generating a DDR2/3PHY BIST command channel test vector, which comprises the following steps: (1) selecting an LFSR structure, and driving the LFSR structure to generate a pseudo-random number by using a low-frequency clock; (2) selecting a shift register value in an LFSR structure as test data; (3) and coding the test data to construct a final test vector. The invention has simple structure and easy realization, the generated test vector can fully test the anti-crosstalk and driving capability of the channel, and the BIST operation frequency and the power consumption are reduced under the condition of meeting the test requirement.

Description

Method for generating test vectors of DDR2/3PHY BIST command channel

Technical Field

The invention relates to the technical field of integrated circuit testability design, in particular to a method for generating a DDR2/3PHY BIST command channel test vector.

Background

The purpose of integrated circuit testing is to detect defects generated during manufacturing, and built-in self test (BIST) is an important method for design for testability. The BIST test principle is that test vectors are generated inside a circuit, and test results are analyzed and judged. Pseudo-random test generation is a popular test generation method in BIST technology.

And the DDR2/3PHY command channel test vector is transmitted to IO through a command transmitting channel and returns to the BIST through a special command receiving channel, and the returned result is compared with the initial test vector to complete the BIST function. The whole process only sends and receives the test vector, and the reliability and the stability of channel transmission are detected. The Linear Feedback Shift Register (LFSR) structure is a popular generation method for pseudo-random test data due to low hardware overhead and compact structure. In the prior art, a Linear Feedback Shift Register (LFSR) is generally used to generate a test vector, but the IO driving capability cannot be checked for crosstalk between signals and signal inversion.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the method can simulate the conditions of signal inversion, signal crosstalk and the like, and can specifically test the stability of the PHY command channel, reduce the LFSR clock frequency and reduce the BIST operation power consumption.

The technical solution of the invention is as follows:

a DDR2/3PHY BIST command channel test vector generation method comprises the following steps:

(1) selecting an LFSR structure, and driving the LFSR structure to generate a pseudo-random number by using a low-frequency clock;

(2) selecting a shift register value in an LFSR structure as test data;

(3) and coding the test data to construct a final test vector.

In the step (1), the number of shift registers in the LFSR structure is n +1, where n is determined by the command channel bit width.

n is determined as follows:

the command channel signals are divided into two groups according to functions: one group is address signals with a bit width of M; the other group is signals except addresses, and the signals are N bits in total;

n is related to whether the register is multiplexed in the design, and if the register is selected, N is max (M, N); if not multiplexed, N is M + N.

In the step (2), the values of n shift registers are selected from n +1 shift registers of the LFSR structure and are allocated to the command channel signal as the test data.

The specific way to select the values of the n shift registers to assign to the command channel signals as test data is as follows:

if N is max (M, N), the values of N shift registers are randomly distributed to one group with the largest signal bit width in two groups of command channel signals, and then the values of min (M, N) shift registers are randomly selected from the selected N shift registers and distributed to the other group of command channel signals;

if N is M + N, the values of N shift registers are randomly assigned to all command channel signals.

In the step (3), the test data is encoded by using a 2B/4B encoding method to construct a final test vector.

The manner in which each bit of the command channel signal is 2B/4B encoded is as follows:

source code data	00	01	10	11
					Encoding data	0110	1001	0101	1010

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention codes the value of the LFSR structure shift register and generates a signal with all data in the channel turned over, thereby being capable of testing the anti-crosstalk and IO driving capability of the channel.

(2) The invention utilizes the low-frequency clock to drive the LFSR structure to generate the pseudo-random test data, realizes the high-frequency pseudo-random test vector through 2B/4B coding, and can reduce the LFSR clock frequency and the BIST operation power consumption.

(3) The test vector after the coding of the invention has a characteristic that: each vector has no continuous 3 same values (0 or 1), and the error detector can be constructed at the BIST receiving end according to the characteristic to judge whether the output result is correct or incorrect.

Drawings

FIG. 1 is a flow chart of test vector construction according to the present invention;

FIG. 2 is a diagram of a test vector hardware generation module;

FIG. 3 is a test vector simulation waveform diagram for a code implementation.

Detailed Description

The invention is described in further detail below with reference to the accompanying drawings and specific embodiments:

as shown in fig. 1, the method of the present invention comprises the steps of:

(1) and selecting an LFSR structure, and driving the LFSR structure to generate pseudo random numbers by using a low-frequency clock, wherein the number of shift registers in the LFSR structure is n +1, and n is determined by the bit width of a command channel.

A typical LFSR is feedback connected by n shift registers, several exclusive or gates. Shift registerThe number of registers n is related to the command channel bit width. The feedback coefficient of each register is determined by its primitive polynomial to generate a maximum length sequence. The operating state of an LFSR is close to an exhaustive test vector generator, since it can be any 2 except in the case of a register with all 0 statesⁿ-cycling between 1 different states. In addition, the invention adds the n +1 th register, which can make the rest registers have all 0 states and complement 2 statesⁿSeed state, can be from 2 during testingⁿAnd selecting part of the middle state as a test vector. The LFSR has a simple structure and low hardware overhead.

n is determined as follows:

the command channel signals are divided into two groups according to functions: one group is address signals with a bit width of M; the other group is signals except addresses, such as a bank address signal, a chip select signal CS, a row select RAS, a column select CAS and a WE which share N bits.

The number N of shift registers is related to whether the registers are multiplexed in design, and if the multiplexing registers are selected, N is max (M, N); if not multiplexed, N is M + N.

(2) The shift register values in the LFSR structure are selected as test data.

Selecting values of n shift registers from n +1 shift registers of the LFSR structure to be distributed to command channel signals as test data, and the specific mode is as follows:

if N is max (M, N), the values of the N shift registers are randomly allocated to one of the two groups with the largest number of signals, and then the values of the min (M, N) shift registers are randomly selected from the N registers to be used as the test data of the other group. The multiplexing register reduces the scale of the LFSR register by sacrificing the randomness between signals; if N is M + N, the values of N shift registers are randomly assigned to all command channel signals.

(3) And coding the test data to construct a final test vector.

The invention designs a 2B/4B coding method, and for each bit of command channel signal, the coding method is shown as the following table:

source code data	00	01	10	11
					Encoding data	0110	1001	0101	1010

As known from the encoding method, the 2 nd and 4 th bits in the encoded data can be regarded as the data jump of the 1 st and 3 rd bits respectively, so that the multi-bit command channel can be simultaneously turned over at a certain moment no matter how many source codes exist; moreover, the method can easily obtain that the new test vector formed by encoding does not have continuous 3 same data, and can construct an error detector at the BIST receiving end according to the characteristic to judge whether the result is correct.

Example (b):

in fig. 2, a 16-bit wide address signal is taken as an example, in order to cover all cases (including all 0) of 16-bit address signals as much as possible, a 17-bit linear feedback shift register is selected to generate a random number, an exclusive or gate connected in a feedback manner is an external connection type, in this example, 1 st, 10 th, 16 th, and 17 th bit register external exclusive or gates are used to feed back to a1 st bit register to form an LFSR, and a reset state is a 17 th position 1 and other 16 th positions 0. The output of 16 registers is selected as the input test data of the data encoding module, and the 16 registers can generate the length of 2¹⁶Pseudo-random sequence, with partial sequence selectable according to test coverageThe columns are taken as test vectors. The clock module generates a clock signal clk connected to the shift register and the data encoding module. The test data is processed by the data encoding module to form a final test vector, and part of the output waveforms are shown in fig. 3. Where ck _ gen _ addr is the input clock and A0-A15 is the 16-bit address signal. As can be seen from the waveforms on the graph, the holding time of each address signal is ck _ gen _ addr clock half period; there are 2 consecutive identical values at most, can construct the simple error detector according to this characteristic; all addresses are periodically turned over at a certain moment, so that the channel anti-crosstalk performance and the IO driving capability can be tested. The 2B/4B encoding increases the test vector data frequency and may reduce the BIST clock frequency, thereby reducing power consumption.

Other commands than 16-bit address signals are not logically functionally related to the address signals, and the A [15:0] address signal portion of the test data may be multiplexed. In order to reduce the scale of the shift register and the power consumption and the area of the BIST in the example, other command channels select the test vectors of the multiplexed address signals, and the characteristics of the vectors are similar to those of the address signals.

The invention has simple structure and easy realization, the generated test vector can fully test the anti-crosstalk and driving capability of the channel, the stability of the PHY command channel is tested in a targeted way, the BIST operation frequency is reduced under the condition of meeting the test requirement, and the power consumption is reduced.

The above description is only an exemplary embodiment of the present invention, but the scope of the present invention is not limited thereto.

Claims

1. A DDR2/3PHY BIST command channel test vector generation method is characterized by comprising the following steps:

(2) selecting a shift register value in an LFSR structure as test data;

(3) and coding the test data to construct a final test vector.

2. The method of claim 1, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: in the step (1), the number of shift registers in the LFSR structure is n +1, where n is determined by the command channel bit width.

3. The method of claim 2, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: n is determined as follows:

4. The method of claim 3, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: in the step (2), the values of n shift registers are selected from n +1 shift registers of the LFSR structure and are allocated to the command channel signal as the test data.

5. The method of claim 4, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: the specific way to select the values of the n shift registers to assign to the command channel signals as test data is as follows:

6. The method of claim 1, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: in the step (3), the test data is encoded by using a 2B/4B encoding method to construct a final test vector.

7. The method of claim 6, wherein the DDR2/3PHY BIST command channel test vector generation method comprises: the manner in which each bit of the command channel signal is 2B/4B encoded is as follows:

source code data 00 01 10 11 Encoding data 0110 1001 0101 1010