CN111031011B - Interaction method and device of TCP/IP accelerator - Google Patents
Interaction method and device of TCP/IP accelerator Download PDFInfo
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- CN111031011B CN111031011B CN201911171018.7A CN201911171018A CN111031011B CN 111031011 B CN111031011 B CN 111031011B CN 201911171018 A CN201911171018 A CN 201911171018A CN 111031011 B CN111031011 B CN 111031011B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0823—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
- H04L41/083—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability for increasing network speed
Abstract
The invention provides an interaction method and device of a TCP/IP accelerator, wherein the method comprises the following steps: acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card; distributing an address for target data through software, sending a data writing instruction to a TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card; after the TCP/IP accelerator board processes the target data, a data reading instruction is sent to the TCP/IP accelerator board, the storage information of the data is read from the TCP/IP accelerator board, and the processed target data is read from the TCP/IP accelerator board according to the storage information. By the scheme, the technical problems of low efficiency and more system time consumption existing in the existing data processing only through software are solved, and the technical effects of effectively improving the utilization rate of hardware resources and reducing the system waiting time are achieved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an interaction method and device of a TCP/IP accelerator.
Background
The Internet based on TCP/IP protocol has evolved into a very large computer network with the largest size and the largest number of users and resources, and thus TCP/IP protocol has become the de facto industry standard. However, as web elements are enriched and the number of users increases, the requirements for interaction latency and processing power are also increasing. The existing TCP congestion control algorithm is not suitable for a link with high time delay and high error code, so that a TCP/IP protocol unloading engine accelerator technology is provided, namely, the work of consuming a large amount of resources on an original host processor to process data packets of a multilayer network protocol is transferred to a network card, so that the utilization rate of a host CPU is effectively reduced, and the transmission efficiency is improved.
The TOE (TCP/IP offload engine) network card can be divided into full offload and data path offload according to the offload degree, wherein full offload refers to offloading TCP/IP protocol processing to a special processing device for processing, and data path offload refers to offloading receiving and sending TCP/IP data to a special processor for processing, and meanwhile, handing connection management to a host CPU for processing.
The existing TCP/IP accelerator analyzes and processes received data mostly through software, and occupies a large amount of resources in the process of processing and transmitting the data on a network, so an effective solution is not provided.
Disclosure of Invention
The embodiment of the invention provides an interaction method and device of a TCP/IP accelerator, which are used for effectively improving the utilization rate of hardware resources and further reducing the waiting time of a system.
In one aspect, an interactive method of a TCP/IP accelerator is provided, which includes:
acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card;
distributing an address for target data through software, sending a write data instruction to the TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card;
after the TCP/IP accelerator board card processes the target data, sending a read data instruction to the TCP/IP accelerator board card, reading storage information of the data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
In one embodiment, the stored information includes at least one of: data address, data length, and number.
In one embodiment, reading data from the TCP/IP accelerator board according to the storage information includes:
and reading data from the DDR module of the TCP/IP accelerator board card according to the storage information.
In one embodiment, after sending a read data instruction to the TCP/IP accelerator board, reading storage information of data from the TCP/IP accelerator board, and reading data from the TCP/IP accelerator board according to the storage information, the method further includes:
and after the preset time for establishing the TCP connection, the TCP/IP accelerator board card automatically disconnects the TCP connection.
In one embodiment, acquiring address information of a target TCP/IP accelerator board, and sending a communication instruction carrying the address information to a network card to establish a TCP connection with the TCP/IP accelerator board includes:
acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information;
sending a first control instruction to the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the control instruction carries a first identifier and an IP address;
the target TCP/IP accelerator board card reads information from the PIO address according to the first identifier and writes a first reply identifier through the PIO;
after receiving the first reply identifier, writing a second control instruction into the PIO address through PIO, wherein the second control instruction carries a second identifier, an IP address and port information;
the target TCP/IP accelerator board card reads corresponding information according to the second identifier and sends a second reply identifier;
and after receiving the second reply identifier, writing an IP address through PIO to complete the establishment of the TCP connection.
In one embodiment, an address is allocated to target data through software, a data writing instruction is sent to the TCP/IP accelerator board card, and the target data is written into the TCP/IP accelerator board card;
writing the target data into the target TCP/IP accelerator board card through DMA mode reading and writing, wherein the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board card;
writing a third control instruction into the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the third control instruction is data address information, and storing the data address information into a write data information address opened by the target TCP/IP accelerator board card;
writing a fourth control instruction into the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the fourth control instruction carries: updating the flag bit, the length of the target data and the handle information;
and the target TCP/IP accelerator board card extracts and processes the target data according to the fourth control instruction.
In one embodiment, sending a read data instruction to the TCP/IP accelerator board, reading storage information of data from the TCP/IP accelerator board, and reading data from the TCP/IP accelerator board according to the storage information includes:
reading the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through PIO mode reading and writing;
reading the third control instruction from a second read data information address opened by the target TCP/IP accelerator board card through PIO mode reading and writing;
reading data from the pre-opened data storage address of the target TCP/IP accelerator board card through DMA mode reading and writing according to the information carried in the fourth control instruction and the third control instruction;
and writing a fifth control instruction into the first read data information address through PIO mode reading and writing, wherein the fifth control instruction carries an update flag bit.
In one embodiment, the third, fourth, and fifth control instructions are 32-bit control instructions.
In another aspect, an interactive device of a TCP/IP accelerator is provided, which includes:
the acquisition module is used for acquiring address information of a target TCP/IP accelerator board card and sending a communication instruction carrying the address information to a network card so as to establish TCP connection with the TCP/IP accelerator board card;
the write-in module is used for distributing an address for target data through software, sending a write-in data instruction to the TCP/IP accelerator board card and writing the target data into the TCP/IP accelerator board card;
and the reading module is used for sending a read data instruction to the TCP/IP accelerator board card after the TCP/IP accelerator board card processes the target data, reading storage information of the data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
In one embodiment, the obtaining module comprises:
the acquisition unit is used for acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information;
the sending unit is used for sending a first control instruction to the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the control instruction carries a first identifier and an IP address;
a first writing unit, configured to write a second control instruction to the PIO address through the PIO after receiving a first reply identifier written by the PIO after the target TCP/IP accelerator board reads information from the PIO address according to the first identifier, where the second control instruction carries a second identifier, an IP address, and port information;
and the second writing unit is used for writing an IP address through PIO after receiving a second reply identifier sent by the target TCP/IP accelerator board card after reading corresponding information according to the second identifier, so as to complete the establishment of TCP connection.
In one embodiment, the write module includes:
a third writing unit, configured to write the target data into the target TCP/IP accelerator board through DMA mode read-write, where the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board;
a fourth writing unit, configured to write a third control instruction to the target TCP/IP accelerator board through PIO mode read-write, where the third control instruction is data address information, and store the data address information in a write data information address created by the target TCP/IP accelerator board;
a fifth writing unit, configured to write a fourth control instruction into the target TCP/IP accelerator board through PIO mode read-write, where the fourth control instruction carries: and updating a zone bit, the length of target data and handle information, wherein the fourth control instruction is used for the target TCP/IP accelerator board card to extract and process the target data.
In one embodiment, the reading module comprises:
the first reading unit is used for reading and writing the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through a PIO mode;
the second reading unit is used for reading and writing the third control instruction from a second read data information address opened up by the target TCP/IP accelerator board card through a PIO mode;
a third reading unit, configured to read and write data from the pre-opened data storage address of the target TCP/IP accelerator board in a DMA mode according to information carried in the fourth control instruction and the third control instruction;
and a sixth writing unit, configured to write a fifth control instruction into the first read data information address through PIO mode read-write, where the fifth control instruction carries an update flag bit.
In yet another aspect, a network device is provided, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.
In one aspect, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method.
In the above example, a method is provided for establishing a TCP connection between a host and a TCP/IP accelerator, transporting data from the host to a TCP/IP accelerator board, waiting for processing by the accelerator board, and simultaneously reading data information from the accelerator board, that is, data processing work of a part of software is shared by hardware.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a method flow diagram of a method of interaction of a TCP/IP accelerator according to an embodiment of the invention;
FIG. 2 is a flow diagram of a method of TCP/IP offload according to an embodiment of the invention;
fig. 3 is a block diagram of an interactive apparatus of a TCP/IP accelerator according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
In view of the fact that the existing TCP/IP accelerator mostly analyzes and processes received data through software and occupies a large amount of resources in the process of processing and transmitting data on a network, the present embodiment provides an interactive method of a TCP/IP accelerator, which shares a part of data processing work through a TCP/IP accelerator board card to reduce the waiting time of a system.
As shown in fig. 1, in this example, an interactive method of a TCP/IP accelerator is provided, which may include the following steps:
step 101: acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card;
step 102: distributing an address for target data through software, sending a write data instruction to the TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card;
step 103: after the TCP/IP accelerator board card processes the target data, sending a read data instruction to the TCP/IP accelerator board card, reading storage information of the data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
In the above example, a method is provided for establishing a TCP connection between a host and a TCP/IP accelerator, transporting data from the host to a TCP/IP accelerator board, waiting for processing by the accelerator board, and simultaneously reading data information from the accelerator board, that is, data processing work of a part of software is shared by hardware.
The stored information may include, but is not limited to, at least one of: data address, data length, and number.
Specifically, in the implementation process, the reading of the data from the TCP/IP accelerator board according to the storage information may be reading the data from a DDR module of the TCP/IP accelerator board according to the storage information.
Specifically, after a read data instruction is sent to the TCP/IP accelerator board, storage information of data is read from the TCP/IP accelerator board, and after the data is read from the TCP/IP accelerator board according to the storage information, the TCP/IP accelerator board may automatically disconnect the TCP connection after a predetermined time period for establishing the TCP connection.
Specifically describing the step 101-103 as follows, the step 101 obtaining address information of the target TCP/IP accelerator board, and sending a communication instruction carrying the address information to the network card to establish a TCP connection with the TCP/IP accelerator board may specifically include:
s1: acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information;
s2: sending a first control instruction to the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the control instruction carries a first identifier and an IP address;
s3: the target TCP/IP accelerator board card reads information from the PIO address according to the first identifier and writes a first reply identifier through the PIO;
s4: after receiving the first reply identifier, writing a second control instruction into the PIO address through PIO, wherein the second control instruction carries a second identifier, an IP address and port information;
s5: the target TCP/IP accelerator board card reads corresponding information according to the second identifier and sends a second reply identifier;
s6: and after receiving the second reply identifier, writing an IP address through PIO to complete the establishment of the TCP connection.
In the step 102, allocating an address to the target data by software and sending a write data instruction to the TCP/IP accelerator board, and writing the target data into the TCP/IP accelerator board may specifically include:
s1: writing the target data into the target TCP/IP accelerator board card through DMA mode reading and writing, wherein the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board card;
s2: writing a third control instruction into the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the third control instruction is data address information, and storing the data address information into a write data information address opened by the target TCP/IP accelerator board card;
s3: writing a fourth control instruction into the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the fourth control instruction carries: updating the flag bit, the length of the target data and the handle information;
s4: and the target TCP/IP accelerator board card extracts and processes the target data according to the fourth control instruction.
The step 103 of sending a read data instruction to the TCP/IP accelerator board, reading storage information of data from the TCP/IP accelerator board, and reading data from the TCP/IP accelerator board according to the storage information may specifically include:
s1: reading the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through PIO mode reading and writing;
s2: reading the third control instruction from a second read data information address opened by the target TCP/IP accelerator board card through PIO mode reading and writing;
s3: reading data from the pre-opened data storage address of the target TCP/IP accelerator board card through DMA mode reading and writing according to the information carried in the fourth control instruction and the third control instruction;
s4: and writing a fifth control instruction into the first read data information address through PIO mode reading and writing, wherein the fifth control instruction carries an update flag bit.
The first control instruction, the second control instruction, the third control instruction, the fourth control instruction, and the fifth control instruction described above may all be 32-bit control instructions. Because the provided overall instruction length can be fixed to be 32 bytes, the adoption of the reduced instruction set can effectively reduce the complexity of hardware design and improve the instruction execution speed, thereby improving the speed of a machine.
Specifically, the upper 8 bits of the first control instruction are identifiers, the last 24 bits are the first 24 bits of the ip address, the upper 8 bits of the second control instruction are identifiers, the middle 8 bits are the lower 8 bits of the ip address, and the last 16 bits are port information. The third control instruction is 32-bit data address information, the upper 8 bits of the fourth control instruction are update flag bits, so that the hardware can conveniently judge whether the data is new data according to the flag bits, the middle 16 bits are data length to be written, the lower 8 bits are handle (handle) information, the upper 8 bits of the fifth control instruction are update flag bits for the board card to judge as a new group of data, and the remaining 24 bits are 0.
The above method is described below with reference to a specific example, however, it should be noted that the specific example is only for better describing the present application and is not to be construed as limiting the present application.
In this example, an interactive protocol for a TCP/IP accelerator is proposed to improve the efficiency of the TCP/IP accelerator in processing data, and specifically, a communication-data transmission-data read-back operation between a host and the TCP/IP accelerator is optimized through the protocol to save the time for transmitting communication between network data and the TCP/IP accelerator. The overall instruction length provided by the protocol can be fixed to be 32 bytes, and the simplified instruction set can effectively reduce the complexity of hardware design and improve the instruction execution speed, thereby improving the speed of a machine. And the expandability and applicability of the protocol can be further considered.
In the implementation process, the following steps can be included:
s1: the upper computer acquires IP and port information of a target TCP/IP accelerator board card, then sends a communication instruction to the network card and establishes TCP connection;
s2: the upper computer distributes an address for each data to be written through software, sends a data writing instruction to the TCP/IP accelerator board card, and writes the data to be sent and data information into the board card;
s3: and the upper computer sends a data reading instruction to the TCP/IP accelerator board card, reads the data address, the data length and the serial number stored in the storage module of the board card from the board card, and reads data from the DDR module of the board card to the upper computer according to the information.
S4: after the upper computer establishes TCP connection with the TCP/IP accelerator board card, the board card automatically disconnects the TCP connection after a period of time.
In the above example, a protocol is provided in which the host establishes a TCP connection with the TCP/IP accelerator, carries data from the host side to the accelerator, waits for the accelerator to process, and can read data information from the accelerator. Through a special flow and by adopting a mode of fixing the instruction length, the waiting time of the system is effectively reduced, and the utilization rate of hardware resources is improved.
That is, an interactive protocol of a TCP/IP accelerator is provided, so that part of the work of software data processing is shared by hardware, and an efficient implementation of the protocol is achieved by way of cooperative processing, which is described in a specific example, the interactive protocol may include the following steps:
step 1: as shown in fig. 2, the upper computer obtains the IP address and port information of the target TCP/IP accelerator board, and then reads and writes the configuration information through a PIO (Programmed Input-Output) mode of the PCIE. The method comprises the following specific steps:
s1-1: and sending a 32-bit instruction to the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the upper 8 bits of the instruction are identifiers, and the rear 24 bits are the first 24 bits of the IP address.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK）
#31- -control field (31-24) - -23- -data field (23-0) - -0
S1-2: and the TCP/IP accelerator board card reads information from the PIO address according to the identifier sent by S1-1 and writes a reply identifier through the PIO.
The implementation function may be:
PCIE_Read32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_BUTTON_ADDR,&status）
s1-3: and after receiving the reply identifier, the upper computer writes a 32-bit instruction into the same address through the PIO again, wherein the upper 8 bits of the instruction are the identifier, the middle 8 bits are the lower 8 bits of the ip address, and the rear 16 bits are port information.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -control field (31-24) - -23- -data field (23-16) - -15- -data field 2(15-0) - -0
S1-4: and the TCP/IP accelerator board card reads corresponding information according to the identifier in the S1-3 and sends back a reply identifier.
The implementation function may be:
PCIE_Read32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_BUTTON_ADDR,&Status)
s1-5: and after receiving the reply identifier, the upper computer writes the ip _ id through the PIO.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -control field (31-24) - -23- -reserved field (23-8) - -7- -data information field (7-0) - -0
S1-6: after receiving the information, the TCP/IP accelerator board completes the work of establishing TCP connection.
The implementation function may be:
PCIE_Read32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_BUTTON_ADDR,&Status)
step 2: as shown in fig. 2, the upper computer acquires data to be transmitted, and assigns an address to each set of data to be written according to software. The data writing command is read and written through a PIO (Programmed Input-Output) mode of the PCIE, and the data is written through a dma (direct Memory access) mode of the PCIE. The method comprises the following specific steps:
s2-1: and the upper computer writes data to be transmitted into the TCP/IP accelerator board card through DMA mode reading and writing, and the data is stored in a data storage address specially opened in the TCP/IP accelerator board card.
The implementation function may be:
PCIE_DmaWrite(hPCIe,LocalAddr,pWrite,nTestSize)
the written address is determined by hardware, the address space of the hardware and the mode of a configuration file are provided for the upper computer, and the upper computer allocates an address for each data to be written.
S2-2: and the upper computer writes a 32-bit instruction into the board card through PIO mode reading and writing, wherein the instruction content is 32-bit data address information and is stored into a write data information address opened up by the accelerator board card.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -data Address information- - #0
S2-3: the upper computer writes a 32-bit instruction into the board card through PIO mode reading and writing, wherein the upper 8 bits of the instruction are updating flag bits, hardware can conveniently judge whether the instruction is new data or not according to the flag bits, the middle 16 bits are data length to be written, and the lower 8 bits are handle information for distinguishing different data packets.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -update flag (31-24) - -23- -data length (23-8) - -7- -handle (7-0) - -0
S2-4: and the hardware acceleration board card performs data extraction and processing on the information.
And step 3: and the upper computer reads and writes information such as the length, address, handle (handle) and the like of data in the TCP/IP accelerator board card through a PIO (Programmed Input-Output) mode of PCIE. And reading and writing the data according to the information in a DMA (direct Memory access) mode of the PCIE.
The method comprises the following specific steps:
s3-1: and the upper computer reads a 32-bit instruction from a read data information address 1 opened from the TCP/IP accelerator board card through PIO mode reading and writing. The high 8 bits of the instruction are update marks for the upper computer end to judge whether the instruction is a new group of data, the middle 16 bits are length information of data in the TCP/IP accelerator board card, and the low 8 bits are handle information for distinguishing different data packets.
The implementation function may be:
PCIE_Read32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -update flag (31-24) - -23- -data length (23-8) - -7- -handle (7-0) - -0
S3-2: and the upper computer reads a 32-bit instruction from a read data information address 2 opened from the TCP/IP accelerator board card through PIO mode reading and writing, wherein the instruction is 32-bit address information.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -data Address information- - #0
S3-3: and the upper computer reads and writes the data from the read data address of the board card through the DMA mode according to the information read in the two steps.
The implementation function may be:
PCIE_DmaRead(hPCIe,LocalAddr,pRead,nTestSize)
s3-4: and the upper computer writes a 32-bit instruction into the read data information address 1 through PIO mode reading and writing, wherein the upper 8 bits of the instruction are update flag bits for the board card to judge as a new group of data, and the rest 24 positions are 0.
The implementation function may be:
PCIE_Write32(hPCIe,DEMO_PCIE_USER_BAR,DEMO_PCIE_IO_LED_ADDR,(DWORD)MASK)
#31- -the update flag bit (31-24) - -23- -is set to 0- -0
And 4, step 4: after the upper computer establishes TCP connection with the TCP/IP accelerator board card, the board card automatically disconnects the TCP connection after a period of time, and the specific time length can be defined by the upper computer. The accelerator can be prevented from being occupied for a long time and hardware resources can be prevented from being wasted by automatically disconnecting the TCP connection.
In the implementation process, the system may self-determine a protocol order according to a protocol, for example, after the accelerator board card in step 1 is executed to establish the TCP connection, step 2 or step 3 may be executed first according to a requirement of a user, the order of S2-2 and S2-3 in step 2 may be set according to an actual requirement, or may be executed in parallel, and the order of S3-1 and S3-2 in step 3 may be set according to an actual requirement, or may be executed in parallel.
By the scheme, the running speed of the software end program can be increased, and the hardware waiting time is reduced, so that the processing performance of the TCP/IP accelerator can be improved. Specifically, an interactive protocol for a TCP/IP accelerator is provided, data communication delay between a host and the TCP/IP accelerator is reduced, unnecessary link delay is effectively avoided, the adopted instruction length is fixed to be 32 bits, the complexity of hardware design is effectively reduced by adopting the simplified instruction set, the instruction execution speed is improved, and therefore the speed of a machine is improved.
In the above example, to achieve the contemplated migration and eliminate the problems posed by the host processing data, TCP processing from the host system on the accelerator is reallocated using the transmission control protocol, the accelerator may have appropriate software for handling TCP processing, thereby allowing the reallocation of host system processing resources to application processing.
Based on the same inventive concept, the embodiment of the present invention further provides an interactive apparatus of a TCP/IP accelerator, as described in the following embodiments. Because the principle of the interactive device of the TCP/IP accelerator for solving the problem is similar to the interactive method of the TCP/IP accelerator, the implementation of the interactive device of the TCP/IP accelerator can refer to the implementation of the interactive method of the TCP/IP accelerator, and repeated details are not described again. As used hereinafter, the term "unit" or "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated. Fig. 3 is a block diagram of an interaction device of a TCP/IP accelerator according to an embodiment of the present invention, and as shown in fig. 3, the interaction device may include: an acquisition module 301, a write module 302, and a read module 303, the structure of which is described below.
An obtaining module 301, configured to obtain address information of a target TCP/IP accelerator board, and send a communication instruction carrying the address information to a network card to establish a TCP connection with the TCP/IP accelerator board;
a write-in module 302, configured to allocate an address to target data through software, send a write-in data instruction to the TCP/IP accelerator board, and write the target data into the TCP/IP accelerator board;
the reading module 303 is configured to send a read data instruction to the TCP/IP accelerator board after the TCP/IP accelerator board processes the target data, read storage information of the data from the TCP/IP accelerator board, and read the processed target data from the TCP/IP accelerator board according to the storage information.
In one embodiment, the obtaining module 301 may include: the acquisition unit is used for acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information; the sending unit is used for sending a first control instruction to the target TCP/IP accelerator board card through PIO mode reading and writing, wherein the control instruction carries a first identifier and an IP address; a first writing unit, configured to write a second control instruction to the PIO address through the PIO after receiving a first reply identifier written by the PIO after the target TCP/IP accelerator board reads information from the PIO address according to the first identifier, where the second control instruction carries a second identifier, an IP address, and port information; and the second writing unit is used for writing an IP address through PIO after receiving a second reply identifier sent by the target TCP/IP accelerator board card after reading corresponding information according to the second identifier, so as to complete the establishment of TCP connection.
In one embodiment, the writing module 302 may include: a third writing unit, configured to write the target data into the target TCP/IP accelerator board through DMA mode read-write, where the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board; a fourth writing unit, configured to write a third control instruction to the target TCP/IP accelerator board through PIO mode read-write, where the third control instruction is data address information, and store the data address information in a write data information address created by the target TCP/IP accelerator board; a fifth writing unit, configured to write a fourth control instruction into the target TCP/IP accelerator board through PIO mode read-write, where the fourth control instruction carries: and updating a zone bit, the length of target data and handle information, wherein the fourth control instruction is used for the target TCP/IP accelerator board card to extract and process the target data.
In one embodiment, the reading module 303 may include: the first reading unit is used for reading and writing the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through a PIO mode; the second reading unit is used for reading and writing the third control instruction from a second read data information address opened up by the target TCP/IP accelerator board card through a PIO mode; a third reading unit, configured to read and write data from the read data address of the target TCP/IP accelerator board in a DMA mode according to information carried in the fourth control instruction and the third control instruction; and a sixth writing unit, configured to write a fifth control instruction into the first read data information address through PIO mode read-write, where the fifth control instruction carries an update flag bit.
An embodiment of the present application further provides a specific implementation manner of an electronic device, which is capable of implementing all steps in the interaction method of the TCP/IP accelerator in the foregoing embodiment, where the electronic device specifically includes the following contents: a processor (processor), a memory (memory), a communication Interface (Communications Interface), and a bus; the processor, the memory and the communication interface complete mutual communication through the bus; the communication interface is used for realizing information transmission among the server, the client terminal and other participating mechanisms; the processor is configured to call a computer program in the memory, and when the processor executes the computer program, the processor implements all the steps in the interaction method of the TCP/IP accelerator in the above embodiments, for example, when the processor executes the computer program, the processor implements the following steps:
step 1: acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card;
step 2: distributing an address for target data through software, sending a write data instruction to the TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card;
and step 3: after the TCP/IP accelerator board card processes the target data, sending a read data instruction to the TCP/IP accelerator board card, reading storage information of the data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
As can be seen from the above description, the embodiments of the present application provide a method for establishing a TCP connection between a host and a TCP/IP accelerator, transporting data from the host to a TCP/IP accelerator board, waiting for processing by the accelerator board, and simultaneously reading data information from the accelerator board, that is, sharing a part of data processing work of software by hardware, and by the above scheme, the technical problems of low efficiency and more time consumption of the system in the existing data processing only by software are solved, and a technical effect of effectively improving the utilization rate of hardware resources is achieved, thereby reducing the waiting time of the system.
Embodiments of the present application further provide a computer-readable storage medium capable of implementing all steps in the interaction method of the TCP/IP accelerator in the foregoing embodiments, where the computer-readable storage medium stores a computer program, and the computer program, when executed by a processor, implements all steps of the interaction method of the TCP/IP accelerator in the foregoing embodiments, for example, when the processor executes the computer program, implements the following steps:
step 1: acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card;
step 2: distributing an address for target data through software, sending a write data instruction to the TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card;
and step 3: after the TCP/IP accelerator board card processes the target data, sending a read data instruction to the TCP/IP accelerator board card, reading storage information of the data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
As can be seen from the above description, the embodiments of the present application provide a method for establishing a TCP connection between a host and a TCP/IP accelerator, transporting data from the host to a TCP/IP accelerator board, waiting for processing by the accelerator board, and simultaneously reading data information from the accelerator board, that is, sharing a part of data processing work of software by hardware, and by the above scheme, the technical problems of low efficiency and more time consumption of the system in the existing data processing only by software are solved, and a technical effect of effectively improving the utilization rate of hardware resources is achieved, thereby reducing the waiting time of the system.
In this specification, adjectives such as first and second may only be used to distinguish one element or action from another, without necessarily requiring or implying any actual such relationship or order. References to an element or component or step (etc.) should not be construed as limited to only one of the element, component, or step, but rather to one or more of the element, component, or step, etc., where the context permits.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the hardware + program class embodiment, since it is substantially similar to the method embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Although the present application provides method steps as described in an embodiment or flowchart, additional or fewer steps may be included based on conventional or non-inventive efforts. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or client product executes, it may execute sequentially or in parallel (e.g., in the context of parallel processors or multi-threaded processing) according to the embodiments or methods shown in the figures.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
Although embodiments of the present description provide method steps as described in embodiments or flowcharts, more or fewer steps may be included based on conventional or non-inventive means. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or end product executes, it may execute sequentially or in parallel (e.g., parallel processors or multi-threaded environments, or even distributed data processing environments) according to the method shown in the embodiment or the figures. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the presence of additional identical or equivalent elements in a process, method, article, or apparatus that comprises the recited elements is not excluded.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, in implementing the embodiments of the present description, the functions of each module may be implemented in one or more software and/or hardware, or a module implementing the same function may be implemented by a combination of multiple sub-modules or sub-units, and the like. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may therefore be considered as a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
As will be appreciated by one skilled in the art, embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The embodiments of this specification may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The described embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment. In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the specification. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only an example of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Various modifications and variations to the embodiments described herein will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.
Claims (14)
1. An interactive method of a TCP/IP accelerator is characterized by comprising the following steps:
acquiring address information of a target TCP/IP accelerator board card, and sending a communication instruction carrying the address information to a network card to establish TCP connection with the TCP/IP accelerator board card;
distributing an address for target data through software, sending a write data instruction to the TCP/IP accelerator board card, and writing the target data into the TCP/IP accelerator board card;
after the TCP/IP accelerator board card processes the target data, sending a read data instruction to the TCP/IP accelerator board card, reading storage information of the processed target data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
2. The method of claim 1, wherein the stored information comprises at least one of: data address, data length, and number.
3. The method of claim 1, wherein reading the processed target data from the TCP/IP accelerator board according to the storage information comprises:
and reading the processed target data from the DDR module of the TCP/IP accelerator board card according to the storage information.
4. The method of claim 1, after sending a read data command to the TCP/IP accelerator board, reading storage information of the processed target data from the TCP/IP accelerator board, and reading the processed target data from the TCP/IP accelerator board according to the storage information, further comprising:
and after the preset time for establishing the TCP connection, the TCP/IP accelerator board card automatically disconnects the TCP connection.
5. The method of claim 1, wherein obtaining address information of a target TCP/IP accelerator board and sending a communication instruction carrying the address information to a network card to establish a TCP connection with the TCP/IP accelerator board comprises:
acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information;
sending a first control instruction to the target TCP/IP accelerator board card through a PIO mode, wherein the control instruction carries a first identifier and an IP address;
the target TCP/IP accelerator board card reads information from the PIO address according to the first identifier and writes a first reply identifier in the PIO mode;
after receiving the first reply identifier, writing a second control instruction into the PIO address through a PIO mode, wherein the second control instruction carries a second identifier, an IP address and port information;
the target TCP/IP accelerator board card reads corresponding information according to the second identifier and sends a second reply identifier;
and after receiving the second reply identifier, writing an IP address through a PIO mode to complete the establishment of the TCP connection.
6. The method of claim 1, wherein writing target data to the TCP/IP accelerator board by software assigning an address to the target data and sending a write data instruction to the TCP/IP accelerator board comprises:
writing the target data into the target TCP/IP accelerator board card through a DMA mode, wherein the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board card;
writing a third control instruction into the target TCP/IP accelerator board card through a PIO mode, wherein the third control instruction is data address information, and storing the data address information into a write data information address opened by the target TCP/IP accelerator board card;
writing a fourth control instruction into the target TCP/IP accelerator board card through a PIO mode, wherein the fourth control instruction carries: updating the flag bit, the length of the target data and the handle information;
and the target TCP/IP accelerator board card extracts and processes the target data according to the fourth control instruction.
7. The method of claim 6, wherein sending a read data command to the TCP/IP accelerator board, reading storage information of the processed target data from the TCP/IP accelerator board, and reading the processed target data from the TCP/IP accelerator board according to the storage information comprises:
reading the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through a PIO mode;
reading the third control instruction from a second read data information address opened by the target TCP/IP accelerator board card through a PIO mode;
reading processed target data from the pre-opened data storage address of the target TCP/IP accelerator board card through a DMA mode according to information carried in the fourth control instruction and the third control instruction;
and writing a fifth control instruction into the first read data information address through a PIO mode, wherein the fifth control instruction carries an update flag bit.
8. The method of claim 7, wherein the third, fourth, and fifth control instructions are 32-bit control instructions.
9. An interactive apparatus of a TCP/IP accelerator, comprising:
the acquisition module is used for acquiring address information of a target TCP/IP accelerator board card and sending a communication instruction carrying the address information to a network card so as to establish TCP connection with the TCP/IP accelerator board card;
the write-in module is used for distributing an address for target data through software, sending a write-in data instruction to the TCP/IP accelerator board card and writing the target data into the TCP/IP accelerator board card;
and the reading module is used for sending a read data instruction to the TCP/IP accelerator board card after the TCP/IP accelerator board card processes the target data, reading the storage information of the processed target data from the TCP/IP accelerator board card, and reading the processed target data from the TCP/IP accelerator board card according to the storage information.
10. The apparatus of claim 9, wherein the obtaining module comprises:
the acquisition unit is used for acquiring the IP address and the port information of the target TCP/IP accelerator board card as address information;
the sending unit is used for sending a first control instruction to the target TCP/IP accelerator board card through a PIO mode, wherein the control instruction carries a first identifier and an IP address;
a first writing unit, configured to write a second control instruction to the PIO address in the PIO mode after receiving a first reply identifier written in the PIO mode after the target TCP/IP accelerator board reads information from the PIO address according to the first identifier, where the second control instruction carries a second identifier, an IP address, and port information;
and the second writing unit is used for writing an IP address through a PIO mode after receiving a second reply identifier sent by the target TCP/IP accelerator board card after reading corresponding information according to the second identifier so as to complete the establishment of the TCP connection.
11. The apparatus of claim 9, wherein the write module comprises:
the third writing unit is used for writing the target data into the target TCP/IP accelerator board card through a DMA mode, wherein the target data is stored in a data storage address pre-opened in the target TCP/IP accelerator board card;
a fourth writing unit, configured to write a third control instruction to the target TCP/IP accelerator board in a PIO mode, where the third control instruction is data address information, and store the data address information in a write data information address created by the target TCP/IP accelerator board;
a fifth writing unit, configured to write a fourth control instruction into the target TCP/IP accelerator board in a PIO mode, where the fourth control instruction carries: and updating a zone bit, the length of target data and handle information, wherein the fourth control instruction is used for the target TCP/IP accelerator board card to extract and process the target data.
12. The apparatus of claim 11, wherein the reading module comprises:
the first reading unit is used for reading the fourth control instruction from a first read data information address opened up by the target TCP/IP accelerator board card through a PIO mode;
the second reading unit is used for reading the third control instruction from a second read data information address opened up by the target TCP/IP accelerator board card through a PIO mode;
a third reading unit, configured to read, according to information carried in the fourth control instruction and the third control instruction, processed target data from the pre-opened data storage address of the target TCP/IP accelerator board in a DMA mode;
and a sixth writing unit, configured to write a fifth control instruction into the first read data information address in a PIO mode, where the fifth control instruction carries an update flag bit.
13. A network device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 8 when executing the computer program.
14. A non-transitory computer readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of any of claims 1 to 8.
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| CN113011117B (en) * | 2021-02-18 | 2022-10-28 | 中科驭数（北京）科技有限公司 | Hardware acceleration board card analog simulation method, system and device |
| CN113190395B (en) * | 2021-03-15 | 2023-08-18 | 新华三信息技术有限公司 | State monitoring method and device |
| CN117155729A (en) * | 2022-05-24 | 2023-12-01 | 北京有竹居网络技术有限公司 | Communication method, system, device and electronic equipment |
| CN115473861B (en) * | 2022-08-18 | 2023-11-03 | 珠海高凌信息科技股份有限公司 | High-performance processing system and method based on communication and calculation separation and storage medium |
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