CN111030830A - Network interface circuit for road administration cabinet supervision system - Google Patents
Network interface circuit for road administration cabinet supervision system Download PDFInfo
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- CN111030830A CN111030830A CN201811172805.9A CN201811172805A CN111030830A CN 111030830 A CN111030830 A CN 111030830A CN 201811172805 A CN201811172805 A CN 201811172805A CN 111030830 A CN111030830 A CN 111030830A
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- 239000003990 capacitor Substances 0.000 claims abstract description 130
- 239000013078 crystal Substances 0.000 claims description 12
- 206010033799 Paralysis Diseases 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/02—Constructional details
- H04Q1/028—Subscriber network interface devices
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Abstract
The invention relates to a network interface circuit for a road administration cabinet supervision system, which comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a first inductor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor and a network interface chip. The invention overcomes the problems that the prior art can not carry out centralized real-time management on data and can face high delay and system paralysis when the data volume is huge, has low delay and is suitable for more nodes.
Description
Technical Field
The invention belongs to the field of Internet of things road administration, and particularly relates to a network interface circuit for a road administration cabinet supervision system.
Background
The advent of the internet of things has brought about a significant change in the information field, which is considered to be the third wave of information industry after computers, the internet and mobile communication networks. As the name implies, the Internet of things is the Internet with connected objects. This has two layers: firstly, the core and the foundation of the internet of things are still the internet; and secondly, the user side extends and expands to any article to perform information exchange and communication, namely, the article information. Under this wave of great tide, improvements and changes in road administration technology are also becoming imminent.
When the system is designed, data needs to be received or sent through a network, however, because the requirement of the road administration system on the data transmission performance is high, the prior art has no scheme designed for the network transmission of the road administration system.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a network interface circuit for an administrative cabinet supervision system. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a network interface circuit for a road administration cabinet supervision system, which comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a first inductor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor and a network interface chip; one end of the first capacitor is connected with a voltage source and one end of a first inductor, the other end of the first capacitor is connected with a grounding terminal, the other end of the first inductor is connected with one end of a second capacitor, one end of a third capacitor, a crystal oscillator pin 4 and the voltage source, and the other end of the second capacitor and the other end of the third capacitor are both connected with the grounding terminal; the crystal oscillator pin 3 is connected with one end of the second resistor and one end of the third resistor, the other end of the second resistor is connected with the microprocessor, and the other end of the third resistor is connected with the network interface chip pin 34; one end of the fourth capacitor, one end of the fifth capacitor, one end of the sixth capacitor and one end of the seventh capacitor are all connected with the pin 37, the pin 18 and the pin 23 of the network interface chip, and the other end of the fourth capacitor, the other end of the fifth capacitor, the other end of the sixth capacitor and the other end of the seventh capacitor are all connected with a grounding terminal; one end of the fourth resistor is connected with a ground terminal, and the other end of the fourth resistor is connected with the network interface chip pin 24; one end of the fifth resistor is connected with a voltage source, and the other end of the fifth resistor is connected with the pin 7 of the network interface chip; one end of the sixth resistor is connected with a voltage source, and the other end of the sixth resistor is connected with the network interface chip pin 29; one end of the seventh resistor is connected with a voltage source, and the other end of the seventh resistor is connected with the network interface chip pin 30; one end of the eighth resistor is connected with a voltage source, and the other end of the eighth resistor is connected with the network interface chip pin 30 through the ninth resistor; the pins 31, 13, 14, 16 and 17 of the network interface chip are connected with the microprocessor; the microprocessor is connected with the network interface chip pin 44 through the tenth resistor; the microprocessor is connected with the network interface chip pin 43 through the eleventh resistor; the microprocessor is connected with the network interface chip pin 4 through the fifteenth resistor; the microprocessor is connected with the network interface chip pin 3 through the sixteenth resistor; the microprocessor is connected with the network interface chip pin 2 through the seventeenth resistor; the pin 5 of the network interface chip is connected with a ground end through the thirteenth resistor; the pin 6 of the network interface chip is connected with a ground end through the twelfth resistor; one end of the eighteenth resistor is connected with a voltage source, and the other end of the eighteenth resistor is connected with the network interface chip pin 28; one end of the nineteenth resistor is connected with a voltage source, and the other end of the nineteenth resistor is connected with the network interface chip pin 27; one end of the twentieth resistor is connected with a voltage source, and the other end of the twentieth resistor is connected with the network interface chip pin 26; one end of the twenty-first resistor is connected with a voltage source, and the other end of the twenty-first resistor is connected with the network interface chip pin 21; one end of the twenty-second resistor is connected with a voltage source, and the other end of the twenty-second resistor is connected with the network interface chip pin 20; the network interface chip pin 22, the network interface chip pin 48 and the network interface chip pin 32 are all connected with one end of the eighth capacitor, one end of the ninth capacitor, one end of the tenth capacitor, one end of the eleventh capacitor, one end of the twelfth capacitor, one end of the thirteenth capacitor, one end of the second inductor and the voltage source, the other end of the eighth capacitor, the other end of the ninth capacitor, the other end of the tenth capacitor, the other end of the eleventh capacitor, the other end of the twelfth capacitor and the other end of the thirteenth capacitor are connected with a grounding terminal, and the other end of the second inductor is connected with the voltage source; the pins 19, 15, 47, 35 and 36 of the network interface chip are all connected to the ground.
In one embodiment, the microprocessor is of the model STM32F 429.
In a specific embodiment, the crystal oscillator is an active crystal oscillator.
In one embodiment, the voltage source (V1) is 3.3V.
Compared with the prior art, the invention has the beneficial effects that:
the network interface circuit for the road administration cabinet supervision system can send the received data to the server from the station, and the circuit can transmit the obtained information to the server on the upper layer in real time, so that the problems that the data cannot be centrally managed in real time in the prior art, high delay and system paralysis are caused when the data amount is huge are solved, the delay is low, and the network interface circuit is suitable for more nodes.
Drawings
Fig. 1 is a circuit diagram of a network interface for an administrative cabinet supervision system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a network interface circuit diagram for a road administration cabinet monitoring system according to an embodiment of the present invention, including a first capacitor C, a second capacitor C, a third capacitor C, a fourth capacitor C, a fifth capacitor C, a sixth capacitor C, a seventh capacitor C, an eighth capacitor C, a ninth capacitor C, a tenth capacitor C, an eleventh capacitor C, a twelfth capacitor C, a thirteenth capacitor C, a first inductor L, a second resistor R, a third resistor R, a fourth resistor R, a fifth resistor R, a sixth resistor R, a seventh resistor R, an eighth resistor R, a ninth resistor R, a tenth resistor R, an eleventh resistor R, a twelfth resistor R, a thirteenth resistor R, a fourteenth resistor R, a fifteenth resistor R, a sixteenth resistor R, a seventeenth resistor R, an eighteenth resistor R, a nineteenth resistor R, a twentieth resistor R, Twenty-first resistor R21, twenty-second resistor R22 and network interface chip DP 83848; one end of the first capacitor C1 is connected to a voltage source V1 and one end of a first inductor L1, the other end of the first capacitor C1 is connected to a ground terminal GND, the other end of the first inductor L1 is connected to one end of a second capacitor C2, one end of a third capacitor C3, a pin 4 of a crystal oscillator U1 and the voltage source V1, and the other end of the second capacitor C2 and the other end of the third capacitor C3 are both connected to the ground terminal GND; the pin 3 of the crystal oscillator U1 is connected with one end of the second resistor R2 and one end of the third resistor R3, the other end of the second resistor R2 is connected with a microprocessor U2, and the other end of the third resistor R3 is connected with a pin 34 of the network interface chip DP 83848; one end of the fourth capacitor C4, one end of the fifth capacitor C5, one end of the sixth capacitor C6 and one end of the seventh capacitor C7 are all connected to the pin 37, the pin 18 and the pin 23 of the network interface chip DP83848, and the other end of the fourth capacitor C4, the other end of the fifth capacitor C5, the other end of the sixth capacitor C6 and the other end of the seventh capacitor C7 are all connected to a ground terminal GND; one end of the fourth resistor R4 is connected to a ground GND, and the other end is connected to the pin 24 of the network interface chip DP 83848; one end of the fifth resistor R5 is connected with a voltage source V1, and the other end of the fifth resistor R5 is connected with the pin 7 of the network interface chip DP 83848; one end of the sixth resistor R6 is connected with a voltage source V1, and the other end of the sixth resistor R6 is connected with the pin 29 of the network interface chip DP 83848; one end of the seventh resistor R7 is connected with a voltage source V1, and the other end of the seventh resistor R7 is connected with the pin 30 of the network interface chip DP 83848; one end of the eighth resistor R8 is connected to a voltage source V1, and the other end of the eighth resistor R8 is connected to the pin 30 of the network interface chip DP83848 through the ninth resistor R9; the pin 31, the pin 13, the pin 14, the pin 16 and the pin 17 of the network interface chip DP83848 are connected with a microprocessor U2; the microprocessor U2 is connected to the DP83848 pin 44 of the network interface chip through the tenth resistor R10; the microprocessor U2 is connected to the DP83848 pin 43 of the network interface chip through the eleventh resistor R11; the microprocessor U2 is connected to the DP83848 pin 4 of the network interface chip through the fifteenth resistor R15; the microprocessor U2 is connected to the DP83848 pin 3 of the network interface chip through the sixteenth resistor R16; the microprocessor U2 is connected to the DP83848 pin 2 of the network interface chip through the seventeenth resistor R17; the pin 5 of the network interface chip DP83848 is connected to a ground GND through the thirteenth resistor R13; the pin 6 of the network interface chip DP83848 is connected to the ground GND through the twelfth resistor R12; one end of the eighteenth resistor R18 is connected with a voltage source V1, and the other end of the eighteenth resistor R18 is connected with the pin 28 of the network interface chip DP 83848; one end of the nineteenth resistor R19 is connected to a voltage source V1, and the other end of the nineteenth resistor R19 is connected to the pin 27 of the network interface chip DP 83848; one end of the twentieth resistor R20 is connected with a voltage source V1, and the other end of the twentieth resistor R20 is connected with the pin 26 of the network interface chip DP 83848; one end of the twenty-first resistor R21 is connected with a voltage source V1, and the other end of the twenty-first resistor R21 is connected with the pin 21 of the network interface chip DP 83848; one end of the twenty-second resistor R22 is connected with a voltage source V1, and the other end of the twenty-second resistor R22 is connected with the pin 20 of the network interface chip DP 83848; the network interface chip DP83848 pin 22, the network interface chip DP83848 pin 48, and the network interface chip DP83848 pin 32 are all connected to one end of the eighth capacitor C8, one end of the ninth capacitor C9, one end of the tenth capacitor C10, one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the thirteenth capacitor C13, one end of the second inductor L2, and the voltage source V1, the other end of the eighth capacitor C8, the other end of the ninth capacitor C9, the other end of the tenth capacitor C10, the other end of the eleventh capacitor C11, the other end of the twelfth capacitor C12, and the other end of the thirteenth capacitor C13 are connected to a ground GND, and the other end of the second inductor L2 is connected to the voltage source V1; the pin 19, the pin 15, the pin 47, the pin 35, and the pin 36 of the network interface chip DP83848 are all connected to the ground GND.
The network interface circuit for the road administration cabinet supervision system can send the received data to the server from the station, and the circuit can transmit the obtained information to the server on the upper layer in real time, so that the problems that the data cannot be centrally managed in real time in the prior art, high delay and system paralysis are caused when the data amount is huge are solved, the delay is low, and the network interface circuit is suitable for more nodes.
In one embodiment, the microprocessor U2 is model number STM32F 429.
In one embodiment, the crystal oscillator U1 is an active crystal oscillator.
In one embodiment, the voltage source (V1) is 3.3V.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (4)
1. A network interface circuit for a road administration cabinet supervision system is characterized by comprising a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8), a ninth capacitor (C9), a tenth capacitor (C10), an eleventh capacitor (C11), a twelfth capacitor (C12), a thirteenth capacitor (C13), a first inductor (L1), a second inductor (L2), a second resistor (R2), a third resistor (R2), a fourth resistor (R2), a fifth resistor (R2), a sixth resistor (R2), a seventh resistor (R2), an eighth resistor (R2), a ninth resistor (R2), a tenth resistor (R2), an eleventh resistor (R2), a twelfth resistor (R2), a fourteenth resistor (R2), A fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), an eighteenth resistor (R18), a nineteenth resistor (R19), a twentieth resistor (R20), a twenty-first resistor (R21), a twenty-second resistor (R22) and a network interface chip (DP 83848); one end of the first capacitor (C1) is connected with one end of a voltage source (V1) and one end of a first inductor (L1), the other end of the first capacitor (C1) is connected with a ground terminal (GND), the other end of the first inductor (L1) is connected with one end of a second capacitor (C2), one end of a third capacitor (C3), a pin 4 of a crystal oscillator (U1) and the voltage source (V1), and the other end of the second capacitor (C2) and the other end of the third capacitor (C3) are both connected with the ground terminal (GND); the pin 3 of the crystal oscillator (U1) is connected with one end of the second resistor (R2) and one end of the third resistor (R3), the other end of the second resistor (R2) is connected with the microprocessor (U2), and the other end of the third resistor (R3) is connected with the pin 34 of the network interface chip (DP 83848); one end of the fourth capacitor (C4), one end of the fifth capacitor (C5), one end of the sixth capacitor (C6) and one end of the seventh capacitor (C7) are all connected with the pin 37, the pin 18 and the pin 23 of the network interface chip (DP83848), and the other ends of the fourth capacitor (C4), the fifth capacitor (C5), the sixth capacitor (C6) and the seventh capacitor (C7) are all connected with a ground terminal (GND); one end of the fourth resistor (R4) is connected with a ground terminal (GND), and the other end of the fourth resistor (R4) is connected with the pin 24 of the network interface chip (DP 83848); one end of the fifth resistor (R5) is connected with a voltage source (V1), and the other end of the fifth resistor (R5) is connected with a pin 7 of the network interface chip (DP 83848); one end of the sixth resistor (R6) is connected with a voltage source (V1), and the other end of the sixth resistor (R6) is connected with the pin 29 of the network interface chip (DP 83848); one end of the seventh resistor (R7) is connected with a voltage source (V1), and the other end of the seventh resistor (R7) is connected with the pin 30 of the network interface chip (DP 83848); one end of the eighth resistor (R8) is connected with a voltage source (V1), and the other end of the eighth resistor (R8) is connected with the pin 30 of the network interface chip (DP83848) through the ninth resistor (R9); the pins 31, 13, 14, 16 and 17 of the network interface chip (DP83848) are connected with a microprocessor (U2); the microprocessor (U2) is connected to the network interface chip (DP83848) pin 44 through the tenth resistor (R10); the microprocessor (U2) is connected with the pin 43 of the network interface chip (DP83848) through the eleventh resistor (R11); the microprocessor (U2) is connected with the pin 4 of the network interface chip (DP83848) through the fifteenth resistor (R15); the microprocessor (U2) is connected with the pin 3 of the network interface chip (DP83848) through the sixteenth resistor (R16); the microprocessor (U2) is connected to pin 2 of the network interface chip (DP83848) through the seventeenth resistor (R17); the pin 5 of the network interface chip (DP83848) is connected with a ground terminal (GND) through the thirteenth resistor (R13); the pin 6 of the network interface chip (DP83848) is connected with a ground terminal (GND) through the twelfth resistor (R12); one end of the eighteenth resistor (R18) is connected with a voltage source (V1), and the other end of the eighteenth resistor (R18) is connected with the pin 28 of the network interface chip (DP 83848); one end of the nineteenth resistor (R19) is connected with a voltage source (V1), and the other end of the nineteenth resistor (R19) is connected with the pin 27 of the network interface chip (DP 83848); one end of the twentieth resistor (R20) is connected with a voltage source (V1), and the other end of the twentieth resistor (R20) is connected with the pin 26 of the network interface chip (DP 83848); one end of the twenty-first resistor (R21) is connected with a voltage source (V1), and the other end of the twenty-first resistor (R21) is connected with a pin 21 of the network interface chip (DP 83848); one end of the twenty-second resistor (R22) is connected with a voltage source (V1), and the other end of the twenty-second resistor (R22) is connected with the pin 20 of the network interface chip (DP 83848); the pin 22 of the network interface chip (DP83848), the pin 48 of the network interface chip (DP83848) and the pin 32 of the network interface chip (DP83848) are all connected to one end of the eighth capacitor (C8), one end of the ninth capacitor (C9), one end of the tenth capacitor (C10), one end of the eleventh capacitor (C11), one end of the twelfth capacitor (C12), one end of the thirteenth capacitor (C13), one end of the second inductor (L2) and the voltage source (V1), the other end of the eighth capacitor (C8), the other end of the ninth capacitor (C9), the other end of the tenth capacitor (C10), the other end of the eleventh capacitor (C11), the other end of the twelfth capacitor (C12), the other end of the thirteenth capacitor (C13) are connected to the ground terminal (GND), and the other end of the second inductor (L2) is connected to the voltage source (V1); the pin 19, the pin 15, the pin 47, the pin 35 and the pin 36 of the network interface chip (DP83848) are all connected to the Ground (GND).
2. The network interface circuit for an administrative cabinet supervision system according to claim 1, characterized in that the microprocessor (U2) is of the model STM32F 429.
3. The network interface circuit for an administrative cabinet supervision system according to claim 1, characterized in that the crystal oscillator (U1) is an active crystal oscillator.
4. The network interface circuit for an administrative cabinet supervision system according to claim 1, characterized in that the voltage source (V1) is 3.3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811172805.9A CN111030830A (en) | 2018-10-09 | 2018-10-09 | Network interface circuit for road administration cabinet supervision system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811172805.9A CN111030830A (en) | 2018-10-09 | 2018-10-09 | Network interface circuit for road administration cabinet supervision system |
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| CN111030830A true CN111030830A (en) | 2020-04-17 |
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| CN201811172805.9A Pending CN111030830A (en) | 2018-10-09 | 2018-10-09 | Network interface circuit for road administration cabinet supervision system |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102387054A (en) * | 2011-10-17 | 2012-03-21 | 杭州鸥信电子科技有限公司 | Serial port to Ethernet control device based on STM32 |
| CN202282784U (en) * | 2011-10-17 | 2012-06-20 | 杭州鸥信电子科技有限公司 | Controlling device for converting serial port to Ethernet based on STM 32 |
| CN102970095A (en) * | 2012-11-26 | 2013-03-13 | 杭州电子科技大学 | Clock synchronization circuit applied to DCS (distributed control systems) |
| CN204946443U (en) * | 2015-09-16 | 2016-01-06 | 广州市风标电子技术有限公司 | A kind of car networked electronic synthesis experiment platform |
-
2018
- 2018-10-09 CN CN201811172805.9A patent/CN111030830A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102387054A (en) * | 2011-10-17 | 2012-03-21 | 杭州鸥信电子科技有限公司 | Serial port to Ethernet control device based on STM32 |
| CN202282784U (en) * | 2011-10-17 | 2012-06-20 | 杭州鸥信电子科技有限公司 | Controlling device for converting serial port to Ethernet based on STM 32 |
| CN102970095A (en) * | 2012-11-26 | 2013-03-13 | 杭州电子科技大学 | Clock synchronization circuit applied to DCS (distributed control systems) |
| CN204946443U (en) * | 2015-09-16 | 2016-01-06 | 广州市风标电子技术有限公司 | A kind of car networked electronic synthesis experiment platform |
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| Title |
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| 贾克斯大师: "STM32+DP83848 以太网连接问题", 《电子工程世界》 * |
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