CN111028875B - Memory computing circuit - Google Patents
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- CN111028875B CN111028875B CN201911212863.4A CN201911212863A CN111028875B CN 111028875 B CN111028875 B CN 111028875B CN 201911212863 A CN201911212863 A CN 201911212863A CN 111028875 B CN111028875 B CN 111028875B
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
Abstract
The present disclosure provides a memory computing circuit. The circuit comprises a signal input unit (1), a first 1T1R unit (2), a second 1T1R unit (3), and an output unit (4), wherein: the signal input unit (1) is used for inputting a first voltage signal, a second voltage signal and a third voltage signal, the first voltage signal is used for driving a first 1T1R unit (2) and a second 1T1R unit (3), the second voltage signal is input into a first 1T1R unit (2), the third voltage signal is input into a second 1T1R unit (3), the first voltage signal corresponds to a first weight, or the combination of the second voltage signal and the third voltage signal corresponds to the first weight; the combination of the resistance value of the first 1T1R cell (2) and the resistance value of the second 1T1R cell (3) corresponds to a second weight value; the output unit (4) is connected with the first 1T1R unit (2) and the second 1T1R unit (3) and is used for outputting an electric signal, and the value of the electric signal corresponds to the product of the first weight and the second weight.
Description
Technical Field
The present disclosure relates to the field of circuit technology, and in particular, to a memory computing circuit.
Background
Machine learning plays an important role in the fields of image recognition, voice recognition, signal processing and the like, and multiplication and addition operation is used as core operation of a machine learning algorithm, and the performance of the multiplication and addition operation is one of the keys for accelerating machine learning application. A nonvolatile Random Access Memory (RRAM) has advantages of a fast Access speed, low power consumption, and high density. Based on the resistance characteristics of the RRAM device and the one-transistor one-memory cell (1T1R) array structure, vector data can be expressed as input voltage signals, and matrix data can be stored in the RRAM 1T1R array cells, thereby realizing efficient multiply-add operation.
In the related art, positive and negative weights are mainly realized through a positive array and a negative array to perform multiplication and addition operation, or the multiplication and addition operation is realized through a difference mode. In the two schemes, positive and negative weights are used for separate calculation, the multiplication and addition value is obtained by reading out the positive and negative multiplication and addition values and then adding and subtracting the positive and negative multiplication and addition values again through two Analog-to-Digital converters (ADC), the two schemes both reduce the range of the multiplication and addition value, and the used ADCs are more, so that the cost is higher.
Disclosure of Invention
In view of this, the present disclosure provides a memory computing circuit for implementing a binary weight input and a ternary output multiply-add operation based on a 2T2R RRAM array with a common source structure.
In one aspect of the present disclosure, there is provided a memory computing circuit including a signal input unit, a first 1T1R unit, a second 1T1R unit, and an output unit, wherein: the signal input unit is used for inputting a first voltage signal, a second voltage signal and a third voltage signal, the first voltage signal is used for driving the first 1T1R unit and the second 1T1R unit, the second voltage signal is input into the first 1T1R unit, the third voltage signal is input into the second 1T1R unit, the first voltage signal corresponds to a first weight, or the combination of the second voltage signal and the third voltage signal corresponds to the first weight; the combination of the resistance value of the first 1T1R cell and the resistance value of the second 1T1R cell corresponds to a second weight; the output unit is connected with the first 1T1R unit and the second 1T1R unit and is used for outputting an electric signal, and the value of the electric signal corresponds to the product of the first weight value and the second weight value.
Optionally, when the first voltage signal corresponds to the first weight, the electrical signal is formed by dividing the second voltage signal and the third voltage signal by the first 1T1R unit and the second 1T1R unit.
Optionally, when a combination of the second voltage signal and the third voltage signal corresponds to the first weight, the first voltage signal is at a high level, and the output unit is precharged to a preset level.
Optionally, the electrical signal is formed by performing pull-up, pull-down, or leave unchanged processing on the preset level by the second voltage signal or the third voltage signal.
Optionally, the preset level is an average value of the second voltage signal and the third voltage signal.
Optionally, the signal input unit (1) comprises: a first input subunit (11) for inputting the first voltage signal to the first 1T1R cell (2) and the second 1T1R cell (3) to control the on/off of the transistors in the first 1T1R cell (2) and the second 1T1R cell (3); a second input subunit (12) for inputting the second voltage signal; a third input subunit (13) for inputting the third voltage signal.
Optionally, one of the second voltage signal and the third voltage signal is at a low level, and the other is at a high level, and when the combination of the second voltage signal and the third voltage signal corresponds to the first weight, the first weight is 1 or-1.
Optionally, when the first voltage signal corresponds to the first weight, the first weight is 0 or 1.
Optionally, the first 1T1R unit (2) is connected in common source with a second 1T1R unit (3), and the input unit (1) is configured to input the first voltage signal to source terminals of the first 1T1R unit (2) and the second 1T1R unit (3).
Optionally, when the resistance value of the first 1T1R cell (2) is greater than the resistance value of the second 1T1R cell (3), the second weight is-1, when the resistance value of the first 1T1R cell (2) is equal to the resistance value of the second 1T1R cell (3), the second weight is 0, and when the resistance value of the first 1T1R cell (2) is less than the resistance value of the second 1T1R cell (3), the second weight is 1.
(III) advantageous effects
The memory computing and calculating circuit provided by the disclosure has the following beneficial effects:
(1) the 1T1R array structure with the common source line is adopted, the array structure can be manufactured on Fab and has reliable operation;
(2) by calculating the positive and negative weights in the array, the output part can read out the final multiplied value by only one ADC, so that the number of required ADCs is reduced, and higher parallelism can be supported;
(3) the output multiplication and addition values are three, the multiplication and addition values with a larger range are output, the peak current is smaller, and the current in the circuit is reduced.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
fig. 1 schematically illustrates a block diagram of a memory computing circuit according to an embodiment of the present disclosure;
fig. 2 schematically illustrates a block diagram of a memory computing circuit according to another embodiment of the present disclosure;
FIG. 3 is a block diagram schematically illustrating an architecture of an in-memory computing circuit array provided by an embodiment of the present disclosure; and
fig. 4 schematically shows a block diagram of a memory computing circuit array according to another embodiment of the present disclosure.
Description of reference numerals:
1-a signal input unit; 2-first 1T1R cell; 3-a second 1T1R cell; 4-an output unit; 11-a first input subunit; 12-a second input subunit; 13-third input subunit.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The embodiment of the disclosure provides an in-memory computing circuit. The memory computing circuit includes a signal input unit 1, a first 1T1R unit 2, a second 1T1R unit 3, and an output unit 4, wherein: the signal input unit 1 is configured to input a first voltage signal, a second voltage signal and a third voltage signal, the first voltage signal is used to drive the first 1T1R cell 2 and the second 1T1R cell 3, the second voltage signal is input to the first 1T1R cell 2, the third voltage signal is input to the second 1T1R cell 3, the first voltage signal corresponds to the first weight, or a combination of the second voltage signal and the third voltage signal corresponds to the first weight; the combination of the resistance of the first 1T1R cell 2 and the resistance of the second 1T1R cell 3 corresponds to a second weight; the output unit 4 is connected to the first 1T1R unit 2 and the second 1T1R unit 3, and outputs an electrical signal, a value of which corresponds to a product of the first weight and the second weight.
Fig. 1 is a block diagram schematically illustrating a memory computing circuit for a first voltage signal corresponding to a first weight. Referring to fig. 1, the structure shown in fig. 1 will be described in detail.
The signal input unit 1 comprises a first input subunit 11, a second input subunit 12 and a third input subunit 13.
The first input sub-unit 11 inputs a first voltage signal to the first 1T1R cell 2 and the second 1T1R cell 3 to control the on/off of the transistors in the first 1T1R cell 2 and the second 1T1R cell 3. Specifically, the first 1T1R cell 2 and the second 1T1R cell 3 are connected in common source, and the first sub input cell 11 inputs the first voltage signal to the first 1T1R cell 2 and the second 1T1R cell 3 and the source terminal. The transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are turned on when the first voltage signal is high, and the transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are turned off when the first voltage signal is low.
The first voltage signal corresponds to a first weight, and the first weight is 0 or 1. Specifically, when the first voltage signal is at a low level, the transistor is in an off state, and a first weight corresponding to the first voltage signal is 0; when the first voltage signal is at a high level VDD, the transistor is in an on state, and the first weight corresponding to the first voltage signal is 1. In the embodiment of the present disclosure, the high-level first voltage signal is, for example, 3.3V, and the low-level first voltage signal is, for example, 0V.
The second input sub-unit 12 inputs the second voltage signal to the first 1T1R unit 2. The third input subunit 13 inputs a third voltage signal to the second 1T1R unit 3. In the embodiment of the present disclosure, the second voltage signal is at a high level VhThe third voltage signal is at low levelVlThe second voltage signal at the high level is, for example, +1.2V, and the third voltage signal at the low level is, for example, + 0.6V.
When the first voltage signal is high, the transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are in an on state, and the electrical signal of the output unit 4 is the first 1T1R cell 2 and the second 1T1R cell 3 to the second voltage signal VhAnd a third voltage signal VlAfter partial pressure is established.
The resistance of the first 1T1R cell 2 is the sum of the equivalent resistance of the transistor in the first 1T1R cell 2 and the resistance of the variable resistor R1, and the resistance of the second 1T1R cell 3 is the sum of the equivalent resistance of the transistor in the second 1T1R cell 3 and the resistance of the variable resistor R2.
In the embodiment of the disclosure, when the resistance of the first 1T1R cell 2 is greater than the resistance of the second 1T1R cell 3, the second weight is-1, when the resistance of the first 1T1R cell 2 is equal to the resistance of the second 1T1R cell 3, the second weight is 0, and when the resistance of the first 1T1R cell 2 is less than the resistance of the second 1T1R cell 3, the second weight is 1. The resistance of the first 1T1R cell 2 may be adjusted by adjusting the value of the variable resistor R1, and the resistance of the second 1T1R cell 3 may be adjusted by adjusting the value of the variable resistor R2.
For the case that the first voltage signal is at low level, the transistors in the first 1T1R unit 2 and the second 1T1R unit 3 are in an off state, the first weight is 0, and the output unit 4 outputs an electric signal indicating that the multiplication and addition operation output is 0.
For the case where the first voltage signal is high, the transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are in an on state, and the first weight is 1. When the resistance of the first 1T1R cell 2 is greater than the resistance of the second 1T1R cell 3, the second weight is-1, and specifically, for example, when the resistance of the second 1T1R cell 3 is much smaller than the resistance of the first 1T1R cell 2, the voltage signal of the output unit 4 is approximately the third voltage signal VlThe result indicates that the multiplication and addition operation output is-1; when the resistance of the first 1T1R cell 2 is equal to the resistance of the second 1T1R cell 3, the second weight is 0, and the voltage signal of the output cell 4 is (V)h+Vl) A/2, which represents that the multiplication and addition operation output is 0; when the resistance of the first 1T1R cell 2 is smaller than that of the second 1T1R cellWhen the resistance of the element 3 is smaller than the second weight value, the second weight value is-1, and specifically, for example, when the resistance of the second 1T1R cell 3 is larger than the resistance of the first 1T1R cell 2, the voltage signal of the output cell 4 is approximately the second voltage signal VhThe result of the multiplication and addition operation is 1.
The multiply-add scheme in the embodiment shown in fig. 1 is shown in table 1. R1 and R2 include two states, a High Resistance State (HRS) and a Low Resistance State (LRS).
TABLE 1
| Input IN (first voltage signal) | Weight W (R1, R2) | Product (IN X W) | ΔVo |
| 0 | 0(HRS，HRS) | 0 | 0 |
| 0 | -1(HRS，LRS) | 0 | 0 |
| 0 | +1(LRS，HRS) | 0 | 0 |
| 1(VDD) | 0(HRS，HRS) | 0 | 0 |
| 1(VDD) | -1(HRS，LRS) | -1 | ΔV1 |
| 1(VDD) | +1(LRS，HRS) | +1 | ΔV2 |
Wherein, is Δ VoIndicating a change in the output voltage relative to the multiplication value of 0.Δ V1 shows that multiplying the addition value-1 causes a change in the output voltage with respect to the multiplication value 0; Δ V2 represents the change in output voltage caused by multiplying the addition value 1 with respect to the multiplication value 0, and the magnitudes of Δ V1 and Δ V2 are respectively:
wherein, VhIs a second voltage signal, VlIs a third voltage signal, RBL-SLIs the equivalent resistance of the first 1T1R cell corresponding to the multiplication addition value 0, RSL-BLBThe equivalent resistance of the second 1T1R cell corresponding to the multiplier-adder 0.
Fig. 2 is a block diagram schematically illustrating a configuration of a memory computing circuit in which a combination of a second voltage signal and a third voltage signal corresponds to a first weight. Referring to fig. 2, the structure shown in fig. 2 will be described in detail.
The signal input unit 1 comprises a first input subunit 11, a second input subunit 12 and a third input subunit 13.
The first input sub-unit 11 inputs a first voltage signal to the first 1T1R cell 2 and the second 1T1R cell 3 to control the on/off of the transistors in the first 1T1R cell 2 and the second 1T1R cell 3. Specifically, the first 1T1R cell 2 and the second 1T1R cell 3 are connected in common source, and the first sub input cell 11 inputs the first voltage signal to the first 1T1R cell 2 and the second 1T1R cell 3 and the source terminal. The transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are turned on when the first voltage signal is high, and the transistors in the first 1T1R cell 2 and the second 1T1R cell 3 are turned off when the first voltage signal is low. In the embodiment shown in fig. 2, the first voltage signal is high, so that the circuit shown in fig. 2 is in a normal calculation state.
The second input sub-unit 12 inputs the second voltage signal to the first 1T1R unit 2. The third input subunit 13 inputs a third voltage signal to the second 1T1R unit 3. One of the second voltage signal and the third voltage signal is at a low level, the other one is at a high level, and a first weight corresponding to a combination of the second voltage signal and the third voltage signal is 1 or-1. Specifically, when the second voltage signal is at a low level VLThe third voltage signal is at a high level VHThen, the first weight is-1; when the second voltage signal is at a high level VHThe third voltage signal is at a low level VLThe first weight is 1.
The output unit 4 is precharged to a preset level, which is an average value of the second voltage signal and the third voltage signal. In the disclosed embodiment, the high level VHE.g. 0.8V, low level VLFor example 0V, and the preset level is for example 0.4V.
In the embodiment shown in FIG. 2, the second weight is-1 when the resistance of the first 1T1R cell 2 is greater than the resistance of the second 1T1R cell 3, 0 when the resistance of the first 1T1R cell 2 is equal to the resistance of the second 1T1R cell 3, and 1 when the resistance of the first 1T1R cell 2 is less than the resistance of the second 1T1R cell 3. The resistance of the first 1T1R cell 2 may be adjusted by adjusting the value of the variable resistor R1, and the resistance of the second 1T1R cell 3 may be adjusted by adjusting the value of the variable resistor R2.
The electrical signal of the output unit 4 is formed by performing pull-up, pull-down or constant processing on a preset level by the second voltage signal or the third voltage signal. Specifically, for example, the second voltage signal is at a low level of 0V, the third voltage signal is at a high level of 0.8V, the resistance of the first 1T1R unit 2 is at a high-resistance state HRS, the resistance of the second 1T1R unit 3 is at a high-resistance state HRS, and the output unit is precharged to 0.4V, where the first weight is-1 and the second weight is 0, the voltage difference between the two ends of the first 1T1R unit 2 and the voltage difference between the two ends of the second 1T1R unit 3 are both at 0.4V, and the resistances of the two units are the same, so that the currents flowing through the first 1T1R unit 2 and the second 1T1R unit 3 are the same, the output unit 4 is not charged and discharged, the electrical signal at the output unit 4 remains unchanged, and the product corresponding to the electrical signal of the output unit 4 is 0. Taking the second voltage signal as a low level 0V, the third voltage signal as a high level 0.8V, the resistance of the first 1T1R unit 2 is a high resistance state HRS, the resistance of the second 1T1R unit 3 is a low resistance state LRS, and the output unit is precharged to 0.4V, where the first weight is-1 and the second weight is-1, the voltage difference between the two ends of the first 1T1R unit 2 and the voltage difference between the two ends of the second 1T1R unit 3 are both 0.4V, the resistance of the first 1T1R unit 2 is greater than the resistance of the second 1T1R unit 3, the current flowing through the first 1T1R unit 2 is smaller than the current flowing through the second 1T1R unit 3, at this time, the output unit 4 is charged, the third voltage signal pulls up the electrical signal of the output unit 4, and the product corresponding to the electrical signal of the output unit 4 is +1.
The multiply-add scheme in the embodiment shown in fig. 2 is shown in table 2. The magnitude of Δ V1 and Δ V2 is the same as that of Δ V1 and Δ V2 in table 1, and will not be described herein again.
TABLE 2
Based on this, the memory computing circuit in the embodiment shown in fig. 1 and fig. 2 is an RRAM array composed of two common-source 1T1R units, a multiplication and addition scheme of binary input and three-value output is implemented in the RRAM array, the analog-to-digital conversion times required by positive and negative weight processing in the related art are reduced through subtraction in an analog domain, current and power consumption in the operation process are also reduced through resistance voltage division, and the memory computing circuit has a wide application scenario.
Fig. 3 schematically shows a block diagram of a memory computing circuit array according to an embodiment of the present disclosure. The structure shown in fig. 3 is expanded by the memory computing circuit shown in fig. 1, and can support multiply-add operation with larger parallelism. Word lines WL [1] to WL [ n ] are used as first input sub-cells, bit lines BL [1] to BL [ n ] are used as second input sub-cells, bit lines BLB [1] to BLB [ n ] are used as third input sub-cells, and source lines SL [1] to SL [ n ] are used as output cells. The circuit structures in each dashed line frame constitute a memory computation unit, which has inputs of word lines WL [1] to WL [ n ], bit lines BL [ i ], and bit lines BLB [ i ], i being 1, 2, … …, n, and an output of source line SL [ i ]. The working process is the same as that of the memory computing circuit in the embodiment shown in fig. 1, and is not described here again.
Fig. 4 schematically shows a block diagram of a memory computing circuit array according to another embodiment of the present disclosure. The structure shown in fig. 4 is expanded by the memory computing circuit shown in fig. 2, and can support multiply-add operation with larger parallelism. Word lines WL [1] to WL [ n ] are used as first input sub-cells, source lines SL [1] to SL [ n ] are used as second input sub-cells, source lines SLB [1] to SLB [ n ] are used as third input sub-cells, and bit lines BL [1] to BL [ n ] are used as output cells. The circuit configuration in each dashed line frame constitutes a memory computation unit, which has inputs of word lines WL [1] to WL [ n ], a source line SL [ i ], and a source line SLB [ i ], i being 1, 2, … …, n, and an output of a bit line BL [ i ]. The working process is the same as that of the memory computing circuit in the embodiment shown in fig. 2, and is not described here again.
In conjunction with fig. 3 and 4, it can be seen that the structure of the memory computing circuit in the embodiment of the present disclosure is easily extended to support multiply-add operations with greater parallelism.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (8)
1. A memory computing circuit comprising a signal input unit (1), a first 1T1R unit (2), a second 1T1R unit (3), and an output unit (4), wherein:
the signal input unit (1) is configured to input a first voltage signal, a second voltage signal and a third voltage signal, the first voltage signal is used to drive the first 1T1R unit (2) and the second 1T1R unit (3), the second voltage signal is input to one end of the first 1T1R unit (2), the third voltage signal is input to one end of the second 1T1R unit (3), the first voltage signal corresponds to a first weight, or a combination of the second voltage signal and the third voltage signal corresponds to the first weight, wherein when the first voltage signal corresponds to the first weight, an electrical signal output by the output unit (4) is formed by dividing the second voltage signal and the third voltage signal by the first 1T1R unit (2) and the second 1T1R unit (3); when the combination of the second voltage signal and the third voltage signal corresponds to the first weight, the first voltage signal is at a high level, and the output unit (4) is precharged to a preset level;
the combination of the resistance value of the first 1T1R cell (2) and the resistance value of the second 1T1R cell (3) corresponds to a second weight value;
the output unit (4) is respectively connected with the other ends of the branch inputs of the first 1T1R unit (2) and the second 1T1R unit (3) and is used for outputting the electric signal, and the value of the electric signal corresponds to the product of the first weight and the second weight.
2. The circuit of claim 1, wherein the electrical signal is formed by pulling up, pulling down, or leaving the preset level unchanged by the second or third voltage signal.
3. The circuit of claim 1, wherein the predetermined level is an average of the second voltage signal and a third voltage signal.
4. The circuit according to claim 1, wherein the signal input unit (1) comprises:
a first input subunit (11) for inputting the first voltage signal to the first 1T1R cell (2) and the second 1T1R cell (3) to control the on/off of the transistors in the first 1T1R cell (2) and the second 1T1R cell (3);
a second input subunit (12) for inputting the second voltage signal;
a third input subunit (13) for inputting the third voltage signal.
5. The circuit of claim 1, wherein one of the second voltage signal and the third voltage signal is low and the other is high, and when the combination of the second voltage signal and the third voltage signal corresponds to the first weight, the first weight is 1 or-1.
6. The circuit of claim 1, wherein the first weight is 0 or 1 when the first voltage signal corresponds to the first weight.
7. The circuit of claim 1, wherein the first 1T1R cell (2) is cascode connected with a second 1T1R cell (3), the input cell (1) for inputting the first voltage signal to source terminals of the first 1T1R cell (2) and second 1T1R cell (3).
8. The circuit of claim 1, wherein the second weight is-1 when the resistance of the first 1T1R cell (2) is greater than the resistance of the second 1T1R cell (3), 0 when the resistance of the first 1T1R cell (2) is equal to the resistance of the second 1T1R cell (3), and 1 when the resistance of the first 1T1R cell (2) is less than the resistance of the second 1T1R cell (3).
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