CN111028755B - Single-stage GOA circuit and display device - Google Patents
Single-stage GOA circuit and display device Download PDFInfo
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- CN111028755B CN111028755B CN201911242065.6A CN201911242065A CN111028755B CN 111028755 B CN111028755 B CN 111028755B CN 201911242065 A CN201911242065 A CN 201911242065A CN 111028755 B CN111028755 B CN 111028755B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a single-stage GOA circuit and a display device, wherein the circuit comprises a plurality of transistors, first ends of the transistors are connected with a preset clock signal, second ends of the transistors are connected to a Q point, and third ends of the transistors are used as output ends to drive a plurality of rows of scanning lines respectively. According to the invention, the number of GOA units required by the panel assembly is reduced by a mode of driving a plurality of rows of scanning lines by a single group of GOA, so that the design requirement of a narrow frame is realized.
Description
Technical Field
The invention relates to the technical field of displays, in particular to a single-stage GOA circuit and a display device.
Background
The design principle of a conventional GOA (gate on array) circuit is similar to the form of a shift register, and referring to fig. 1-3, the GOA circuit can be abstracted into the following 4 parts, i.e., a pull-up unit, an output unit, a pull-down unit, and a pull-down maintaining unit. The output signal of the previous stage is fed back to the next stage to lift the potential of the Q point, so that the output of the next stage is realized; meanwhile, the next-stage signal is fed back to the previous stage, and the Q point and the Gate output signal are pulled down, so that the Gate of the scanning line is turned off. The current design forms of various GOA circuits can be classified into the four parts. As can be seen from the above description, 1 row of scan lines corresponds to 1 GOA output unit, and the switch is controlled by the GOA output unit. Namely, the number of Gate lines should be greater than or equal to the number of GOA-level pass cells.
Narrow borders have been an irreversible trend for the current panel industry. In order to realize narrow frames, most display products currently adopt the GOA scan line driving method, but for increasingly narrow frame requirements and large-size panels, the real-world panels produced by the conventional GOA method have difficulty in meeting the narrow frame requirements, and further optimization of the GOA circuit is required.
Disclosure of Invention
The invention provides a single-stage GOA circuit and a display device, and solves the problem that narrow frames are difficult to meet in the prior art.
The invention provides a single-stage GOA circuit which comprises a plurality of transistors, wherein first ends of the transistors are connected with a preset clock signal, second ends of the transistors are connected to a Q point, and third ends of the transistors are used as output ends to drive a plurality of rows of scanning lines respectively.
The single-stage GOA circuit further comprises a pull-up unit, a pull-down unit and a pull-down maintaining unit, wherein a first end of the pull-up unit is connected with a preset first feedback signal, a first end of the pull-down unit is connected with a preset second feedback signal, and a second end of the pull-up unit, a second end of the pull-down unit and a first end of the pull-down maintaining unit are all connected to the Q point.
In the single-stage GOA circuit of the present invention, the third terminal of the pull-down unit and the second terminal of the pull-down sustain unit are also connected to a predetermined power supply.
In the single-stage GOA circuit of the present invention, all of the transistors are TFTs.
The single-stage GOA circuit further comprises a plurality of grid control lines, and a plurality of transistors are arranged on the grid control lines respectively.
In the single-stage GOA circuit, the TFT is a top gate type TFT, and the plurality of gate control lines are bottom gate control lines.
In the single-stage GOA circuit, the TFT is a bottom gate type TFT, and the plurality of gate control lines are all top gate control lines.
In the single-stage GOA circuit of the invention, the single-stage GOA circuit is an nth-stage GOA circuit, and the Q point is an nth-stage QnPoint, multiple output ends are Gn、Gn+1、Gn+2、……Gn+mWherein m is the number of the plurality of output terminals.
In the single-stage GOA circuit of the present invention, the first feedback signal is a feedback signal of an n-1 th-stage GOA circuit, and the second feedback signal is a feedback signal of an n +1 th-stage GOA circuit.
In another aspect, the present invention further provides a display device, which includes the single-stage GOA circuit as described above.
The invention has the following beneficial effects:
the number of GOA units required by the panel assembly is reduced by a mode of driving a plurality of rows of scanning lines by a single group of GOA, so that the design requirement of a narrow frame is met.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a prior art single stage GOA circuit diagram;
FIG. 2 is a schematic diagram illustrating a frame occupation of a GOA circuit in the prior art;
FIG. 3 is a waveform diagram of the output of a single stage GOA circuit of the prior art;
fig. 4 is a circuit diagram of a single-stage GOA according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a frame occupation of a GOA circuit according to an embodiment of the present invention;
fig. 6 is a waveform diagram of an output of a single-stage GOA circuit according to an embodiment of the present invention.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Referring to fig. 4, fig. 4 is a circuit diagram of a single-stage GOA circuit according to an embodiment of the present invention, where the single-stage GOA circuit includes a plurality of transistors 1, first terminals of the transistors 1 are all connected to a predetermined clock signal, second terminals of the transistors 1 are all connected to a Q point, and third terminals of the transistors 1 are all used as output terminals to respectively drive a plurality of rows of scan lines. In addition, the single-stage GOA circuit further comprises a pull-up unit 2, a pull-down unit 3 and a pull-down maintaining unit 4, a first end of the pull-up unit 2 is connected to a preset first feedback signal, a first end of the pull-down unit 3 is connected to a preset second feedback signal, and a second end of the pull-up unit 2, a second end of the pull-down unit 3 and a first end of the pull-down maintaining unit 4 are all connected to the Q point. The third end of the pull-down unit 3 and the second end of the pull-down maintaining unit 4 are also connected to a preset power supply VGL. Where Vgl is the negative power input pin of the TFT panel and Vgh is the positive power input pin of the TFT panel.
Preferably, the single-stage GOA circuit further includes a plurality of gate control lines, and a plurality of transistors 1 are respectively disposed on the plurality of gate control lines. Wherein, a plurality of the transistors 1 are all TFTs.
With respect to the gate control line, the following two embodiments are provided:
in the first embodiment, the TFT is a top gate TFT, and the plurality of gate control lines are all bottom gate control lines.
In a second embodiment, the TFT is a bottom gate TFT, and the plurality of gate control lines are all top gate control lines.
Meanwhile, the single-stage GOA circuit is an nth-stage GOA circuit, and the Q point is an nth-stage QnPoint, multiple output ends are Gn、Gn+1、Gn+2、……Gn+mWherein m is the number of the plurality of output terminals. The first feedback signal is a feedback signal of the n-1 st-level GOA circuit, and the second feedback signal is a feedback signal of the n +1 st-level GOA circuit.
Fig. 4 shows an embodiment where m is 2, that is, an embodiment includes two TFTs, see fig. 5-6, and fig. 5 is a schematic diagram of a frame occupation of a GOA circuit provided in an embodiment of the present invention; fig. 6 is a waveform diagram of an output of a single-stage GOA circuit according to an embodiment of the present invention. The single-stage GOA unit of the invention has two output TFT switches T1/T2, two output switches correspond to 2 rows of scanning lines respectively, when Q point is opened, CK (clock signal) high level is written into, write high level into T1/T2 source, meanwhile, if take the top gate type TFT structure as an example, pass through two bottom gate control lines at T1/T2 respectively, Vbg1/Vbg2 respectively, because bottom gate potential (VLS) has effects of modulating TFT device Vth (threshold voltage) (VLS and Vth have proportional corresponding relation), when CK outputs high level, Vbg1 writes into high level at first, T1 is set as negative, G1 outputs; at this time, Vbg2 is negative, setting Vth at T2 to a positive value, and T2 is turned off. When the scan line needs to be turned off, the Vbg signal is a CK signal with a duty ratio of 50%, so that the scan line can be continuously pulled down. The rest is similar to the conventional GOA, and referring to fig. 5, compared to the conventional GOA design, the proposed method reduces the number of TFTs required for the GOA area by at least 50%, further reducing the frame width.
In addition to the above-mentioned 2 rows of scanning lines controlled by the GOA unit, the present invention can realize that a single GOA unit controls any row of scanning lines, and the method is the same as the above.
In addition, the invention also provides a display device which comprises the single-stage GOA circuit. That is, when the display device is implemented by the plurality of single-stage GOA circuits, if an embodiment including two TFTs in the single-stage GOA circuit is adopted, the number of TFTs required for the GOA region is reduced by at least 50%, and if an embodiment including more TFTs in the single-stage GOA circuit is adopted, the frame width can be further reduced.
Through the single-stage GOA circuit and the display device, the mode that a single group of GOA drives a plurality of rows of scanning lines is adopted, so that the number of GOA units required by a panel is reduced, and the design requirement of a narrow frame is met.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A single-stage GOA circuit is characterized by comprising a plurality of transistors, wherein first ends of the transistors are connected with a preset clock signal, top gates of the transistors are connected to a Q point, third ends of the transistors are used as output ends to drive a plurality of rows of scanning lines respectively, and the number of the output ends is m;
the transistor array substrate further comprises a plurality of grid control lines, and a plurality of transistors are arranged on the grid control lines respectively;
the pull-up unit, the pull-down unit and the pull-down maintaining unit are also included;
a plurality of the transistors are all TFTs;
the TFT is a double-gate TFT, and the gate control lines are all bottom gate control lines;
the Q point is a part where the second end of the pull-up unit, the second end of the pull-down unit and the first end of the pull-down maintaining unit are connected;
the bottom gate control line is a CK signal with the duty ratio of 1/m so as to drive a plurality of rows of scanning lines in a time-sharing mode.
2. The single-stage GOA circuit as recited in claim 1, wherein the first terminal of the pull-up unit is coupled to a predetermined first feedback signal, and the first terminal of the pull-down unit is coupled to a predetermined second feedback signal.
3. The single-stage GOA circuit as recited in claim 2, wherein the third terminal of the pull-down unit and the second terminal of the pull-down maintaining unit are further connected to a predetermined power supply.
4. The single-stage GOA circuit of claim 2, wherein the single-stage GOA circuit is an nth-stage GOA circuit, and the Q point is an nth-stage QnPoint, multiple output ends are Gn、Gn+1、Gn+2、……Gn+m。
5. The single-stage GOA circuit of claim 4, wherein the first feedback signal is a feedback signal of an n-1 stage GOA circuit, and wherein the second feedback signal is a feedback signal of an n +1 stage GOA circuit.
6. A single-stage GOA circuit is characterized by comprising a plurality of transistors, wherein first ends of the transistors are connected with a preset clock signal, bottom gates of the transistors are connected to a Q point, third ends of the transistors are used as output ends to drive a plurality of rows of scanning lines respectively, and the number of the output ends is m;
the transistor array substrate further comprises a plurality of grid control lines, and a plurality of transistors are arranged on the grid control lines respectively;
the pull-up unit, the pull-down unit and the pull-down maintaining unit are also included;
a plurality of the transistors are all TFTs;
the TFT is a double-gate TFT, and the gate control lines are all top gate control lines;
the Q point is a part where the second end of the pull-up unit, the second end of the pull-down unit and the first end of the pull-down maintaining unit are connected;
the top gate control line is a CK signal with the duty ratio of 1/m so as to drive a plurality of rows of scanning lines in a time-sharing mode.
7. The single-stage GOA circuit as recited in claim 6, wherein the first terminal of the pull-up unit is coupled to a predetermined first feedback signal, and the first terminal of the pull-down unit is coupled to a predetermined second feedback signal.
8. The single-stage GOA circuit of claim 7, wherein the third terminal of the pull-down unit and the second terminal of the pull-down maintaining unit are further connected to a predetermined power source.
9. The single-stage GOA circuit of claim 7, wherein the single-stage GOA circuit is an nth-stage GOA circuit, and the Q point is an nth-stage QnPoint, multiple output ends are Gn、Gn+1、Gn+2、……Gn+m。
10. The single-stage GOA circuit of claim 9, wherein the first feedback signal is a feedback signal of an n-1 GOA circuit, and wherein the second feedback signal is a feedback signal of an n +1 GOA circuit.
11. A display device comprising a single stage GOA circuit as claimed in any one of claims 1 to 10.
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| CN201911242065.6A CN111028755B (en) | 2019-12-06 | 2019-12-06 | Single-stage GOA circuit and display device |
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| CN201911242065.6A CN111028755B (en) | 2019-12-06 | 2019-12-06 | Single-stage GOA circuit and display device |
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| CN111028755B true CN111028755B (en) | 2022-07-12 |
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| CN111477190A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | GOA device and gate drive circuit |
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| CN107579077A (en) * | 2017-08-11 | 2018-01-12 | 上海天马有机发光显示技术有限公司 | A kind of display panel, its preparation method and display device |
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| JP2011135523A (en) * | 2009-12-25 | 2011-07-07 | Sony Corp | Drive circuit and display device |
| CN104157248A (en) * | 2014-05-08 | 2014-11-19 | 京东方科技集团股份有限公司 | Gate driving circuit, gate driving method and display device |
| CN108573667B (en) * | 2017-03-09 | 2019-11-15 | 合肥鑫晟光电科技有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN110415648A (en) * | 2019-07-16 | 2019-11-05 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
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Patent Citations (5)
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| CN107579077A (en) * | 2017-08-11 | 2018-01-12 | 上海天马有机发光显示技术有限公司 | A kind of display panel, its preparation method and display device |
| CN109427310A (en) * | 2017-08-31 | 2019-03-05 | 京东方科技集团股份有限公司 | Shift register cell, driving device, display device and driving method |
| CN108597430A (en) * | 2018-01-22 | 2018-09-28 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
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