CN111026573A - Watchdog system of multi-core processing system and control method - Google Patents
Watchdog system of multi-core processing system and control method Download PDFInfo
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Abstract
The invention provides a hardware watchdog system and a control method suitable for a mixed security level multi-core processing system. The watchdog system can independently monitor the task running condition of each processor core in the multi-core processor, and establishes effective fault isolation capability among different processor cores, so that when the processor core running a low-security level task breaks down, the normal running of a high-security level task is not influenced. The invention can provide more comprehensive monitoring capability for the multi-core processing system and limit the influence range of single processor core failure, thereby effectively improving the reliability of the multi-core processing system.
Description
Technical Field
The invention belongs to the field of embedded computer design, and particularly relates to a watchdog system and a control method suitable for a mixed security level multi-core processing system.
Background
In highly reliable embedded computers, hardware watchdog is typically used to monitor the task performance of the processor. The hardware watchdog is essentially a timer circuit. The task run by the processor periodically performs a count reset operation on the watchdog timer, commonly referred to as a "feed dog" operation. When the processor cannot continue to normally run its task due to some faults (for example, a program pointer enters a non-program area by mistake, or a software branch falls into a dead loop, etc.), the feeding operation cannot be performed regularly, the watchdog timer is not reset in time any more, and the watchdog timer counts to a timing end point to generate a corresponding output signal, which is generally called a "dog call" signal. The dog call signal typically generates a high priority watchdog interrupt to the processor or directly causes a processor reset.
The hardware watchdog monitors the task running state of the processor through the mechanism, so that the hardware watchdog can process errors or reset and restart in time, and the embedded computer is prevented from losing functions for a long time, so that the hardware watchdog is widely applied to the field of high-reliability embedded computers.
In recent years, the development of a single-core processor enters a bottleneck, the improvement of the performance cannot be brought about by only increasing the main frequency of the single-core processor, excessive heat is generated, and the cost performance of the high-frequency single-core processor is unacceptable. However, the integration of multiple processor cores in the same chip still can bring about a great increase in computing capability, and therefore, more and more computing systems adopt multi-core processors as the computing cores. In some complex high-reliability embedded computing systems, due to the demands for reducing the size, the weight and the power consumption, tasks of different security levels originally running on a plurality of computers or a plurality of single-core processors need to be concentrated into the same multi-core processor to run. This allows tasks of multiple different security levels to run simultaneously on the same multi-core processor. Generally, these tasks with different security levels are respectively run in different processor cores of the multi-core processor.
The traditional hardware watchdog mechanism is designed based on a single-core processor, can only monitor the task running condition of one processor core, and cannot comprehensively monitor the task running conditions of a plurality of processor cores in the multi-core processor. In recent years, with the increasingly widespread use of multi-core processors, practitioners have begun to research watchdog monitoring mechanisms applied to the multi-core processors, such as "CN 201610827586.8 a hardware watchdog control method and system based on a multi-core system", and so on. However, the common point of these new designs is that a hardware watchdog is used to monitor the operation status of all processor cores together by using the inter-processor core communication, and when any processor core crashes or cannot normally perform the inter-core communication, the watchdog sends out a dog call signal to interrupt or reset the whole multi-core processor. There are two disadvantages to this new design: 1. the watchdog cannot individually monitor the operation condition of each processor core and cannot master the respective task operation state of each processor core in the multi-core processor; 2. the method is not suitable for a multi-core processor running the mixed security level task, and when a processor core running the low security level task breaks down, the watchdog is called to interrupt/reset (or the broken processor core may carry out unexpected illegal access to the watchdog, so that the watchdog breaks down), so that the normal running of the high security level task is influenced, and the method is not acceptable in a mixed security level task system. In a task system with mixed safety levels, fault isolation is required to be carried out among tasks with different safety levels, and the fault of the task with low safety level cannot influence the normal operation of the task with high safety level.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a watchdog system and a control method suitable for a mixed security level multi-core processing system, which solve the problems of the current multi-core processing system watchdog design, can monitor the respective task running condition of each processor core in a multi-core processor in real time, is suitable for the multi-core processor running a mixed security level task, and cannot influence the normal running of a high security level task when the processor core running a low security level task fails.
The technical scheme of the invention is as follows:
a watchdog system adapted for use in a hybrid security level multi-core processing system, comprising:
the multi-core processor comprises n processor cores, namely a processor core A and a processor core B … … processor core X;
a programmable logic device, which contains n watchdog timers, namely a watchdog timer A and a watchdog timer B … …, and 1 reset control circuit inside;
n-1 storage spaces, namely storage space B … … storage space X;
the processor core A in the multi-core processor is used for accessing the programmable logic device; the watchdog timer A and the watchdog timer B … … respectively monitor the corresponding processor core A and the processor core B … … processor core X; memory space B … … memory space X is accessed by the corresponding processor core B … … processor core X, respectively, all of which are accessed by processor core a.
The reset control circuit sends a reset signal outwards when the watchdog timer A sends out a dog call signal or the processor core A sends out a reset command, so that the whole system is reset.
A watchdog system control method suitable for a mixed security level multi-core processing system adopts a watchdog system, and the control method comprises the following steps: the processor core A directly accesses the watchdog timer A corresponding to the processor core A to perform dog feeding, timing duration configuration, enabling and prohibiting operations, the processor core B … … processor core X cannot directly access the watchdog timer corresponding to the processor core, but writes required watchdog operation information into a storage space corresponding to the processor core, and writes watchdog operation heartbeat count, the processor core A periodically inquires the storage space of the processor core B … … processor core X to obtain the required watchdog operation information and the required watchdog operation heartbeat count, and when the heartbeat count is confirmed to be updated, the processor core A performs the operation of the watchdog timer corresponding to the processor core; in addition, the processor core a also obtains the current state of each watchdog timer periodically, and writes the current state of the watchdog timer B … … watchdog timer X into the storage space of the corresponding processor core, and then the processor core B … … processor core X can know the current state of the watchdog timer from the corresponding storage space.
When a certain watchdog timer is not timely fed with a dog operation, the watchdog timer sends out a dog call signal; when there is a dog call signal, there are two interrupt reporting modes: in the first mode, each watchdog timer transmits a corresponding dog call interrupt signal to a corresponding processor core in a mode of processor external interrupt, and each processor core only receives the dog call interrupt of the watchdog timer corresponding to the processor core; in the second mode, when the watchdog timer A calls, the processor core A is informed in a mode of external interruption of the processor, and when other watchdog timers call, the processor core A regularly acquires the state of the watchdog and then informs the corresponding processor core through inter-core interruption.
The invention has the advantages and effects that:
the hardware watchdog system is applied to a multi-core processing system and has two outstanding advantages:
1. the watchdog can independently monitor the task running condition of each processor core in the multi-core processor;
2. when the watchdog is applied to a multi-core processing system with mixed security level, the influence range of single processor core fault is limited, and stronger fault isolation capability is established between processor cores running different security level tasks, so that when the processor core running a low security level task fails, the normal running of a high security level task is not influenced. The fault isolation capability is mainly characterized by the following characteristics:
a) when the processor cores B, … … and X which run the tasks with lower security level fail, even if unexpected accesses are sent outwards, the normal operation of the watchdog corresponding to other processor cores cannot be influenced;
b) when watchdog timers corresponding to the processor cores B and … … and the processor core X which run the tasks with lower security level generate a dog call, the interrupt of the watchdog timers only informs the processor core which generates the exception, and other processor cores are not influenced;
c) when the processor cores B, … … and X running the tasks with lower safety level fail, the whole system is not reset. When the processor core A running the task with the highest safety level fails, the system is reset.
The hardware watchdog and the control method thereof are suitable for the mixed security level multi-core processing system, can provide more comprehensive monitoring capability for a plurality of processor cores of the multi-core processor, limit the influence range of the faults of the single processor core, and establish effective fault isolation among the processor cores. The invention can provide effective guarantee for the reliability of the mixed security level multi-core processing system.
Drawings
Fig. 1 is a schematic diagram of the watchdog system according to the present invention (a first interrupt reporting mode is adopted).
Fig. 2 is a schematic diagram of the watchdog system according to the present invention (interrupt reporting mode two).
Detailed Description
The hardware watchdog system is formed by adopting the programmable logic device, the multi-core processor and the storage space of each processor core. The invention uses a programmable logic device (usually FPGA) to realize a hardware watchdog circuit, and uses a shared memory space among a plurality of processor cores of a multi-core processor to realize a watchdog control method.
The watchdog system includes:
the multi-core processor comprises n processor cores, namely a processor core A and a processor core B … … processor core X;
a programmable logic device, which contains n watchdog timers, namely a watchdog timer A and a watchdog timer B … …, and 1 reset control circuit inside;
n-1 storage spaces, namely storage space B … … storage space X;
the processor core A in the multi-core processor is used for accessing the programmable logic device; the watchdog timer A and the watchdog timer B … … respectively monitor the corresponding processor core A and the processor core B … … processor core X; memory space B … … memory space X is accessed by the corresponding processor core B … … processor core X, respectively, all of which are accessed by processor core a.
The reset control circuit sends a reset signal outwards when the watchdog timer A sends out a dog call signal or the processor core A sends out a reset command, so that the whole system is reset.
The mechanism of the present invention is shown in FIG. 1. The multi-core processor is provided with n processor cores, namely a processor core A, processor cores B and … … and a processor core X. Among the tasks with the mixed security level, the task with the highest security level runs on the processor core A, and the task with the lower security level runs on other processor cores. The hardware watchdog circuit is realized in the programmable logic device and comprises n watchdog timers A, B, … … and X respectively, and each watchdog timer monitors the task running condition of the corresponding processor core. In addition, the hardware watchdog circuit also comprises a reset control circuit used for generating a reset signal. Only processor core a may directly access all of the watchdog circuitry and other processor cores may not be allowed to directly access the watchdog circuitry. The other processor cores can access the watchdog timer corresponding to the other processor cores through the agent of the processor core A. And allocating a corresponding memory space (memory spaces B, … … and X) for the processor cores B, … … and X respectively for carrying out watchdog operation. The processor cores B, … … and X running the tasks with lower security level can only access the watchdog operation storage space corresponding to the processor cores, while the processor core A running the task with highest security level has the highest access authority and can access the watchdog operation storage space corresponding to other processor cores. (Note: the access privilege of a particular processor core to a particular address space is defined by the higher management privilege configuration program and cannot be changed by the lower management privilege operating system or application program.)
The processor core A can directly access the watchdog timer A corresponding to the processor core A, and carry out operations such as dog feeding, timing duration configuration, enabling, forbidding and the like on the watchdog timer A. The other processor cores cannot directly access the watchdog timer corresponding to the other processor cores, but write the required watchdog operation information (dog feeding, timing duration configuration, enabling, disabling, and the like) into the storage space corresponding to the processor core, and write the watchdog operation heartbeat count (each time of operation, the heartbeat count is increased by 1 to mark that the operation is a new operation). The processor core A periodically inquires the storage space of other processor cores to obtain the watchdog operation information and the heartbeat count of the operation required by the processor core A, and when the heartbeat count is confirmed to be updated, the agent performs the operation of the watchdog timer corresponding to the processor core. The processor core a not only periodically performs the agent watchdog operation, but also periodically obtains the current state of each watchdog timer (whether to be dog called, the number of times of the dog called, etc.), and writes the current state of the watchdog timers B, … …, X into the watchdog operation storage space of the corresponding processor core. Then, the processor core can acquire the current state of the watchdog timer from the corresponding memory space.
Through the mode, the processor core A can directly access the watchdog timer A corresponding to the processor core A, and other processor cores can also indirectly access the watchdog timer corresponding to the processor cores. The task performance of each processor core is individually monitored by a corresponding watchdog timer. Processor core a may also be aware of the current operating conditions of all processor cores.
When the tasks of other processor cores except the processor core A are abnormal in operation and the watchdog feeding operation cannot be carried out in time, the corresponding watchdog timer can count to the end point to generate a dog call signal. When the task of the processor core A is abnormal in operation and various watchdog operations cannot be carried out in time, all watchdog timers count to the end point and generate a dog call signal. When a watchdog is called, there are two interrupt reporting modes: as shown in fig. 1, each watchdog timer transmits a corresponding dog call interrupt signal to a corresponding processor core in a processor external interrupt manner, and each processor core only receives the dog call interrupt of the watchdog timer corresponding to the processor core; in the second mode, as shown in fig. 2, when the watchdog timer a calls, the processor core a is notified in an external interrupt mode of the processor, and when other watchdog timers call, the processor core a periodically learns the status of the watchdog, and then notifies the corresponding processor core through inter-core interrupt. When the number of processor cores in the multi-core processor is small and the number of external interrupts is enough, reporting the watchdog interrupt by adopting a first mode; when the number of processor cores in the multi-core processor is large and the number of external interrupts is insufficient, the watchdog interrupt reporting can be performed in a second mode.
The reset control circuit of the watchdog outwards initiates reset signals under two conditions: 1. when the processor core A running the task with the highest safety level is abnormal and the watchdog timer A makes a dog call, the reset control circuit automatically initiates a reset signal (the reset control circuit can also be set to initiate reset when the watchdog timer A makes a plurality of dog calls so as to tolerate a certain degree of transient abnormality); 2. when the processor core A learns that other processor cores are seriously abnormal through the states of the watchdog timers and needs the whole processing system to carry out whole reset, the processor core A actively orders the reset control circuit to initiate a reset signal.
In the invention, only the processor core A running the task with the highest security level can directly access the watchdog circuit, while the processor cores B, … … and X running the tasks with lower security levels cannot directly access the watchdog circuit and only can directly access the respective watchdog operation storage space. The access authority of the specific processor core to the specific address space is limited by the configuration program with higher management authority and cannot be changed by the operating system or the application program with lower management authority. Therefore, even if the processor cores B, … … and processor core X fail and initiate unexpected accesses to the outside, these accesses do not directly access the watchdog circuit (at most access the watchdog operation memory space corresponding to the failed processor core), and thus cannot cause unexpected influence on the watchdog timers corresponding to other processor cores. Therefore, effective fault isolation is established among different processor cores, and when the processor cores B, … … and the processor core X have faults, the normal operation of the watchdog corresponding to other processor cores is not influenced. When the processor core A fails, the watchdog of other processor cores can be influenced, but because the task operated by the processor core A is the highest security level, the task does not violate the requirement that the task with the low security level in the hybrid security level task system cannot be influenced by the task with the high security level.
Through the scheme, the hardware watchdog system can be used for individually monitoring the task running condition of each processor core in the multi-core processor, and effectively limiting the influence range of the single processor core fault. The processor cores have stronger fault isolation capability, and when the processor cores B, … … and X which operate tasks with lower security level have faults, the normal operation of the watchdog corresponding to other processor cores can not be influenced even if unexpected access is sent outwards. When the watchdog timer corresponding to the processor cores B, … … and X generates a dog call, the interrupt is only notified to the processor core with the exception, and the other processor cores are not affected. When the processor cores B, … … and X running the tasks with lower safety level fail, the whole system is not reset. When the processor core A running the task with the highest safety level fails, the system is reset. In addition, when the processor core A judges that other current processor cores are seriously abnormal, the system is initiatively reset under the condition of not influencing the task with the highest security level. When the processor core A fails, the normal operation of other processor cores and watchdog timers thereof can be influenced, but the fault does not violate the requirement that the low-safety-level task cannot influence the high-safety-level task in a mixed safety-level task system.
Therefore, the watchdog is suitable for the multi-core processor running the mixed security level tasks, strong fault isolation capability is established among the different security level tasks, and when the processor core running the low security level task breaks down, normal running of the high security level task is not affected.
The invention is suitable for the multi-core processor which simultaneously runs a plurality of tasks with different security levels. By applying the design, the respective task running condition of each processor core in the multi-core processor can be independently monitored, and effective fault isolation capability is established among the processor cores running tasks with different safety levels. When the processor core running the low-security level task fails, the normal running of the high-security level task is not affected.
Firstly, a watchdog control method of a processor core A running a highest security level task is as follows:
1. after the multi-core processing system is started, clearing watchdog operation information, watchdog state information and watchdog operation heartbeat count in the storage spaces B and … … and the storage space X, and setting corresponding clear-clearing completion marks after clearing is completed;
2. initializing a watchdog timer A (configuring and enabling timing duration);
3. regularly feeding the watchdog timer A to prevent the watchdog timer A from generating a dog call;
4. periodically inquiring watchdog operation information and corresponding watchdog operation heartbeat counts in the storage spaces B and … … and the storage space X;
5. if the heartbeat count of the watchdog operation is updated, the agent executes the corresponding watchdog operation (performs the required operation on the watchdog timer corresponding to the storage space);
6. regularly inquiring the watchdog states of the watchdog timers B and … … and the watchdog timer X, and writing the state information into the corresponding storage spaces B and … … and the storage space X.
Secondly, the method for controlling the watchdog by other processor cores running tasks with lower security level is as follows:
1. after the multi-core processing system is started, inquiring a watchdog operation storage space corresponding to the processor core, confirming that watchdog operation information, watchdog state information and watchdog operation heartbeat count are all cleared, and confirming that a clear clearing completion flag is set to be effective;
2. operating a storage space for a watchdog corresponding to the processor core, writing watchdog timer initialization operation (timing duration configuration and enabling), and updating corresponding watchdog operation heartbeat count;
3. periodically operating a storage space for a watchdog corresponding to the processor core, writing watchdog feeding operation, and updating corresponding watchdog operation heartbeat count;
4. and periodically reading the state information of the watchdog in the watchdog operation storage space corresponding to the processor core, and acquiring the current state of the watchdog timer corresponding to the processor core.
Thirdly, the working mode of each watchdog timer is as follows:
1. after the enabling, starting timing counting, wherein the timing duration is a preset value;
2. when the dog is fed, the timing count is reset;
3. if the dog is not fed in time, the timing count reaches the preset timing duration, and a dog calling signal is sent out;
4. after the dog is called, the timer is reset, a new counting cycle is restarted, if the dog is not fed in time, the timing counting reaches the timing duration again, the dog calling signal can be sent out repeatedly, and the cycle is repeated.
And fourthly, the interruption mechanism adopts a mode one, and after each watchdog calls, the interruption reporting working mode is as follows:
1. after each watchdog dog calls, each corresponding processor core is interrupted through an external interrupt signal;
2. and after receiving the external interrupt of the corresponding watchdog, the processor core carries out interrupt processing.
And fifthly, when the interrupt mechanism adopts the second mode, after each watchdog calls, the interrupt reporting working mode is as follows:
the dog call processing mode of the watchdog timer A is as follows:
1. after the watchdog timer A generates a dog call, the processor core A is interrupted through an external interrupt signal;
2. and after receiving the external interrupt of the watchdog, the processor core A carries out interrupt processing.
The method for processing other watchdog timers for the dog call is as follows:
1. other watchdog timers except the watchdog timer a generate a dog call;
2. the processor core A periodically inquires the watchdog states of the watchdog timers B and … … and the watchdog timer X to know that a certain watchdog timer generates a dog call;
3. the processor core A informs a corresponding processor core which generates a watchdog call through inter-core interruption;
4. and after receiving the inter-core interrupt, the corresponding processor core carries out interrupt processing.
Sixthly, the reset control circuit of the watchdog works as follows:
1. when the watchdog timer A makes a dog call, the reset control circuit automatically initiates a reset signal (or can be set to initiate reset when the watchdog timer A makes multiple dog calls so as to tolerate a certain degree of transient abnormality);
2. when the processor core A actively sends a reset command to the reset control circuit, the reset control circuit sends a reset signal.
Claims (4)
1. A watchdog system adapted for use in a hybrid security level multi-core processing system, comprising:
the multi-core processor comprises n processor cores, namely a processor core A and a processor core B … … processor core X;
a programmable logic device, which contains n watchdog timers, namely a watchdog timer A and a watchdog timer B … …, and 1 reset control circuit inside;
n-1 storage spaces, namely storage space B … … storage space X;
the processor core A in the multi-core processor is used for accessing the programmable logic device; the watchdog timer A and the watchdog timer B … … respectively monitor the corresponding processor core A and the processor core B … … processor core X; memory space B … … memory space X is accessed by the corresponding processor core B … … processor core X, respectively, all of which are accessed by processor core a.
2. The watchdog system of claim 1, wherein: the reset control circuit sends a reset signal outwards when the watchdog timer A sends out a dog call signal or the processor core A sends out a reset command, so that the whole system is reset.
3. A watchdog system control method suitable for a mixed security level multi-core processing system, which adopts the watchdog system of claim 1 or 2, and is characterized in that the control method comprises the following steps: the processor core A directly accesses the watchdog timer A corresponding to the processor core A to perform dog feeding, timing duration configuration, enabling and prohibiting operations, the processor core B … … processor core X cannot directly access the watchdog timer corresponding to the processor core, but writes required watchdog operation information into a storage space corresponding to the processor core, and writes watchdog operation heartbeat count, the processor core A periodically inquires the storage space of the processor core B … … processor core X to obtain the required watchdog operation information and the required watchdog operation heartbeat count, and when the heartbeat count is confirmed to be updated, the processor core A performs the operation of the watchdog timer corresponding to the processor core; in addition, the processor core a also obtains the current state of each watchdog timer periodically, and writes the current state of the watchdog timer B … … watchdog timer X into the storage space of the corresponding processor core, and then the processor core B … … processor core X can know the current state of the watchdog timer from the corresponding storage space.
4. The watchdog system control method of claim 3, wherein: when a certain watchdog timer is not timely fed with a dog operation, the watchdog timer sends out a dog call signal; when there is a dog call signal, there are two interrupt reporting modes: in the first mode, each watchdog timer transmits a corresponding dog call interrupt signal to a corresponding processor core in a mode of processor external interrupt, and each processor core only receives the dog call interrupt of the watchdog timer corresponding to the processor core; in the second mode, when the watchdog timer A calls, the processor core A is informed in a mode of external interruption of the processor, and when other watchdog timers call, the processor core A regularly acquires the state of the watchdog and then informs the corresponding processor core through inter-core interruption.
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| CN112463430A (en) * | 2020-12-03 | 2021-03-09 | 哲库科技(北京)有限公司 | Crash information storage method and medium for multi-core system, and electronic device |
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| CN114416408A (en) * | 2021-12-13 | 2022-04-29 | 飞腾信息技术有限公司 | Interrupt processing method and device |
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