CN111026515B - State monitoring device, task scheduler and state monitoring method - Google Patents

State monitoring device, task scheduler and state monitoring method Download PDF

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CN111026515B
CN111026515B CN201811178883.XA CN201811178883A CN111026515B CN 111026515 B CN111026515 B CN 111026515B CN 201811178883 A CN201811178883 A CN 201811178883A CN 111026515 B CN111026515 B CN 111026515B
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task
job
current
current task
processor
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CN111026515A (en
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请求不公布姓名
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Shanghai Cambricon Information Technology Co Ltd
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Shanghai Cambricon Information Technology Co Ltd
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Priority to PCT/CN2019/110273 priority patent/WO2020073938A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The utility model provides a state monitoring device, task dispatcher and state monitoring method, this state monitoring device includes task registration circuit, check circuit and state processing circuit, and task registration circuit, check circuit and state processing circuit are electric connection in proper order, and check circuit and state processing circuit all are connected to the second treater, and state processing circuit still is connected to first treater. The state monitoring device, the task scheduler, the state monitoring method and the storage medium can realize real-time monitoring of the task execution information of the second processor.

Description

State monitoring device, task scheduler and state monitoring method
Technical Field
The present disclosure relates to the field of computer applications, and in particular, to a state monitoring device, a task scheduler, and a state monitoring method.
Background
With the development of artificial intelligence technology, deep learning is ubiquitous and indispensable nowadays, and artificial intelligence processors are increasingly applied to various scenes such as mobile terminals, servers and the like. In practical applications of the artificial intelligence processor, the artificial intelligence processor is generally a coprocessor serving as a general purpose processor, and thus the general purpose processor serving as a main processor needs to be capable of monitoring the operation state of the artificial intelligence processor in real time so as to realize cooperative control over the artificial intelligence processor. The conventional processor monitoring device is often used for monitoring whether the processor has abnormal operation or not by detecting parameters such as voltage or current in the operation process of the processor, and the function of the processor monitoring device is single.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a state monitoring device and a task scheduler that can monitor a task processing process of a second processor in real time, thereby enriching functions of the state monitoring device.
The state monitoring device comprises a task registration circuit, a checking circuit and a state processing circuit, wherein the task registration circuit, the checking circuit and the state processing circuit are electrically connected in sequence, the checking circuit and the state processing circuit are connected to a second processor, and the state processing circuit is also connected to a first processor; wherein,,
the task registration circuit is used for receiving a task registration request of a current task and distributing task identifiers for the current task according to the task registration request of the current task, wherein the current task with the obtained task identifiers can be scheduled and executed;
the checking circuit is used for obtaining the total number of the jobs contained in the current task and the job receiving number of the second processor; generating an assignment completion instruction according to the total number of the jobs and the job receiving number of the second processor;
the state processing circuit is connected with the first processor, and is used for receiving the job ending information of each job of the current task according to the dispatching completion instruction and transmitting the job ending information of each job of the current task to the first processor.
In one embodiment, the verification circuitry includes a comparator;
the comparator is configured to obtain a job receiving number and a preset job number of the second processor, and generate the dispatch completion instruction when the job receiving number of the second processor is equal to the preset job number.
In one embodiment, the preset number of jobs is the total number of jobs;
alternatively, the preset number of jobs is 2 n Wherein the value range of n is 5-10, n is a positive integer, and the preset number of jobs is smaller than the total number of jobs.
In one embodiment, the state processing circuit includes a state buffer circuit, the state buffer circuit connecting the verification circuit and the first processor;
the state buffer circuit is used for receiving the job ending information of each job of the current task, re-ordering the received job ending information according to a preset arrangement mode when the number of the received job ending information reaches the number of the preset ending information, and transmitting the received job ending information to the first processor according to the re-ordered sequence.
In one embodiment, the state processing circuitry further comprises exception processing circuitry;
the abnormality processing circuit is used for receiving the job ending information of the current job, judging whether the current task has an execution abnormality according to the job ending information of the current job, and generating a task destruction instruction when the current task has the execution abnormality.
In one embodiment, the execution exception of the current task includes a first exception condition and a second exception condition, and the task destruction instruction includes a first task destruction instruction and a second task destruction instruction;
the abnormality processing circuit is used for generating a first task destruction instruction according to the current operation ending information when the first abnormality condition exists in the current task according to the operation ending information of the current operation so as to destroy the current task; when the second abnormal condition exists in the current task according to the task ending information of the current task, generating a second task destroying instruction according to the current task ending information so as to destroy the current task and all tasks after the current task.
In one embodiment, when the current task has a pre-task, the task registration circuit is further configured to receive a task query request of the pre-task, and assign a task identifier to the current task according to the task registration request of the current task after determining that the pre-task is performed according to the task query request of the pre-task.
A task scheduler comprising a task assigning device and a status monitoring device connected with the task assigning device; the task assigning device and the state monitoring device are both connected to the second processor, and the state monitoring device can also be connected to the first processor;
the task assigning device is used for sending a task registration request of a current task to the state monitoring device;
the task registration circuit is used for receiving a task registration request of the current task, distributing a task identifier for the current task according to the task registration request of the current task, and transmitting the task identifier obtained by registration to the task dispatching device;
the task assigning device is further used for sending the decomposition information of the current task and all task information to the second processor according to the received task identification of the current task, and sending the decomposition information of the current task to the checking circuit;
the second processor is used for processing the second processor according to the decomposition information of the current task and the total task information, and transmitting the job receiving number of the second processor to the checking circuit;
The checking circuit is used for obtaining the total number of the jobs contained in the current task according to the decomposition information of the current task, receiving the job receiving number of the second processor, and generating an assignment completion instruction according to the total number of the jobs and the job receiving number of the second processor;
the state processing circuit is used for receiving and caching the job ending information of each job of the current task according to the received dispatching completion instruction, and transmitting the job ending information of each job of the current task to the first processor.
A method of condition monitoring, the method comprising the steps of:
receiving a task registration request of a current task, and distributing task identifiers for the current task according to the task registration request of the current task, wherein the current task with the obtained task identifiers can be scheduled and executed;
obtaining the total number of jobs contained in the current task and the job receiving number of the second processor;
generating an assignment completion instruction according to the total number of the jobs contained in the current task and the job receiving number of the second processor;
and receiving the job end information of each job of the current task according to the dispatching completion instruction, and transmitting the job end information of each job of the current task to a first processor.
In one embodiment, the step of generating the dispatch completion instruction according to the total number of jobs contained in the current task and the number of jobs received by the second processor further comprises:
and when the number of the received jobs of the second processor is equal to the preset number of jobs, generating the dispatching completion instruction.
In one embodiment, the preset job number is the total number of jobs contained in the current task;
alternatively, the preset number of jobs is 2 n The value range of n is 5-10, n is a positive integer, and the preset job number of the verification unit is smaller than the total job number contained in the current task.
In one embodiment, before the step of transmitting the job end information of each job of the current task to the first processor, the method further includes the steps of:
when the number of the received job ending information reaches the number of the preset ending information, reordering the received job ending information according to a preset arrangement mode, and transmitting the received job ending information to the first processor according to the reordered sequence.
In one embodiment, the method further comprises the steps of:
Receiving job end information of a current job;
judging whether the current task has an execution abnormality according to the task ending information of the current task, and generating a task destruction instruction when the current task has the execution abnormality.
In one embodiment, the method further comprises the steps of:
when the first abnormal condition of the current task is determined according to the task ending information of the current task, generating a first task destroying instruction according to the current task ending information so as to destroy the current task;
when the second abnormal condition exists in the current task according to the task ending information of the current task, generating a second task destroying instruction according to the current task ending information so as to destroy the current task and all tasks after the current task.
According to the state monitoring device, the task scheduler and the state monitoring method, the dispatching completion instruction can be generated according to the total number of the tasks contained in the current task and the job receiving number of the second processor, at this time, the state monitoring device can receive the job ending information of each job of the current task and transmit the job ending information of each job of the current task to the first processor, so that the task execution information of the second processor can be monitored in real time, and the functions of the state monitoring device are enriched.
Drawings
FIG. 1 is an application scenario diagram of a condition monitoring device in one embodiment;
FIG. 2 is a block diagram of an application scenario of a condition monitoring apparatus in one embodiment;
FIG. 3 is a block diagram of the architecture of a task scheduler in one embodiment;
FIG. 4 is a block diagram of the architecture of a second processor body in one embodiment;
FIG. 5 is a block diagram of a second processor architecture according to another embodiment;
FIG. 6 is a block diagram of a second processor architecture according to yet another embodiment;
FIG. 7 is a flow chart of a method of status monitoring in one embodiment;
FIG. 8 is a flow chart of a status monitoring method according to another embodiment;
FIG. 9 is a flow chart of an anomaly monitoring method according to one embodiment;
fig. 10 is a flowchart of an anomaly monitoring method according to another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
As shown in fig. 1 to 3, the condition monitoring apparatus 100 of the embodiment of the present application may be connected to a first processor 200 and a second processor 300, where the first processor 200 may be a general-purpose processor such as a CPU, and the second processor 300 may be used as a coprocessor of the first processor 200. Specifically, the second processor 300 may include a second processor body and a control device for controlling the operation of the second processor body, where the second processor body may be an IPU (Intelligence Processing Unit, intelligent processor) or an NPU (Neural-network Process Unit, neural network processor) or the like. Of course, in other embodiments, the second processor body may be a general purpose processor such as a CPU or GPU.
Further, the number of the second processor bodies may be plural, and the plural second processor bodies are connected to the control device of the second processor body. Alternatively, the second processor body may also comprise a plurality of core processors, each core processor being connected to the control means of the second processor body. The condition monitoring apparatus 100 may be connected to a control apparatus of a second processor body capable of transmitting task execution information of the second processor body to the condition monitoring apparatus 100.
The condition monitoring apparatus 100 may be connected to a global memory, which may be connected to the first processor 200, through DMA (Direct Memory Access ). Alternatively, the global Memory may be DRAM (Dynamic Random Access Memory ) or SRAM (Static Random-Access Memory), or the like. Further, the state monitoring device 100 can store the obtained task execution information of the second processor 300 to the global memory, so that the first processor 200 can obtain the task execution information of the second processor 300 through the global memory, so as to realize the monitoring of the task execution information of the second processor 300 by the state monitoring device 100.
In one embodiment, as shown in fig. 4, the second processor body may include a controller unit 310 and an operation unit 320, wherein the controller unit 310 is connected to the operation unit 320, and the operation unit 320 may include a master processing circuit 321 and a plurality of slave processing circuits 322, and the master processing circuit 321 and the slave processing circuits 322 form a master-slave structure. Optionally, the controller unit 310 is used for acquiring data and calculating instructions. The data may include machine learning data in particular, alternatively the machine learning data may be neural network data. The controller unit 310 is further configured to parse the acquired calculation instruction to obtain an operation instruction, and send a plurality of operation instructions and data to the main processing circuit. The master processing circuit 321 is configured to perform preamble processing on data and operation instructions transferred between the master processing circuit 321 and the plurality of slave processing circuits 322. The plurality of slave processing circuits 322 are configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit 321 to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master processing circuit 321; the main processing circuit 321 is further configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction.
Alternatively, the controller unit 310 may include an instruction cache unit 311, an instruction processing unit 312, and a store queue unit 314; the instruction cache unit 311 is used for storing computing instructions associated with machine learning data; the instruction processing unit 312 is configured to parse the calculation instruction to obtain a plurality of operation instructions; store queue unit 314 is configured to store an instruction queue comprising: a plurality of arithmetic instructions or calculation instructions to be executed in the order of the queue. Optionally, the controller unit 310 may further include a dependency relationship processing unit 313, configured to determine whether a first operation instruction has an association relationship with a zeroth operation instruction before the first operation instruction when there are a plurality of operation instructions, if the first operation instruction has an association relationship with the zeroth operation instruction, then cache the first operation instruction in the instruction storage unit, and after the execution of the zeroth operation instruction is completed, extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit. Specifically, if the dependency relationship processing unit 313 extracts the first storage address interval of the required data (for example, the matrix) in the first operation instruction according to the first operation instruction, extracts the zeroth storage address interval of the required matrix in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have overlapping areas, it is determined that the first operation instruction and the zeroth operation instruction have an association relationship, if the first storage address interval and the zeroth storage address interval do not have overlapping areas, it is determined that the first operation instruction and the zeroth operation instruction do not have an association relationship.
In one embodiment, as shown in fig. 5, the arithmetic unit 320 may further include one or more branch processing circuits 323, wherein the one or more branch processing circuits 323 are connected to the master processing circuit 321, and each branch processing circuit 323 is connected to more than one slave processing circuit 322. The branch processing circuit 323 is configured to execute data or instructions that are forwarded between the master processing circuit 321 and the slave processing circuit 322. In this embodiment, the main processing circuit 321 is specifically configured to determine that the input neuron is broadcast data, the weight is distribution data, and distribute the distribution data into a plurality of data blocks, and send at least one data block of the plurality of data blocks, the broadcast data, and at least one operation instruction of the plurality of operation instructions to the branch processing circuit; the branch processing circuit 323 is used for forwarding data blocks, broadcast data and operation instructions between the master processing circuit 321 and the plurality of slave processing circuits 322; the plurality of slave processing circuits 322 are configured to perform operations on the received data blocks and weights according to the operation instruction to obtain intermediate results, and transmit the intermediate results to the branch processing circuits 323; the main processing circuit 321 is further configured to perform subsequent processing on the intermediate result sent by the branch processing circuit to obtain a result of the calculation instruction, and send the result of the calculation instruction to the controller unit.
In an alternative embodiment, as shown in fig. 6, the operation unit 320 may include one master processing circuit 321 and a plurality of slave processing circuits 322. Wherein the plurality of slave processing circuits 322 are distributed in an array; each of the slave processing circuits 322 is connected to the adjacent other slave processing circuits 322, and the master processing circuit 321 is connected to k slave processing circuits among the plurality of slave processing circuits, the k slave processing circuits being: the K slave processing circuits shown in fig. 6 include only the n slave processing circuits in the 1 st row, the n slave processing circuits in the m th row, and the m slave processing circuits in the 1 st column, that is, the K slave processing circuits are slave processing circuits directly connected to the master processing circuit among the plurality of slave processing circuits. The K slave processing circuits are used for forwarding data and instructions between the master processing circuit and the plurality of slave processing circuits.
Optionally, the main processing circuit may further include one or any combination of a conversion processing circuit, an activation processing circuit, and an addition processing circuit; wherein the conversion processing circuit is configured to perform an exchange (e.g., a conversion of continuous data and discrete data) between the first data structure and the second data structure on the data block or intermediate result received by the main processing circuit; or to perform an exchange between the first data type and the second data type (e.g., a conversion of a fixed point type and a floating point type) on the data block or intermediate result received by the main processing circuit; the activation processing circuit is used for executing the activation operation of the data in the main processing circuit; the addition processing circuit is used for executing addition operation or accumulation operation.
Further, the slave processing circuit includes a multiplication processing circuit; the multiplication processing circuit is used for executing product operation on the received data blocks to obtain a product result. Still further, the slave processing circuit may further include a forwarding processing circuit for forwarding the received data block or the product result, and an accumulation processing circuit for performing an accumulation operation on the product result to obtain the intermediate result.
The processor provided by the application sets the operation unit 320 to be in a master multi-slave structure, and for the calculation instruction of forward operation, the processor can split data according to the calculation instruction of forward operation, so that the parallel operation can be performed on a part with larger calculation amount through a plurality of slave processing circuits, the operation speed is improved, the operation time is saved, and the power consumption is further reduced.
Optionally, the machine learning calculation may specifically include: the artificial neural network operation, the input data may specifically include: neuron data and weight data are input. The calculation result may specifically be: and outputting the neuron data as a result of the artificial neural network operation.
The operation in the neural network can be one-layer operation in the neural network, and in the multi-layer neural network, the implementation process is that in the forward operation, after the execution of the artificial neural network of the upper layer is completed, the operation instruction of the lower layer can take the output neuron calculated in the operation unit as the input neuron of the lower layer to perform operation (or perform certain operations on the output neuron and then take the operation as the input neuron of the lower layer), and meanwhile, the weight is replaced by the weight of the lower layer; in the backward operation, when the backward operation of the artificial neural network of the previous layer is completed, the next-layer operation instruction performs an operation with the input neuron gradient calculated by the operation unit as the output neuron gradient of the next layer (or performs some operations on the input neuron gradient and then uses the operation as the output neuron gradient of the next layer), and simultaneously replaces the weight with the weight of the next layer.
The machine learning computation may also include support vector machine operations, k-nearest neighbor (k-nn) operations, k-means (k-means) operations, principal component analysis operations, and the like. For convenience of description, a specific scheme of machine learning calculation is described below by taking an artificial neural network operation as an example.
For the artificial neural network operation, if the artificial neural network operation has multiple layers of operation, the input neurons and the output neurons of the multiple layers of operation do not refer to the neurons in the input layer and the neurons in the output layer of the whole neural network, but for any two adjacent layers in the network, the neurons in the lower layer of the forward operation of the network are the input neurons, and the neurons in the upper layer of the forward operation of the network are the output neurons. Taking convolutional neural networks as an example, let a convolutional neural network have L layers, k=1, 2,..l-1, for the K-th layer and the K + 1-th layer, we refer to the K-th layer as the input layer, where the neurons are the input neurons, the k+1-th layer as the output layer, where the neurons are the output neurons. That is, each layer except the topmost layer can be used as an input layer, and the next layer is a corresponding output layer.
In one embodiment, as shown in fig. 2 and 3, the status monitoring apparatus 100 may include a task registration circuit 110, a verification circuit 120, and a status processing circuit 130, where the task registration circuit 110, the verification circuit 120, and the status processing circuit 130 are electrically connected in sequence. The task registration circuit 110 may be connected to the task assigning means 400, the verification circuit and the state processing circuit 130 may be connected to the second processor 300, and the state processing circuit 130 may be further connected to the first processor 200.
The task registration circuit 110 is configured to receive a task registration request of a current task, and assign a task identifier to the current task according to the task registration request of the current task, where the task identifier may be used to distinguish different tasks. Specifically, the task registration circuit 110 may be further connected to the task assigning device 400 of the task scheduler, where the task assigning device 400 may send a registration request of the current task to the task registration circuit 110, and the task registration circuit 110 may assign a task identifier to the current task according to the task registration request received by the task registration circuit 110, so as to complete registration of the current task. The task registration circuit 110 may transmit the task identification of the current task to the task assigning device 400, and the current task having obtained the task identification can be scheduled by the task assigning device 400 and transmitted to the second processor 300 for processing.
The checking circuit 120 may be connected to the second processor 300, where the checking circuit 120 is configured to obtain the total number of jobs included in the current task and the number of jobs received by the second processor, and generate an dispatch completion instruction according to the total number of jobs of the current task and the number of jobs received by the second processor. Wherein the current task may comprise a plurality of jobs.
Optionally, after the task registration circuit 110 completes registration of the current task, the task assigning device 400 may determine the decomposition information of the current task and transmit the decomposition information of the current task to the task registration circuit 110, and the task registration circuit 110 may obtain the total number of jobs included in the current task according to the decomposition information of the current task and transmit the total number of jobs included in the current task to the verification circuit 120. Further, the task assigning device 400 may be further connected to the second processor 300, where the task assigning device 400 may further send the decomposition information and all task information of the current task to the second processor 300, specifically, the task assigning device 400 may send the decomposition information and all task information of the current task to a control device of the second processor body, and the control device of the second processor body may split the current task into a plurality of jobs according to the decomposition information and all task information of the current task received by the control device of the second processor body, and send the plurality of jobs to each second processor body for processing, so as to process the plurality of jobs of the current task in parallel, thereby improving the processing efficiency of the current task. The check circuit 120 can thus obtain the number of job receptions of the second processor transmitted by the control device of the second processor body, and specifically, the check circuit can obtain the number of job receptions of the second processor transmitted by the control device of the second processor body in real time.
Thereafter, the check circuit 120 may generate a dispatch completion instruction indicating that the second processor 300 has received all jobs sent by the task dispatcher 400 based on the total number of jobs for the current task and the number of job receptions for the second processor. It should be clear that, in the embodiment of the present application, the resolution information of the task refers to information such as the total number of jobs included in the task and the size of each job. All task information for a task may include computer instructions, input data, and configuration information for the task's task category. The task categories may include: block (blocking task), cluster (cluster task) and unit (normal task).
The state processing circuit 130 is configured to receive job end information of each job of the current task according to the received dispatch completion instruction, and transmit the job end information of each job of the current task to the first processor 200. Specifically, when the state processing circuit 130 receives the dispatch completion instruction, the state monitoring device 100 may wait for the execution state information of each received job fed back by the second processor 300, that is, the state processing circuit 130 may start receiving and buffering the job end information of each job in the current task transmitted by the second processor 300. Alternatively, the state processing circuit 130 may be connected to the global memory through DMA, so that the state processing circuit 130 may write the job end information of each job obtained by the state processing circuit into the global memory to transfer the job end information of each job of the current task to the first processor 200 through the global memory.
Alternatively, the task registration circuit 110 may be a storage device, where a state table is stored in the storage device, where the state table includes a plurality of state table entries, and each state table entry corresponds to a task identifier. Specifically, each task registration request may occupy a state table entry, and a storage address or a reference number of the state table entry may be used as a task identifier of the task. In other embodiments, the task registration circuitry 110 can employ other storage devices such as stacks. Further, each state entry may include multiple sub-state entries, and task registration circuitry 110 may assign each task a sub-state entry based on the total number of tasks for the current task. For example, the task identifier corresponding to the current task may be a Table ID, where the Table ID is used to represent the current task. If the current task registration is completed, a sub-state Table item corresponding to the Table ID may be allocated to each job according to the arrangement mode of the jobs in the queue.
Further, when the current task has a pre-task, the task registration circuit 110 is further configured to receive a task query request of the pre-task, and assign a task identifier to the current task according to the task registration request of the current task after determining that the pre-task is performed according to the task query request of the pre-task. The pre-task of the current task refers to a task executed before the current task, and the execution of the current task requires the execution result of the pre-task, that is, the current task and the pre-task have a dependency relationship.
Specifically, the task registration circuit 110 may be further connected to a state processing circuit 130, and when the state processing circuit 130 receives job end information of all jobs of a task, a task completion signal may be generated and stored. Further, the task assigning apparatus 400 may determine a preset data dependency relationship to determine whether a pre-task exists in the current task. If the current task has a pre-task, that is, the execution of the current task needs to depend on the execution result of the pre-task, the task assigning device 400 may send a task query request to the task registration circuit 110 of the state monitoring device 100 to query whether the pre-task of the current task is executed. If the task registration circuit 110 stores the task completion signal of the previous task, it indicates that the previous task of the current task has been executed, and at this time, the task registration circuit 110 may assign a task identifier to the current task according to the task registration request received by the task registration circuit 110. If the front-end task of the current task is determined to be not executed, the task registration circuit allocates a task identifier for the current task according to the received task registration request after waiting for the front-end task of the current task to be executed.
Optionally, a task completion signal of each task may also be stored in a state table entry corresponding to the task identifier of the task, where the task completion signal may be implemented by using a check bit. For example, if the check bit corresponding to the task is 1, it indicates that the task registration circuit 110 has received a task completion signal of the task, and the task has been completed. If the check bit corresponding to the task is 0, the task registration circuit is indicated that the task completion signal of the task is not received yet, and the task is not executed yet.
Alternatively, as shown in fig. 3, the verification circuit 120 may include a comparator 121, where the comparator 121 is configured to obtain the job receiving number of the second processor and the preset job number, compare the job receiving number of the second processor with the preset job number, and when the job receiving number of the second processor is equal to the preset job number, the comparator 121 may output an assignment completion instruction and send the assignment completion instruction to the state processing circuit 130.
Alternatively, the preset job number in the embodiment of the present application may be the total number of jobs that are tasks. At this time, the comparator 121 is configured to determine whether the job reception number of the second processor is equal to the job total number of the current task, and when the job reception number of the second processor is equal to the job total number of the current task, the comparator 121 may generate a dispatch completion instruction and transmit the dispatch completion instruction to the state processing circuit 130. And if the job receiving number of the second processor is smaller than the job total number of the current task, continuing waiting until the job receiving number of the second processor is equal to the job total number of the task.
Optionally, in other embodiments, since each task includes a plurality of jobs, in order to reduce the number of jobs checked at a time, and improve the execution efficiency of the jobs, the preset number of jobs may also be smaller than the total number of jobs of the current task. Specifically, the preset number of operations of the comparator 121 may be 2 n Wherein, the value range of n is 5-10, and n is a positive integer. For example, the preset number of jobs may be 32, 64, 128, 512, 1024, or the like, and is not particularly limited herein.
For example, the preset job number is 128, and the comparator 121 is configured to determine whether the job receiving number of the second processor is equal to 128, and when the job receiving number of the second processor is equal to 128, the comparator 121 may generate a dispatch completion instruction and transmit the dispatch completion instruction to the state processing circuit 130. Meanwhile, the job receiving number of the second processor can be cleared to perform the next cycle of processing. If the job receiving number of the second processor is less than 128, continuing to wait until the job receiving number of the second processor is equal to 128.
Further, the preset job number may be dynamically set according to the job number of the current task. At this time, when the comparator 121 determines that the number of received jobs of the second processor is equal to the preset number of jobs, the comparator 121 may generate a dispatch completion instruction and transmit the dispatch completion instruction to the state processing circuit 130. If the number of received jobs of the second processor is smaller than the preset number of jobs, the waiting is continued until the number of received jobs of the second processor is equal to the preset number of jobs of the comparator 121.
Optionally, the state processing circuit 130 further includes a state buffer circuit 132, where the state buffer circuit 132 may connect the checking circuit 120 and the first processor 200, and in particular, the state buffer circuit 132 may be connected to the first processor 200 through a global memory. The state buffer circuit 132 is configured to receive the dispatch completion instruction output by the comparator of the check circuit 120, receive the job end information of each job of the current task according to the dispatch completion instruction, reorder the received job end information according to a preset permutation mode when the number of received job end information reaches the preset end information number, and transmit the received job end information to the first processor 200 according to the reordered order. Alternatively, the preset arrangement may be an execution order of the respective jobs. Thus, by reordering the job end information of each job, it is possible to ensure that one or more jobs before the current job have all been executed and ended, and thus it is possible to ensure the reliability of the execution result of the current task.
In one embodiment, the state processing circuit 130 further includes an exception handling circuit 131, the exception handling circuit 131 being capable of monitoring for abnormal execution of the respective tasks. Specifically, the exception handling circuit 131 is connected to the state buffer circuit 132 described above, and the exception handling circuit 131 may also be connected to the second processor 300. The exception handling circuit 131 may obtain job end information of the current job through the status buffer circuit 132, and determine whether there is an execution exception for the current task to which the current job belongs according to the job end information of the current job. And if the current task has abnormal execution, generating a task destruction instruction. Alternatively, the job end information of the current job includes result flag data, and the exception processing circuit 131 may determine whether there is an execution exception for the current task according to the result flag data included in the job end information of the current job.
For example, if there is an execution abnormality in the current task, the control device of the second processor body may set the result flag data in the job end information of the current job to be non-0 (e.g., the result flag data is 1), and at this time, the abnormality processing circuit 131 may determine that there is an execution abnormality in the current task according to the result flag data. If there is no execution abnormality in the current task, the control device of the second processor body may set the result flag data in the job end information of the current job to 0, and at this time, the abnormality processing circuit 131 may determine that there is no execution abnormality in the current task according to the result flag data.
Further, the execution abnormality of the current task may include a first abnormality and a second abnormality, and the task destruction instruction may include a first task destruction instruction corresponding to the first abnormality and a second task destruction instruction corresponding to the second abnormality. Alternatively, when it is determined that the current task has an abnormality, the abnormality processing circuit 131 may also determine whether the execution abnormality of the current task is a first abnormality or a second abnormality, based on abnormality flag data included in the job end information of the current job.
For example, if the execution exception of the current task is a first exception condition, the control device of the second processor body may set the exception flag data in the job end information of the current job to be non-0 (e.g., the exception flag data is 1). If the execution abnormality of the current task is a second abnormality, the control device of the second processor body may set the abnormality flag data in the job end information of the current job to 0. In this way, the abnormality processing circuit 131 can determine whether the execution abnormality of the current task is the first abnormality or the second abnormality based on the abnormality flag data included in the job end information of the current job. The first exception condition and the second exception condition may be one or a combination of a plurality of exceptions such as an exception condition of insufficient resources of the second processor 300 and a failure of the second processor 300.
Alternatively, if the exception handling circuit 131 determines that the current task has the first exception condition according to the job end information of the current job, a first task destruction instruction is generated according to the job end information of the current job to destroy the current task. Specifically, if the exception handling circuit 131 determines that the current task has a first exception condition according to the job end information of the current job, then a first task destruction instruction is generated according to the job end information of the current job, and the first task destruction instruction is transmitted to the task assigning device 400, so as to inform the task assigning device 400 to destroy the current task. That is, the task assigning device can destroy all the jobs in the Table ID corresponding to the current task according to the first task destruction instruction received by the task assigning device.
If the exception handling circuit 131 determines that the current task has the second exception condition according to the job ending information of the current job, a second task destroying instruction is generated according to the job ending information of the current job so as to destroy the current task and all tasks after the current task. Specifically, if the exception handling circuit 131 determines that the current task has a second exception condition according to the job end information of the current job, a second task destruction instruction may be generated according to the job end information of the current job, and the second task destruction instruction may be transmitted to the task assigning apparatus 400, so as to inform the task assigning apparatus 400 to destroy the current task and all the tasks thereafter. Alternatively, the task assigning apparatus 400 may store the plurality of tasks to be scheduled in a task queue in a certain order, and after the task assigning apparatus 400 receives the second task destruction instruction transmitted by the exception processing circuit 131, the task assigning apparatus 400 may destroy all the tasks in the task queue to which the current task belongs.
Further, the abnormality processing circuit of the state monitoring apparatus 100 may also transmit the current task execution abnormality information obtained by its detection to the first processor 200. For example, when the exception handling circuitry determines that the current task has a first exception condition, the exception handling circuitry may report the first exception condition to the first processor 200. When the exception handling circuitry determines that the current task has a second exception condition, then the exception handling circuitry may report the second exception condition to the first processor 200.
Further, the exception handling circuit of the state monitoring apparatus 100 may generate an interrupt signal according to the obtained execution exception information of the current task, and transmit the interrupt signal to the first processor 200 to inform the end of the execution of the current task of the first processor 200.
By setting the exception handling mechanism for the exception handling circuit to execute, the accuracy of the task execution result can be ensured. And when an abnormal condition exists, the state monitoring device can inform the task dispatching device to destroy the corresponding task or all the tasks after the corresponding task, so that resource waste caused by the fact that the second processor continues to execute other tasks when the abnormal condition exists is avoided.
Further, when the exception handling circuit 131 determines that the current task has an exception, the exception handling circuit 131 may also transmit exception information for the current task to the first processor. For example, when exception handling circuitry 131 determines that a first exception condition exists for the current task, then exception handling circuitry 131 may report the first exception condition to the first processor. When the exception handling circuit 131 determines that the current task has a second exception condition, then the exception handling circuit 131 may report the second exception condition to the first processor.
Meanwhile, as shown in fig. 3, the embodiment of the present application further provides a task scheduler, which is connected between the first processor 200 and the second processor 300, and is used for scheduling tasks and monitoring task execution information of the second processor 300. Specifically, the task assigning apparatus 400 may include a task decomposing apparatus 410 and a task scheduling apparatus 420, wherein the task decomposing apparatus 410 is used to determine task decomposing information of a current task, and the task scheduling apparatus 420 is used to determine scheduling information of the current task.
Specifically, the condition monitoring apparatus 100 may include a task registration circuit 110, a verification circuit 120, and a condition processing circuit 130. The task assigning means 400 is for transmitting a task registration request of a current task to the state monitoring means 100. The task registration circuit 110 is configured to receive a task registration request of a current task, allocate a task identifier for the current task according to the task registration request of the current task, and transmit the task identifier obtained by registration to the task assigning device 400.
The checking circuit 120 is configured to obtain the total number of jobs included in the current task and the number of job receptions of the second processor, and generate an assignment completion instruction according to the total number of jobs included in the current task and the number of job receptions of the second processor. The state processing circuit 130 is configured to receive and buffer job end information of each job of the current task according to the received dispatch completion instruction, and transmit the job end information of each job of the current task to the first processor 200.
In this embodiment, the state monitoring device 100 may be the state monitoring device 100 in any of the above embodiments, and the specific structure and the working process of the state monitoring device 100 may be referred to the above description, which is not repeated here.
The working principle of the task scheduler according to the embodiment of the present application is illustrated below with reference to fig. 1 and 3:
when a task needs to be sent to the second processor 300 for processing, the task is first registered. Specifically, the task assigning device 400 may transmit a task registration request of the current task to the state monitoring device 100. Task registration circuitry 110 of condition monitoring device 100 may assign a task identification to the current task and communicate the task identification to task assigning device 400.
The task assigning apparatus 400 may obtain task decomposition information of the current task according to the received task identification of the current task, and transmit the decomposition information of the current task to the state monitoring apparatus 100. The task registration circuit 110 of the state monitoring apparatus 100 may obtain the total number of jobs of the current task according to the decomposition information of the current task, and transmit the total number of jobs of the current task to the verification circuit 120.
Further, the task assigning device 400 may further send the decomposition information and all task information of the current task to the second processor 300, specifically, the task assigning device 400 may send the decomposition information and all task information of the current task to the control device of the second processor body, and the control device of the second processor body may split the current task into a plurality of jobs according to the decomposition information and all task information of the current task received by the control device of the second processor body, and send the plurality of jobs to each second processor body for processing. The check circuit 120 can thus obtain the number of job receptions of the second processor transmitted by the control device of the second processor body, and specifically, the check circuit can obtain the number of job receptions of the second processor transmitted by the control device of the second processor body in real time.
During the scheduling process of the current task, the verification circuit 120 of the state monitoring device 100 can determine whether the current task is equal to the preset number of jobs in real time. The preset job number may be the total number of jobs contained in the current task, or may be smaller than the total number of jobs contained in the current task, for example, the preset job number is 2 n Wherein the value range of n is 5-10, n is a positive integer, and the preset job number is smaller than the total number of jobs contained in the current task. When the check circuit 120 determines that the number of job receptions of the second processor is equal to the preset number of jobs, then a dispatch completion instruction may be generated.
After obtaining the dispatch completion instruction, the state monitoring device 100 may wait for the execution state information of each received job fed back by the second processor 300, i.e., the state processing circuit 130 of the state monitoring device 100 may begin receiving and buffering the job end information of each job in the current task transmitted by the second processor 300. Further, the state processing circuit 130 may further determine whether the current task has an execution abnormality according to the job end information of the current job received by the state processing circuit. If the current task has abnormal execution, the state processing circuit 130 may also generate a task destruction instruction according to the task end information of the current task.
For example, if the state processing circuit 130 determines that the current task has the first abnormal condition according to the job end information of the current job, then a first task destruction instruction is generated according to the job end information of the current job, and the first task destruction instruction is transmitted to the task assigning device 400, so as to inform the task assigning device 400 to destroy the current task. If the state processing circuit 130 determines that the current task has the second abnormal condition according to the job end information of the current job, a second task destruction instruction may be generated according to the job end information of the current job, and the second task destruction instruction may be transmitted to the task assigning device 400, so as to inform the task assigning device 400 to destroy the current task and all the tasks after the current task.
If the state processing circuit 130 determines that the current task has no abnormal condition according to the job end information of the current task, the state processing circuit 130 may write the obtained job end information of each job into the global memory, so as to transmit the job end information of each job of the current task to the first processor 200 through the global memory.
In an embodiment, as shown in fig. 7, the embodiment of the present application further provides a state monitoring method, which can be applied to the state monitoring device of any one of the foregoing embodiments, so as to implement monitoring of the second processor. Specifically, the method comprises the following steps:
s100, receiving a task registration request of a current task, and distributing task identifiers for the current task according to the task registration request of the current task, wherein the current task with the obtained task identifiers can be scheduled and processed.
Specifically, the task registration circuit 110 of the state monitoring device 100 may receive the task registration request of the current task sent by the task assigning device 400, assign a task identifier to the current task, and transmit the task identifier to the task assigning device 400, where the task identifier may be used to distinguish different tasks.
S200, obtaining the total number of jobs contained in the current task and the job receiving number of the second processor. Specifically, the state monitoring apparatus 100 may obtain the total number of jobs of the current task from the decomposition information of the current task, and the state monitoring apparatus 100 may obtain the job reception number of the second processor from the second processor 300.
And S300, generating an assignment completion instruction according to the total number of the jobs contained in the current task and the job receiving number of the second processor.
S400, receiving and caching the job end information of each job of the current task according to the dispatching completion instruction, and transmitting the job end information of each job of the current task to the first processor 200.
Specifically, after obtaining the dispatch completion instruction, the status monitoring device 100 may wait for the execution status information of each received job fed back by the second processor 300. For example, state processing circuitry 130 may begin receiving and buffering job end information for each of the jobs in the current task transmitted by second processor 300. Alternatively, the state processing circuit 130 may be connected to the global memory through DMA, so that the state processing circuit 130 may write the job end information of each job obtained by the state processing circuit into the global memory to transfer the job end information of each job of the current task to the first processor 200 through the global memory.
Optionally, as shown in fig. 8, the step S300 further includes:
s310, generating an allocation completion instruction when the number of job receiving operations of the second processor is equal to the preset number of job receiving operations. Alternatively, the preset job number may be the total number of jobs contained in the current task. Alternatively, the preset number of jobs may be smaller than the total number of jobs contained in the current task, for example, the preset number of jobs of the comparator 121 is 2 n Wherein, the value range of n is 5-10, and n is a positive integer. Thus, the number of single checks of the comparator 121 can be reduced, and the operation efficiency can be improved. For example, the preset number of jobs may be 32, 64, 128, 512, 1024, or the like, and is not particularly limited herein.
When it is determined that the number of jobs received by the second processor is equal to the preset number of jobs, the verification circuitry 120 may generate a dispatch completion instruction and transmit the dispatch completion instruction to the state processing circuitry 130. If the job receiving number of the second processor is smaller than the preset job number, continuing to wait until the job receiving number of the second processor is equal to the preset job number.
Optionally, the step S400 further includes the following steps:
s410, when the number of the received job ending information reaches the number of the preset ending information, the received job ending information is reordered according to the preset arrangement mode, and the job ending information of each job is transmitted to the first processor 200 according to the reordered sequence. Alternatively, the preset arrangement may be an execution order of the respective jobs. Thus, by reordering the job end information of each job, it is possible to ensure that one or more jobs before the current job have all been executed and ended, and thus it is possible to ensure the reliability of the execution result of the current task.
Of course, in other embodiments, the status monitor apparatus 100 may not reorder the job end information of each job of the current task. At this time, when the status monitor 100 receives the job end information of the current job, the status monitor 100 may transmit the job end information of the current job to the first processor 200.
Optionally, the state monitoring device 100 may also monitor whether an abnormal situation exists during the task execution process. Specifically, as shown in fig. 9, the method further includes the following steps:
s500, receiving job end information of a current job; specifically, when the second processor 300 completes execution of the current job, the second processor 300 may transmit job end information of the current job to the status monitoring apparatus 100.
S510, judging whether the current task has abnormal execution or not according to the task ending information of the current task. Specifically, the state monitoring apparatus 100 may determine whether or not there is an execution abnormality of the current task to which the current job belongs, based on the job end information of the current job.
S520, generating a task destruction instruction if the current task has abnormal execution. And if the current task does not have the execution abnormality, continuing to execute other jobs of the current task. If there is no abnormality in the current task, the job end information of the next job may be continuously received, and at this time, the above steps S510 to S520 may be repeated.
Alternatively, the job end information of the current job includes result flag data, and the state monitoring apparatus 100 may determine whether the current task has an abnormal execution according to the result flag data included in the job end information of the current job. For example, if there is an execution abnormality in the current task, the control device of the second processor body may set the result flag data in the job end information of the current job to be non-0 (e.g., the abnormality flag data is 1), and at this time, the abnormality processing circuit of the state monitoring device 100 may determine that there is an execution abnormality in the current task according to the result flag data. If the current task has no execution abnormality, the control device of the second processor body may set the result flag data in the job end information of the current job to 0, and at this time, the abnormality processing circuit may determine that the current task has no execution abnormality according to the result flag data.
Optionally, the execution exception of the current task includes a first exception condition and a second exception condition, and the task destruction instruction includes a first task destruction instruction and a second task destruction instruction. Specifically, as shown in fig. 10, when it is determined that the current task has an abnormal situation, the method further includes the following steps:
S521, judging whether the execution abnormality of the current task is the first abnormality according to the task ending information of the current task. If the job end information of the current task determines that the current task has the first abnormal condition, step S522 is executed to generate a first task destruction instruction according to the job end information of the current task, so as to destroy the current task. If the job ending information of the current task determines that the current task has the second abnormal condition, step S523 is executed to generate a second task destroying instruction according to the job ending information of the current task, so as to destroy the current task and all tasks after the current task.
For example, if the execution exception of the current task is a first exception condition, the control device of the second processor body may set the exception flag data in the job end information of the current job to be non-0 (e.g., the exception flag data is 1). If the execution abnormality of the current task is a second abnormality, the control device of the second processor body may set the abnormality flag data in the job end information of the current job to 0. In this way, the abnormality processing circuit can determine whether the execution abnormality of the current task is the first abnormality or the second abnormality based on the abnormality flag data included in the job end information of the current job.
If the exception handling circuit determines that the current task has a first exception condition according to the job ending information of the current job, a first task destroying instruction is generated according to the job ending information of the current job, and the first task destroying instruction is transmitted to the task assigning device 400, so that the task assigning device 400 is notified to destroy the current task. If the exception handling circuit determines that the current task has a second exception condition according to the job end information of the current job, a second task destruction instruction may be generated according to the job end information of the current job, and the second task destruction instruction may be transmitted to the task assigning device 400, so as to inform the task assigning device 400 to destroy the current task and all the tasks after the current task. Alternatively, the task assigning apparatus 400 may store a plurality of tasks to be scheduled in a queue in a certain order, and after the task assigning apparatus 400 receives the second task destruction instruction transmitted by the exception processing circuit 131, the task assigning apparatus 400 may destroy all the tasks in the queue.
Further, the abnormality processing circuit of the state monitoring apparatus 100 may also transmit the current task execution abnormality information obtained by its detection to the first processor 200. For example, when the exception handling circuitry determines that the current task has a first exception condition, the exception handling circuitry may report the first exception condition to the first processor 200. When the exception handling circuitry determines that the current task has a second exception condition, then the exception handling circuitry may report the second exception condition to the first processor 200.
Further, the exception handling circuit of the state monitoring apparatus 100 may generate an interrupt signal according to the obtained execution exception information of the current task, and transmit the interrupt signal to the first processor 200 to inform the end of the execution of the current task of the first processor 200.
It should be understood that, although the steps in the flowcharts of fig. 7-10 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 7-10 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
According to the state monitoring device, the task scheduler and the state monitoring method, the dispatching completion instruction can be generated according to the total number of the tasks contained in the current task and the job receiving number of the second processor, at this time, the state monitoring device can receive the job ending information of each job of the current task and transmit the job ending information of each job of the current task to the first processor, so that the task execution information of the second processor can be monitored in real time, and the functions of the state monitoring device are enriched.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (12)

1. The state monitoring device is characterized by comprising a task registration circuit, a checking circuit and a state processing circuit, wherein the task registration circuit, the checking circuit and the state processing circuit are sequentially and electrically connected, the checking circuit and the state processing circuit are both connected to a second processor, and the state processing circuit is also connected to a first processor; wherein,,
the task registration circuit is used for receiving a task registration request of a current task and distributing task identifiers for the current task according to the task registration request of the current task, wherein the current task with the obtained task identifiers can be scheduled and executed;
the checking circuit is used for obtaining the total number of the jobs contained in the current task and the job receiving number of the second processor; generating an assignment completion instruction according to the total number of the jobs of the current task and the job receiving number of the second processor;
the state processing circuit is connected with the first processor and is used for receiving the job ending information of each job of the current task according to the dispatching completion instruction and transmitting the job ending information of each job of the current task to the first processor;
The state processing circuit comprises a state buffer circuit which is connected with the checking circuit and the first processor;
the state buffer circuit is used for receiving the job ending information of each job of the current task, re-ordering the received job ending information according to a preset arrangement mode when the number of the received job ending information reaches the number of the preset ending information, and transmitting the received job ending information to the first processor according to the re-ordered sequence.
2. The condition monitoring device of claim 1, wherein the verification circuit comprises a comparator;
the comparator is configured to obtain a job receiving number and a preset job number of the second processor, and generate the dispatch completion instruction when the job receiving number of the second processor is equal to the preset job number.
3. The condition monitoring device according to claim 2, wherein the preset number of jobs is the total number of jobs;
alternatively, the preset number of jobs is 2 n Wherein the value range of n is 5-10, n is a positive integer, and the preset number of jobs is smaller than the total number of jobs.
4. A condition monitoring device according to any one of claims 1 to 3, wherein the condition processing circuit further comprises an exception handling circuit;
the abnormality processing circuit is used for receiving the job ending information of the current job, judging whether the current task has an execution abnormality according to the job ending information of the current job, and generating a task destruction instruction when the current task has the execution abnormality.
5. The state monitoring device according to claim 4, wherein the execution abnormality of the current task includes a first abnormality and a second abnormality, and the task destruction instruction includes a first task destruction instruction and a second task destruction instruction;
the abnormality processing circuit is used for generating a first task destruction instruction according to the operation ending information of the current operation when the first abnormality condition exists in the current task according to the operation ending information of the current operation so as to destroy the current task; when the second abnormal condition exists in the current task according to the task ending information of the current task, generating a second task destroying instruction according to the current task ending information so as to destroy the current task and all tasks after the current task.
6. A state monitoring device according to any one of claims 1 to 3, wherein, when the current task has a pre-task, the task registration circuit is further configured to receive a task query request of the pre-task, and assign a task identifier to the current task according to the task registration request of the current task after determining that the pre-task is performed according to the task query request of the pre-task.
7. A task scheduler, characterized in that the task scheduler comprises a task dispatching device and a state monitoring device connected with the task dispatching device; the task assigning device and the state monitoring device are both connected to the second processor, and the state monitoring device can also be connected to the first processor; the state monitoring device comprises a task registration circuit, a checking circuit and a state processing circuit;
the task assigning device is used for sending a task registration request of a current task to the state monitoring device;
the task registration circuit is used for receiving a task registration request of the current task, distributing a task identifier for the current task according to the task registration request of the current task, and transmitting the task identifier obtained by registration to the task dispatching device;
The task assigning device is further used for obtaining task decomposition information of the current task according to the received task identification of the current task, sending the decomposition information of the current task and all task information to the second processor, and sending the decomposition information of the current task to the checking circuit;
the second processor is used for processing the second processor according to the decomposition information of the current task and the total task information, and transmitting the number of received jobs of the second processor to the checking circuit;
the checking circuit is used for obtaining the total number of the jobs contained in the current task according to the decomposition information of the current task, receiving the job receiving number of the second processor, and generating an assignment completion instruction according to the total number of the jobs and the job receiving number of the second processor;
the state processing circuit is used for receiving and caching the job ending information of each job of the current task according to the received dispatching completion instruction, and transmitting the job ending information of each job of the current task to the first processor.
8. A method of condition monitoring, the method comprising the steps of:
Receiving a task registration request of a current task, and distributing task identifiers for the current task according to the task registration request of the current task, wherein the current task with the obtained task identifiers can be scheduled and executed;
obtaining the total number of jobs contained in the current task and the job receiving number of the second processor;
generating an assignment completion instruction according to the total number of the jobs contained in the current task and the job receiving number of the second processor;
receiving the job end information of each job of the current task according to the dispatching completion instruction, and transmitting the job end information of each job of the current task to a first processor;
before the step of transmitting job end information of each job of the current task to the first processor, the method further includes:
when the number of the received job ending information reaches the number of the preset ending information, reordering the received job ending information according to a preset arrangement mode, and transmitting the received job ending information to the first processor according to the reordered sequence.
9. The method of claim 8, wherein generating a dispatch completion instruction based on the total number of jobs included in the current task and the number of job receptions by the second processor further comprises:
And when the number of the received jobs of the second processor is equal to the preset number of jobs, generating the dispatching completion instruction.
10. The status monitoring method according to claim 9, wherein the preset job number is a total number of jobs included in the current task;
alternatively, the preset number of jobs is 2 n Wherein the value range of n is 5-10, n is a positive integer, and the preset job number of the verification unit is smaller than the total job number contained in the current task.
11. The condition monitoring method according to claim 8, further comprising the steps of:
receiving job end information of a current job;
judging whether the current task has an execution abnormality according to the task ending information of the current task, and generating a task destruction instruction when the current task has the execution abnormality.
12. The condition monitoring method according to claim 11, further comprising the steps of:
when the first abnormal condition of the current task is determined according to the task ending information of the current task, a first task destroying instruction is generated according to the task ending information of the current task so as to destroy the current task;
When the second abnormal condition exists in the current task according to the task ending information of the current task, a second task destroying instruction is generated according to the current task ending information so as to destroy the current task and all tasks behind the current task.
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