CN111017869B - Silicon-based network structure and preparation method thereof - Google Patents
Silicon-based network structure and preparation method thereof Download PDFInfo
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- CN111017869B CN111017869B CN201911149134.9A CN201911149134A CN111017869B CN 111017869 B CN111017869 B CN 111017869B CN 201911149134 A CN201911149134 A CN 201911149134A CN 111017869 B CN111017869 B CN 111017869B
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Abstract
The invention discloses a silicon-based network structure and a preparation method thereof. The method comprises the following steps: the upper surface of the silicon substrate is provided with a plurality of spherical holes distributed in an array; the material layer is positioned on the upper surface of the silicon substrate and is provided with a plurality of hemispherical through holes distributed in an array manner, wherein the hemispherical through holes are just positioned above the spherical holes and are communicated with the spherical holes to jointly form a plurality of calabash-shaped holes distributed in an array manner; and the coating layers are arranged on the surfaces of the silicon substrate and the material layer and distributed along the inner surfaces of the gourd-shaped holes, wherein the coating layers comprise metal, metal compounds or polymer material layers. The preparation method is simple and stable in preparation process and low in cost, and can be used for preparing a gourd-shaped micro-nano array structure compounded by a plurality of different materials, the structure can be used for integrating the properties of a plurality of materials while exerting the unique advantages of the micro-nano array structure, and the method has wide potential application in the fields of catalysis, biological detection, photoelectric detection and the like.
Description
Technical Field
The invention relates to the field of silicon-based network structures, in particular to a micro-nano composite silicon-based network structure and a preparation method thereof.
Background
In recent years, with the continuous development of micro-nano processing technology, researchers prepare various micro-nano array structures by using a planar micro-nano processing technology, a probe process and a model process. For example, the invention patent CN 101339128a "a method for preparing a surface plasmon resonance imaging nanostructure array chip" in china discloses a periodic nanostructure metal lattice chip prepared by using semiconductor processing techniques such as vacuum true plating, laser direct writing, and photolithography, and used for the surface plasmon resonance imaging array chip. Chinese patent CN103668130A, a method for preparing a metal nanostructure, adopts methods such as photoetching and chemical synthesis to prepare a metal nanostructure, has simple process and high efficiency, can accurately control the structure shape and position, and effectively improves the light extraction efficiency and the light absorption efficiency of the metal nanostructure material. Chinese patent CN 102556952B metal cup-column composite nanostructure array and method for making same, using single-layer polystyrene spheres as mask and adopting plasma etching technology to make a metal cup-column composite nanostructure array with small nanometer size gap and applying to Raman detection. The preparation method of the micro-nano array structure can be roughly divided into two categories of artificial construction method and self-assembly method, wherein the artificial construction method comprises photoetching technology, beam etching technology, nano-imprinting technology, micro-contact printing and the like; the self-assembly method includes molecular self-assembly, colloidal self-assembly, template method, etc. By virtue of the excellent performance of the nano material, the micro-nano array structure not only has uniform and ordered structure and high specific surface area, but also shows a plurality of excellent performances in the aspects of electricity, magnetism, optics and the like, such as the characteristics of electron scattering effect, quantum effect, strong light absorption, luminescence, nonlinear optical characteristics and the like, so that the micro-nano array structure is prepared by utilizing the micro-nano processing technology and has important significance when being applied to the fields of electronics, biology, chemical engineering, energy storage and the like.
Disclosure of Invention
The invention mainly aims to provide a novel silicon-based network structure and a preparation method thereof, which can be used for preparing a plurality of different material composite gourd-shaped hole micro-nano array structures with different sizes.
The silicon-based network structure comprises: the upper surface of the silicon substrate is provided with a plurality of spherical holes distributed in an array; the material layer is positioned on the upper surface of the silicon substrate and is provided with a plurality of hemispherical through holes distributed in an array manner, wherein the hemispherical through holes are just positioned above the spherical holes and are communicated with the spherical holes to jointly form a plurality of calabash-shaped holes distributed in an array manner; and the coating layers are arranged on the surfaces of the silicon substrate and the material layer and distributed along the inner surfaces of the gourd-shaped holes, wherein the coating layers comprise metal, metal compounds or polymer material layers.
In one embodiment, the upper surface of the silicon substrate and the lower surface of the material layer are distributed on the same plane; the spherical holes on the upper surface of the silicon substrate are holes with spherical segments; the hemispherical through holes of the material layer are holes with spherical belt bodies, the upper surfaces of the spherical belt bodies and the upper surface of the material layer are distributed on the same plane, and the lower surfaces of the spherical belt bodies and the lower surface of the material layer are distributed on the same plane; the segment is coaxial with the spherical belt body; the holes with the ball segments and the holes of the ball belt body jointly form the gourd-shaped holes.
In one embodiment, the gourd-shaped holes are arranged in a hexagonal close-packed or cubic close-packed array structure, and the array structure is distributed in a network shape.
In one embodiment, the spherical holes on the upper surface of the silicon substrate have a diameter of 100nm to 100 μm; the material of the material layer includes but is not limited to TiO 2 、ZnO、Al 2 O 3 The diameter of the hemispherical perforation on the material layer is 100nm-100 μm, and the height of the hemispherical perforation is 50 nm-50 μm.
In one embodiment, the cladding material is a metal, a metal compound or a polymer material, wherein the metal includes but is not limited to at least one of Pt/Au/Ag/Cu/Al/Zn/Cr/Ti; metal compounds include, but are not limited to, tiO 2 、ZnO、Al 2 O 3 One of CuO, gaN and TiN; the high molecular material includes but is not limited to at least one of polyethylene, polypropylene, polyvinyl chloride and phenolic resin; the thickness of the coating layer is 5-500 nm.
The invention provides a preparation method of a silicon-based network structure, which comprises the following steps: self-assembling a micro/nanosphere array on the upper surface of the silicon substrate; spin-coating a precursor solution on the surface of the silicon substrate with the self-assembled micro-nano sphere array; placing the silicon substrate in an annealing furnace for annealing, and forming a micro-nano bowl array structure on the surface of the silicon substrate; etching the silicon substrate by using a plasma etching technology to form a micro-nano gourd-shaped array structure; and forming a metal, metal compound or high polymer material layer on the surface of the micro-nano calabash-shaped array structure to form a calabash-shaped composite micro-nano array structure.
In one embodiment, the step of self-assembling the micro-nano sphere array on the upper surface of the silicon substrate comprises: mixing the micro-nano sphere suspension and tert-butyl alcohol according to the volume ratio of 1:1, mixing, and slowly injecting the mixture into an aqueous solution containing the silicon substrate by using a micro-injector; and (3) drying the aqueous solution to deposit the micro-nano spheres on the surface of the silicon substrate, wherein the micro-nano spheres are polystyrene or silicon dioxide nano spheres and self-assemble into a hexagonal close-packed single-layer nano sphere array on the surface of the silicon substrate.
In one embodiment, the annealing temperature is 400-800 ℃, and the annealing time is 20-60 min.
In an embodiment, the step of etching the silicon substrate by using a plasma etching technique is to use an Inductively Coupled Plasma (ICP) system, and the etching gas is SF 6 Or O 2 (ii) a The flow rate of the etching gas is 5 to 40sccm (Standard Cubic Centimeter per Minute), O 2 The flow rate is 5-40sccm, the etching time is 5-2000 s, the ICP power is 200-300W, and the RF power is 10-30W.
In one embodiment, the precursor solution comprises TiO 2 At least one of a solution, a ZnO solution and a CuO solution.
Compared with the prior art, the invention has the beneficial effects that:
the invention can prepare the cucurbit-shaped hole micro-nano array structures which are compounded by a plurality of different materials and have different sizes, wherein the micro-nano array structure is formed by overlapping different material layers, and the different material layers are respectively provided with spherical holes and hemispherical through holes to jointly form the cucurbit-shaped holes. Therefore, the properties of more than two materials can be compounded, and meanwhile, a good micro-nano optical cavity can be formed, so that the absorption of light is effectively enhanced. The preparation method is simple in preparation process, and the cucurbit-shaped hole micro-nano array structure is prepared by annealing, plasma etching, magnetron sputtering and other processes. The micro-nano array structure can effectively and uniformly disperse analytes, has unique semiconductor photoelectric properties of the micro-nano array structure, such as high light absorption rate, surface plasmon effect and the like, and has potential application in the fields of physics, chemistry, energy, life science and the like.
In addition, the invention adopts a solution method to self-assemble the micro-nano sphere mask on the surface of the silicon substrate, compared with the traditional spin coating method and the pulling method, the operation is simpler, the use of micro-nano spheres is effectively reduced, the process is stable, and the uniform single-layer hexagonal close-packed micro-nano sphere array structure can be obtained on the surface of the silicon substrate. According to the invention, the micro-nano bowl array structure formed after annealing is directly used as a mask for plasma etching to obtain the hexagonal close-packed micro-nano groove array structure, and the process steps are simple and continuous.
Drawings
The invention is further illustrated by the following figures and examples.
FIG. 1: the cross section of the silicon substrate array structure with the gourd-shaped holes prepared by the invention is schematic.
FIG. 2: the invention prepares a micro-topography map of the surface of the silicon substrate array structure.
FIG. 3: the cross section of the silicon substrate array structure with the gourd-shaped holes prepared by the invention is schematic.
FIG. 4 is a schematic view of: the invention prepares a silicon substrate array structure surface micro-topography map.
FIG. 5: the invention provides a flow chart of a preparation method of a silicon-based network structure.
FIG. 6: the invention provides a preparation process diagram of a silicon-based network structure.
Detailed Description
The technical solutions of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The invention provides a silicon-based network structure and a preparation method thereof, which can be used for preparing a plurality of different material compounded cucurbit-shaped hole micro-nano array structures with different sizes.
Referring to fig. 1 to 4, fig. 1 is a schematic cross-sectional view of a silicon substrate array structure with gourd-shaped holes; FIG. 2 is a surface micro-topography of a silicon substrate array structure; FIG. 3 is a schematic cross-sectional view of a silicon substrate array structure; FIG. 4 is a surface micro-topography of a silicon substrate array structure.
Referring to fig. 1 and fig. 3, the silicon-based network structure includes: the silicon substrate 1 is provided with a plurality of spherical holes 11 distributed in an array on the upper surface; the material layer 2 is positioned on the upper surface of the silicon substrate 1, and the material layer 2 is provided with a plurality of hemispherical through holes 21 distributed in an array manner, wherein the hemispherical through holes 21 are just positioned above the spherical holes 11 and are communicated with the spherical holes 11 to jointly form a plurality of calabash-shaped holes distributed in an array manner; and the coating layer 3 is arranged on the surfaces of the silicon substrate 1 and the material layer 2 and distributed along the inner surfaces of the gourd-shaped holes, wherein the coating layer 3 comprises a metal, a metal compound or a polymer material layer.
In one embodiment, the upper surface of the silicon substrate 1 and the lower surface of the material layer 2 are distributed on the same plane a; the spherical holes 11 on the upper surface of the silicon substrate 1 are holes with spherical segments, the hemispherical through holes 21 on the material layer 2 are holes with spherical belt bodies, the upper surfaces of the spherical belt bodies and the upper surfaces of the material layer 2 are distributed on the same plane B, and the lower surfaces of the spherical belt bodies and the lower surfaces of the material layer 2 are distributed on the same plane A; the segment and the spherical belt body are coaxial b; the holes with the ball segments and the holes of the ball belt body form gourd-shaped holes together. In this embodiment, the bottom surface of the segment and the upper surface of the silicon substrate are distributed on the same plane a; the lower surface of the ball belt body is the same as the bottom surface of the ball segment in size and is distributed on the same plane A with the lower surface of the material layer.
Referring to fig. 2 and fig. 4 for a view of a micro-topography of the upper surface of the silicon substrate 1, in an embodiment, the gourd-shaped holes are arranged in a hexagonal close-packed or cubic close-packed array structure, and the array structure is distributed in a network shape.
In one embodiment, the spherical holes 11 on the upper surface of the silicon substrate 1 have a diameter of 100nm-100 μm, and the material of the material layer 2 includes but is not limited to TiO 2 、ZnO、Al 2 O 3 The hemispherical through hole 21 on the material layer 2 has a diameter of 100nm to 100 μm and a height of 50nm to 50 μm.
In one embodiment, the material of the coating layer 3 is a metal, a metal compound or a polymer material. Wherein the metal includes but is not limited to at least one of Pt, au, ag, cu, al, zn, cr and TiSeed growing; metal compounds include, but are not limited to, tiO 2 、ZnO、Al 2 O 3 One of CuO, gaN and TiN; the polymer material includes, but is not limited to, at least one of polyethylene, polypropylene, polyvinyl chloride, and phenolic resin. The thickness of the coating layer 3 is 5 to 500nm.
Referring to fig. 5 and fig. 6, the present invention also provides a method for preparing the silicon-based network structure and a process thereof, comprising the following steps:
s1: self-assembling the micro-nano sphere array 4 on the upper surface of the silicon substrate 1, as shown in fig. 6 (a);
s2: spin-coating a precursor solution on the surface of the silicon substrate with the self-assembled micro/nanosphere array, as shown in fig. 6 (b);
s3: placing the silicon substrate in an annealing furnace for annealing, and forming a micro-nano bowl array structure on the surface of the silicon substrate, as shown in fig. 6 (c);
s4: etching the silicon substrate by using a plasma etching technology to form a micro-nano gourd-shaped array structure as shown in fig. 1 and fig. 6 (d);
s5: as shown in fig. 6 (e), a metal, metal compound, or polymer material layer is formed on the surface of the micro-nano gourd-shaped array structure to form a gourd-shaped composite micro-nano array structure as shown in fig. 3.
In one embodiment, the step of self-assembling the micro-nano sphere array on the upper surface of the silicon substrate comprises: mixing the micro-nano sphere suspension and tert-butyl alcohol according to the volume ratio of 1:1, mixing, and slowly injecting the mixture into an aqueous solution containing the silicon substrate by using a micro-injector; and (3) drying the aqueous solution to deposit the micro-nano spheres on the surface of the silicon substrate, wherein the micro-nano spheres are polystyrene or silicon dioxide nano spheres and self-assemble into a hexagonal close-packed single-layer nano sphere array on the surface of the silicon substrate.
In one embodiment, the silicon substrate is a single-side or double-side polished silicon wafer or other substrate material such as silicon dioxide.
In one embodiment, the annealing temperature is 400-800 ℃, and the annealing time is 20-60 min. The preferred temperature range is 450 to 550 ℃ and the time is 20 to 40mins.
In an embodiment, the step of etching the silicon substrate by using the plasma etching technology adopts an Inductively Coupled Plasma (ICP) system, and the etching gas is SF 6 Or O 2 (ii) a The flow rate of the etching gas is 5 to 40sccm (Standard Cubic Centimeter per Minute), O 2 The flow rate is 5-40sccm, the etching time is 5-2000 s, the ICP power is 200-300W, and the RF power is 10-30W.
In one embodiment, the precursor solution comprises TiO 2 At least one of a solution, a ZnO solution and a CuO solution.
In one embodiment, before the step of self-assembling the micro/nano sphere array, RCA (Radio Corporation of America) cleaning is performed on the silicon substrate, and after the cleaning, a hexagonal close-packed monolayer of polystyrene or silica micro/nano spheres is self-assembled on the surface of the silicon substrate.
In one embodiment, the micro-and nanosphere dispersion has a concentration of 2% to 20% by weight and a diameter of 300nm to 10 μm.
In one embodiment, the TiO 2 The concentration range of the solution is 0.1-0.5 mol/L.
In one embodiment, the plasma etching is performed for 10 to 3000 seconds.
In one embodiment, the metal in step S5 includes at least one of Pt/Au/Ag/Cu/Al/Zn/Cr.
The following describes the manufacturing process and conditions of the preparation method provided by the present invention in detail by six specific examples.
Example 1:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer with resistivity of 0.001-0.009 Ω & cm and thickness of 800 μm was selected.
Sa2: and performing RCA standard cleaning on the silicon wafer in Sa1 to remove various impurities and pollutants on the surface. The specific cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a No. 3 solution: 660mL of sulfuric acid and 220mL of hydrogen peroxide are mixed according to 3:1 (hydrogen peroxide is added first and then sulfuric acid is added) to obtain 3# solution, and meanwhile, pure water is heated by a container.
3) And (3) placing the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating at 250 ℃ for 15 minutes, taking out the bracket after boiling and washing, and then placing the bracket in hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing 2# solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water with the temperature of 60-80 ℃ to obtain 2# solution, putting the silicon wafer into the 2# solution for water bath for 15 minutes, taking out the silicon wafer, and putting the silicon wafer into the hot water with the temperature of 60-80 ℃ for washing for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro-nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: mixing 5 mass percent of polystyrene micro-nano sphere dispersion liquid with the diameter of 530nm and tert-butyl alcohol according to the volume ratio of 1:1 mixing, placing the mixed solution in water for 5 minutes by ultrasonic treatment, then slowly injecting 40 mu L of micro-nano sphere dispersion liquid into a water tank containing the silicon wafer treated in the step A (wherein the silicon wafer is completely immersed by water) by adopting a 50 mu L micro-injector at the speed of 45-degree inclination angle of 10 mu L/min, enabling the micro-nano sphere single layer to be tightly arranged on the surface of the water solution, opening small holes at the bottom of the water tank after the micro-nano spheres are fully paved on the whole water surface, starting to slowly drain water, enabling the micro-nano spheres on the water surface to be deposited on the surface of the silicon wafer, and then placing the silicon wafer in a ventilation cabinet to naturally dry the silicon wafer.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: 0.546mL of 75wt% diisopropyl di (acetylacetonate) titanate isopropanol solution is mixed with 5mL of ethanol to obtain 0.15mol/L TiO 2 Precursor solution, followed by spin-coatingAnd spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nano sphere array by using a spin coater, wherein the spin-coating parameters of the spin coater are 5000rpm and the spin-coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc2: and (3) putting the silicon wafer into a muffle furnace for annealing at the annealing temperature of 500 ℃ for 30min, forming a material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the diameter of the aperture to be 530nm.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing a hemispherical perforated material layer which is formed on the surface of a silicon substrate and distributed in an array manner in an SI500 inductively coupled plasma etching system for etching, wherein the etching parameters are as follows: ICP electrode power 200W, RF power 15W, SF 6 The flow rate is 20sccm, the etching time is 20s, the etching depth is 200nm, spherical holes distributed in an array are formed on the upper surface of the silicon substrate, the diameter of the circle on the upper surface of each hole is 480nm, the depth of each hole is 200nm, and the hemispherical through holes are located right above the spherical holes and communicated with the spherical holes to form a plurality of calabash-shaped holes distributed in an array together, as shown in fig. 2.
E. Preparation of coating layer of silicon-based network structure
Se1: the silicon wafer with calabash-shaped holes distributed in an array on the surface is subjected to metal layer deposition by an ExpLorer-14 magnetron sputtering coating system, the sputtering power is 200W, the deposition thickness is 20nm, the schematic cross-sectional view of the silicon wafer is shown in figure 3, the microstructure of a sampling area is shown in figure 4 when the metal layer is an Au layer, and the Au layer can also be Ag, cu, al, ti, ni and Pt.
In this example, a titanium dioxide and silicon composite gourd-shaped hole nano array structure of about 500nm was successfully prepared, the array units were in hexagonal close packing, and Au/TiO shown in fig. 4 was obtained by further depositing 20nm thick gold on the surface 2 the/Si composite gourd-shaped nano array structure can enhance the absorption of titanium dioxide to light and improve the electron state density due to the surface plasmon resonance effect of the surface Au nano particles, thereby further enhancing the photocatalytic effect of the surface titanium dioxide in physics, chemistry and energyAnd has potential application in the fields of life science and the like.
Example 2:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer having a resistivity of 0.1. Omega. Cm and a thickness of 500 μm was selected.
Sa2: RCA standard cleaning is carried out on the silicon chip to remove various impurities and pollutants on the surface, and the cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare a hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a 3# solution, mixing 660mL of sulfuric acid with 220mL of hydrogen peroxide according to 3:1 (firstly adding hydrogen peroxide and then adding sulfuric acid) to obtain the 3# solution, and simultaneously heating pure water by using a container.
3) And (3) placing the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating at 250 ℃ for 15 minutes, taking out the bracket after boiling and washing, and then placing the bracket in hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing a No. 2 solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water to obtain the No. 2 solution, putting the silicon wafer into the No. 2 solution for water bath for 15 minutes, taking out the silicon wafer, and washing the silicon wafer in the hot water at the temperature of 60-80 ℃ for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro/nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: mixing 5% of silicon dioxide micro-nano sphere dispersion liquid with the diameter of 1000nm and tert-butyl alcohol according to the volume ratio of 1:1 mixing, placing the mixed solution in water for 5 minutes by ultrasonic treatment, then slowly injecting 40 mu L of micro-nano sphere dispersion liquid into a water tank with a silicon wafer (wherein the silicon wafer is completely immersed by water) by adopting a 50 mu L micro-injector at the speed of 45-degree inclination angle of 10 mu L/min, enabling the micro-nano sphere single layer to be tightly arranged on the surface of the aqueous solution, opening small holes at the bottom of the water tank after the micro-nano sphere is fully paved on the whole water surface, starting slow water drainage, enabling the micro-nano sphere on the water surface to be deposited on the surface of the silicon wafer, and then placing the silicon wafer in a ventilation cabinet to enable the silicon wafer to be naturally air-dried.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: zn (OAc) 2 ·2H 2 O(>98%) and polyethylene oxide (PEO) (M) w = 1500) dissolved in deionized water to obtain 0.01mol/L Zn (OAc) 2 And (3) spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nanosphere array by using a spin coater, wherein the spin coating parameters of the spin coater are 5000rpm and the spin coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc: and putting the silicon wafer into a muffle furnace for annealing at 450 ℃ for 60min, forming a zinc oxide material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the diameter of the aperture to be 1000nm.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing a hemispherical perforated material layer which is formed on the surface of a silicon substrate and distributed in an array manner in an SI500 inductively coupled plasma etching system for etching, wherein the etching parameters are as follows: ICP electrode power 200W, RF power 15W, SF 6 The flow is 30sccm, the etching time is 25s, the etching depth is 450nm, spherical holes distributed in an array are formed in the upper surface of the silicon substrate, the diameter of the circle of the upper surface of each hole is 800nm, the depth of each hole is 450nm, and the hemispherical through holes are located right above the spherical holes and communicated with the spherical holes to form a plurality of calabash-shaped holes distributed in an array.
E. Preparation of a coating layer for a silicon-based network structure
Se1: depositing a metal oxide layer on a silicon wafer with calabash-shaped holes distributed in an array on the surface of the silicon wafer by adopting a magnetron sputtering coating system, and depositing TiO with the thickness of 50nm 2 Layer of TiO 2 The metal oxide layer may also be Al 2 O 3 、TiO 2 、ZrO 2 。
The embodiment successfully prepares a zinc oxide and silicon composite cucurbit-shaped hole micro-nano array structure with about 1000 nanometers, the array units are in hexagonal close packing, and 50 nanometers of TiO are further deposited on the surface 2 The layer obtains a composite gourd-shaped micro-nano array structure.
Example 3:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer having a resistivity of 0.1. Omega. Cm and a thickness of 500 μm was selected.
And Sa2, carrying out RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface, wherein the cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare a hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a 3# solution, mixing 660mL of sulfuric acid with 220mL of hydrogen peroxide according to 3:1 (firstly adding hydrogen peroxide and then adding sulfuric acid) to obtain the 3# solution, and simultaneously heating pure water by using a container.
3) And putting the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating at 250 ℃ for 15 minutes, taking out the bracket after boiling and washing, and then putting the bracket into hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing a No. 2 solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water to obtain the No. 2 solution, putting the silicon wafer into the No. 2 solution for water bath for 15 minutes, taking out the silicon wafer, and putting the silicon wafer into hot water at the temperature of between 60 and 80 ℃ for washing for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro/nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: firstly, the cleaned silicon substrate is placed in a Q150 microwave plasma degumming machineIn N 2 Activating for 1 minute under the atmosphere, and then spin-coating 2mL of the silica micro-nanosphere dispersion with a mass fraction of 40% and a diameter of 10 μm on the surface of the silicon substrate by using a spin coater with the parameters of 5s at 500rpm and 30s at 2500rpm to closely arrange the silica micro-nanosphere monolayer on the surface of the silicon substrate.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: 6.09 g of analytically pure MgCl 2 ·6H 2 O was placed in a beaker with a volume of 50 ml, dissolved by adding deionized water, followed by addition of 7.2 g of analytically pure CO (NH) 2 ) 2 After stirring, adjusting the pH value of the solution to 3-9 by using analytically pure HCl to form a magnesium oxide precursor solution, then spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nanosphere array by using a spin coater, wherein the spin-coating parameter of the spin coater is 5000rpm, and the spin-coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc: and putting the silicon wafer into a muffle furnace for annealing at 700 ℃ for 30min, forming a magnesium oxide material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the diameter of the aperture to be 10 microns.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing a hemispherical perforated material layer which is formed on the surface of a silicon substrate and distributed in an array manner in an SI500 inductive coupling plasma etching system for etching, wherein the etching parameters are as follows: ICP electrode power 200W, RF power 15W, SF 6 The flow rate is 20sccm, the etching time is 500s, the etching depth is 5 microns, spherical holes distributed in an array mode are formed in the upper surface of the silicon substrate, the diameter of the circle of the upper surface of each hole is 8 microns, the depth of each hole is 5 microns, and the hemispherical through holes are located right above the spherical holes and communicated with the spherical holes to form a plurality of calabash-shaped holes distributed in an array mode.
E. Preparation of coating layer of silicon-based network structure
Se1: depositing a metal nitride layer on the silicon wafer with the calabash-shaped holes distributed in an array on the surface of the silicon wafer by adopting a magnetron sputtering coating system, wherein the deposition thickness is 150nm, and the metal nitride layer can also be AlN or GaN.
In the embodiment, a magnesium oxide and silicon composite gourd-shaped hole micro-nano array structure of about 10 microns is successfully prepared, array units are arranged in a hexagonal close packing manner, and a 150-nanometer metal nitride layer is further deposited on the surface of the array units to obtain the composite gourd-shaped micro-nano array structure.
Example 4:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer with resistivity of 0.001-0.009 Ω & cm and thickness of 800 μm was selected.
And Sa2. Carrying out RCA standard cleaning on the silicon wafer to remove various impurities and pollutants on the surface, wherein the cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare a hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a 3# solution, mixing 660mL of sulfuric acid with 220mL of hydrogen peroxide according to 3:1 (firstly adding hydrogen peroxide and then adding sulfuric acid) to obtain the 3# solution, and simultaneously heating pure water by using a container.
3) And putting the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating the bracket at 250 ℃ for 15 minutes, taking the bracket out after boiling and washing, and then putting the bracket into hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing a No. 2 solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water to obtain the No. 2 solution, putting the silicon wafer into the No. 2 solution for water bath for 15 minutes, taking out the silicon wafer, and washing the silicon wafer in the hot water at the temperature of 60-80 ℃ for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro/nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: mixing 5% of polystyrene micro-nanosphere dispersion liquid with the diameter of 360nm and tert-butyl alcohol according to the volume ratio of 1:1 mixing, placing the mixed solution in water for 5 minutes by ultrasonic treatment, then slowly injecting 40 mu L of micro-nano sphere dispersion liquid into a water tank with a silicon wafer (wherein the silicon wafer is completely immersed by water) by adopting a 50 mu L micro-injector at the speed of 45-degree inclination angle of 10 mu L/min, enabling the micro-nano sphere single layer to be tightly arranged on the surface of the water solution, opening small holes at the bottom of the water tank after the micro-nano spheres are fully paved on the whole water surface, starting to slowly drain water, enabling the micro-nano spheres on the surface of the water to be deposited on the surface of the silicon wafer, and then placing the silicon wafer in a ventilation cabinet to naturally dry the silicon wafer.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: 0.546mL of 75wt% diisopropyl di (acetylacetonate) titanate isopropanol solution is mixed with 5mL of ethanol to obtain 0.15mol/L TiO 2 And (3) spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nanosphere array by using a spin coater, wherein the spin coating parameters of the spin coater are 5000rpm and the spin coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc: and putting the silicon wafer into a muffle furnace for annealing at the annealing temperature of 500 ℃ for 30min, forming a titanium dioxide material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the circular diameter of the upper surface of the aperture to be 360nm.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing a hemispherical perforated material layer which is formed on the surface of a silicon substrate and distributed in an array manner in an SI500 inductively coupled plasma etching system for etching, wherein the etching parameters are as follows: ICP electrode power 200W, RF power 15W, SF 6 The flow rate is 20sccm, the etching time is 10s, the etching depth is 100nm, spherical holes distributed in an array are formed in the upper surface of the silicon substrate, the diameter of the circle of the upper surface of each hole is 280nm, the depth of each hole is 100nm, and the hemispherical through holes are located right above the spherical holes and communicated with the spherical holes to form a plurality of calabash-shaped holes distributed in an array.
E. Preparation of coating layer of silicon-based network structure
Se1: the preparation method comprises the steps of preparing a polyimide film from a silicon wafer with gourd-shaped holes distributed in an array on the surface of the silicon wafer by using a known method, namely, casting a polyamic acid solution on the silicon wafer to deposit a 25nm polyimide polymer layer on the surface of a silicon-based lattice with an array structure.
According to the embodiment, the titanium dioxide and silicon composite cucurbit-shaped hole micro-nano array structure with the size of about 360 nanometers is successfully prepared, the array units are arranged in a hexagonal close-packed mode, and the composite cucurbit-shaped micro-nano array structure is obtained by further depositing a 25 nanometer polyimide polymer layer on the surface.
Example 5:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer with resistivity of 0.001-0.009 Ω & cm and thickness of 800 μm was selected.
Sa2: and performing RCA standard cleaning on the silicon wafer in Sa1 to remove various impurities and pollutants on the surface. The specific cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare a hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a No. 3 solution: 660mL of sulfuric acid and 220mL of hydrogen peroxide are mixed according to 3:1 (hydrogen peroxide is added first and then sulfuric acid is added) to obtain 3# solution, and meanwhile, pure water is heated by a container.
3) And putting the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating the bracket at 250 ℃ for 15 minutes, taking the bracket out after boiling and washing, and then putting the bracket into hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing a No. 2 solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water to obtain the No. 2 solution, putting the silicon wafer into the No. 2 solution for water bath for 15 minutes, taking out the silicon wafer, and putting the silicon wafer into hot water at the temperature of between 60 and 80 ℃ for washing for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro/nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: mixing 5% of polystyrene micro-nanosphere dispersion with the diameter of 100 mu m and tert-butyl alcohol according to the volume ratio of 1:1 mixing, placing the mixed solution in water for 5 minutes by ultrasonic treatment, then slowly injecting 40 mu L of micro-nano sphere dispersion liquid into a water tank containing the silicon wafer treated in the step A (wherein the silicon wafer is completely immersed by water) by adopting a 50 mu L micro-injector at the speed of 45-degree inclination angle of 10 mu L/min, enabling the micro-nano sphere single layer to be tightly arranged on the surface of the water solution, opening small holes at the bottom of the water tank after the micro-nano spheres are fully paved on the whole water surface, starting to slowly drain water, enabling the micro-nano spheres on the water surface to be deposited on the surface of the silicon wafer, and then placing the silicon wafer in a ventilation cabinet to naturally dry the silicon wafer.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: 0.546mL of 75wt% diisopropyl di (acetylacetonate) titanate isopropanol solution is mixed with 5mL of ethanol to obtain 0.15mol/L TiO 2 And (3) spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nanosphere array by using a spin coater, wherein the spin coating parameters of the spin coater are 5000rpm and the spin coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc: and (3) putting the silicon wafer into a muffle furnace for annealing at the annealing temperature of 500 ℃ for 30min, forming a material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the diameter of the aperture to be 100 mu m.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing a hemispherical perforated material layer which is formed on the surface of a silicon substrate and distributed in an array manner in an SI500 inductively coupled plasma etching system for etching, wherein the etching parameters are as follows: ICP electrode power 200W, RF power 15W, SF 6 The flow is 20sccm, the etching time is 2500s, the etching depth is 25 mu m, and an array is formed on the upper surface of the silicon substrateThe upper surfaces of the distributed spherical holes have the circular diameter of 50 mu m and the depth of 25 mu m, wherein the hemispherical through holes are just positioned above the spherical holes and are communicated with the spherical holes to jointly form a plurality of calabash-shaped holes distributed in an array.
E. Preparation of coating layer of silicon-based network structure
Se1: depositing a metal layer on the silicon wafer with the calabash-shaped holes distributed in an array on the surface of the silicon wafer by a magnetron sputtering coating system, wherein the sputtering power is 200W, and the deposition thickness is 500nm.
The embodiment successfully prepares the titanium dioxide and silicon composite cucurbit-shaped hole micro-nano array structure of about 100 microns, the array units are in hexagonal close packing, and the composite cucurbit-shaped micro-nano array structure is obtained by further depositing a 500-nanometer metal layer on the surface.
Example 6:
A. preparation of silicon substrate
Sa1: a4-inch N-type double-side polished silicon wafer with resistivity of 0.001-0.009 Ω & cm and thickness of 800 μm was selected.
Sa2: RCA standard cleaning is carried out on the silicon wafer in Sa1 to remove various impurities and pollutants on the surface. The specific cleaning steps are as follows:
1) Firstly, 100mL of hydrofluoric acid and 2000mL of water are mixed to prepare hydrofluoric acid solution, and meanwhile, a silicon wafer support is cleaned and dried for standby application, and then a silicon wafer is placed on the support.
2) Preparing a No. 3 solution: 660mL of sulfuric acid and 220mL of hydrogen peroxide are mixed according to 3:1 (hydrogen peroxide is added first and then sulfuric acid is added) to obtain 3# solution, and meanwhile, pure water is heated by a container.
3) And putting the bracket containing the silicon wafer into No. 3 liquid for boiling and washing, heating the bracket at 250 ℃ for 15 minutes, taking the bracket out after boiling and washing, and then putting the bracket into hot water at 60-80 ℃ for washing for 5 minutes.
4) Preparing a No. 1 solution, sequentially adding 1L of deionized water, 200mL of ammonia water and 200mL of hydrogen peroxide into a beaker to obtain the No. 1 solution, heating the No. 1 solution to 75 ℃, and then putting the silicon wafer into the No. 1 solution for water bath for 10 minutes.
5) Preparing No. 2 solution, adding 240mL of hydrochloric acid and 240mL of hydrogen peroxide into 1200mL of hot water with the temperature of 60-80 ℃ to obtain No. 2 solution, putting the silicon wafer into the No. 2 solution for water bath for 15 minutes, taking out the silicon wafer, and putting the silicon wafer into the hot water with the temperature of 60-80 ℃ for washing for 5 minutes.
6) The silicon wafer was placed in a 10% hydrofluoric acid solution for 3 minutes to remove the surface oxide layer and finally rinsed with deionized water for 20 minutes.
B. Micro/nano sphere array structure self-assembled on upper surface of silicon substrate
Sb1: mixing 5 mass percent of polystyrene micro-nano sphere dispersion liquid with the diameter of 100nm and tert-butyl alcohol according to the volume ratio of 1:1 mixing, placing the mixed solution in water for 5 minutes by ultrasonic treatment, then slowly injecting 40 mu L of micro-nano sphere dispersion liquid into a water tank containing the silicon wafer treated in the step A (wherein the silicon wafer is completely immersed by water) by adopting a 50 mu L micro-injector at the speed of 45-degree inclination angle of 10 mu L/min, enabling the micro-nano sphere single layer to be tightly arranged on the surface of the water solution, opening small holes at the bottom of the water tank after the micro-nano spheres are fully paved on the whole water surface, starting to slowly drain water, enabling the micro-nano spheres on the water surface to be deposited on the surface of the silicon wafer, and then placing the silicon wafer in a ventilation cabinet to naturally dry the silicon wafer.
C. Preparing material layers in silicon-based network structures
And (2) Sc1: 0.546mL of 75wt% diisopropyl di (acetylacetonate) titanate isopropanol solution is mixed with 5mL of ethanol to obtain 0.15mol/L TiO 2 And (3) spin-coating the precursor solution on the surface of the silicon substrate self-assembled with the micro-nanosphere array by using a spin coater, wherein the spin coating parameters of the spin coater are 5000rpm and the spin coating time is 30s, so that the solution is uniformly dispersed on the surface and is naturally air-dried.
And (2) Sc: and (3) putting the silicon wafer into a muffle furnace for annealing at the annealing temperature of 500 ℃ for 30min, forming a material layer on the upper surface of the silicon substrate, forming a micro-nano bowl array structure by hemispherical perforations distributed in an array manner, and enabling the diameter of the aperture to be 100nm.
D. Preparation of spherical holes distributed in array in silicon-based network structure
Sd1: placing the hemispherical perforated material layer with array distribution formed on the surface of the silicon substrate in an SI500 inductively coupled plasma etching system for etching, wherein the etching parametersComprises the following steps: ICP electrode power 200W, RF power 15W, SF 6 The flow rate is 20sccm, the etching time is 5s, the etching depth is 50nm, spherical holes distributed in an array are formed on the upper surface of the silicon substrate, the diameter of the upper surface of each hole is 80-100nm, the depth of each hole is 50nm, and the hemispherical through holes are located right above the spherical holes and communicated with the spherical holes to form a plurality of calabash-shaped holes distributed in an array together, as shown in fig. 1.
E. Preparation of coating layer of silicon-based network structure
Se1: depositing a metal layer on the silicon wafer with calabash-shaped holes distributed in an array on the surface of the silicon wafer by adopting an ExpLorer-14 magnetron sputtering coating system, wherein the sputtering power is 200W, and the deposition thickness is 5nm.
The embodiment successfully prepares a titanium dioxide and silicon composite cucurbit-shaped hole micro-nano array structure of about 100 nanometers, the array units are in hexagonal close packing, and the surface is further deposited with a 5 nanometer thick gold composite cucurbit-shaped micro-nano array structure.
Compared with the prior art, the invention has the beneficial effects that:
the invention can prepare the cucurbit-shaped hole micro-nano array structures which are compounded by a plurality of different materials and have different sizes, wherein the micro-nano array structure is formed by overlapping different material layers, and the different material layers are respectively provided with spherical holes and hemispherical through holes to jointly form the cucurbit-shaped holes. Therefore, the properties of more than two materials can be compounded, and meanwhile, a good micro-nano optical cavity can be formed, so that the absorption of light is effectively enhanced. The preparation method is simple in preparation process, and the cucurbit-shaped hole micro-nano array structure is prepared by annealing, plasma etching, magnetron sputtering and other processes. The micro-nano array structure can effectively and uniformly disperse analytes, has unique semiconductor photoelectric properties of the micro-nano array structure, such as high light absorption rate, surface plasmon effect and the like, and has potential applications in the fields of physics, chemistry, energy, life science and the like, such as the catalysis field.
In addition, the invention adopts the solution method to self-assemble the micro-nano sphere mask on the surface of the silicon substrate, compared with the traditional spin coating method and the pulling method, the operation is simpler, the use of nano spheres is effectively reduced, the process is stable, and the uniform single-layer hexagonal close-packed micro-nano sphere array structure can be obtained on the surface of the silicon substrate. According to the invention, the micro-nano bowl array structure formed after annealing is directly used as a mask for plasma etching to obtain the hexagonal close-packed micro-nano groove array structure, and the process steps are simple and continuous.
The above embodiments are provided to illustrate the principles and effects of the present invention, and not to limit the present invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A silicon-based network structure, the silicon-based network structure comprising:
the upper surface of the silicon substrate is provided with a plurality of spherical holes distributed in an array;
the material layer is positioned on the upper surface of the silicon substrate and is provided with a plurality of hemispherical through holes distributed in an array manner, wherein the hemispherical through holes are just positioned above the spherical holes and are communicated with the spherical holes to jointly form a plurality of calabash-shaped holes distributed in an array manner;
and the coating layers are arranged on the surfaces of the silicon substrate and the material layer and distributed along the inner surfaces of the gourd-shaped holes, wherein the coating layers comprise metal, metal compounds or polymer material layers.
2. The silicon-based network structure of claim 1, wherein the upper surface of the silicon substrate and the lower surface of the material layer are disposed on the same plane; the spherical holes on the upper surface of the silicon substrate are holes with spherical segments; the hemispherical through holes of the material layer are holes with spherical belt bodies, the upper surfaces of the spherical belt bodies and the upper surface of the material layer are distributed on the same plane, and the lower surfaces of the spherical belt bodies and the lower surface of the material layer are distributed on the same plane; the segment is coaxial with the ball belt body; the holes with the ball segments and the holes of the ball belt bodies jointly form the gourd-shaped holes.
3. The silicon-based network structure of claim 1, wherein the gourd-shaped holes are in a hexagonal close-packed or cubic close-packed array structure, and the array structure is in a network distribution.
4. The silicon-based network structure of claim 1, wherein:
the diameter of the spherical hole on the upper surface of the silicon substrate is 100nm-100 mu m;
the material of the material layer comprises TiO 2 、ZnO、Al 2 O 3 At least one of CuO and TiN, the diameter of the hemispherical perforation on the material layer is 100nm-100 μm, and the height thereof is 50 nm-50 μm.
5. The silicon-based network structure of claim 1, wherein:
the coating layer is made of metal, metal compound or high polymer material, wherein the metal comprises at least one of Pt, au, ag, cu, al, zn, cr and Ti; the metal compound comprising TiO 2 、ZnO、Al 2 O 3 One of CuO, gaN and TiN; the high molecular material comprises at least one of polyethylene, polypropylene, polyvinyl chloride and phenolic resin; the thickness of the coating layer is 5-500 nm.
6. A preparation method of a silicon-based network structure comprises the following steps:
self-assembling a micro/nanosphere array on the upper surface of the silicon substrate;
spin-coating a precursor solution on the surface of the silicon substrate with the self-assembled micro-nano sphere array;
placing the silicon substrate in an annealing furnace for annealing, and forming a micro-nano bowl array structure on the surface of the silicon substrate;
etching the silicon substrate by using a plasma etching technology to form a micro-nano gourd-shaped array structure;
and forming a metal, metal compound or high polymer material layer on the surface of the micro-nano calabash-shaped array structure to form a calabash-shaped composite micro-nano array structure.
7. The method for preparing the micro-nano sphere array of the invention according to claim 6, wherein the step of self-assembling the micro-nano sphere array on the surface of the silicon substrate comprises:
mixing the micro-nano sphere suspension with tert-butyl alcohol according to a volume ratio of 1:1, and slowly injecting the mixture into an aqueous solution containing the silicon substrate by using a micro-injector;
and (3) drying the aqueous solution to deposit the micro-nano spheres on the surface of the silicon substrate, wherein the micro-nano spheres are polystyrene or silicon dioxide nano spheres and self-assemble into a hexagonal close-packed single-layer nano sphere array on the surface of the silicon substrate.
8. The method of claim 6, wherein: the annealing temperature is 400-800 ℃, and the annealing time is 20-60 min.
9. The method of claim 6, wherein: the step of etching the silicon substrate by using the plasma etching technology adopts an Inductively Coupled Plasma (ICP) system, and etching gas is SF 6 Or O 2 (ii) a The flow rate of the etching gas is 5-40sccm (Standard Cubic Centimeter per Minute), O 2 The flow rate is 5-40sccm, the etching time is 5-2000 s, the ICP power is 200-300W, and the Radio Frequency (RF) power is 10-30W.
10. The method of claim 6, wherein: the precursor solution comprises TiO 2 At least one of a solution, a ZnO solution and a CuO solution.
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