CN110993758A - Display array of micro light-emitting diode and manufacturing method thereof - Google Patents
Display array of micro light-emitting diode and manufacturing method thereof Download PDFInfo
- Publication number
- CN110993758A CN110993758A CN201911051010.7A CN201911051010A CN110993758A CN 110993758 A CN110993758 A CN 110993758A CN 201911051010 A CN201911051010 A CN 201911051010A CN 110993758 A CN110993758 A CN 110993758A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- generation layer
- threshold value
- electron generation
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910001425 magnesium ion Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 42
- 230000031700 light absorption Effects 0.000 claims description 40
- 239000011521 glass Substances 0.000 claims description 13
- 230000001154 acute effect Effects 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 229910052594 sapphire Inorganic materials 0.000 claims description 10
- 239000010980 sapphire Substances 0.000 claims description 10
- -1 oxygen ions Chemical class 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 11
- 238000010168 coupling process Methods 0.000 abstract description 11
- 238000005859 coupling reaction Methods 0.000 abstract description 11
- 230000003287 optical effect Effects 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 160
- 239000000463 material Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 14
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 238000002161 passivation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000004020 luminiscence type Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910000952 Be alloy Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 229920001486 SU-8 photoresist Polymers 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a display array of a micro light-emitting diode and a manufacturing method thereof, belonging to the technical field of semiconductors. The display array comprises a circuit board and a plurality of light emitting chips arranged on the circuit board at intervals; each light-emitting chip comprises a P-type electrode, a hole generation layer, an active layer, an electron generation layer and an N-type electrode which are sequentially stacked on the circuit board; a groove extending towards the active layer is formed in a first surface area of the electron generation layer, and the distance between a point in the first surface area and the edge of the light emitting chip is smaller than a first threshold value; magnesium ions are implanted into a second surface area of the electron generation layer in the groove, the distance between a point in the second surface area and the edge of the light emitting chip is between a second threshold value and a third threshold value, the second threshold value is smaller than the third threshold value, and the third threshold value is smaller than the first threshold value. The present disclosure can reduce optical coupling between two adjacent Micro LEDs.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a display array of micro light emitting diodes and a method for fabricating the same.
Background
A Light Emitting Diode (LED) is a commonly used Light Emitting device, which emits Light by energy released by recombination of electrons and holes, and is widely used in the fields of display, decoration, communication, illumination, and the like in daily life. By using different semiconductor materials and structures, leds can cover the full color range from ultraviolet to infrared, essentially occupying the large-pitch display market both indoors and outdoors. The pitch refers to a distance between two adjacent display units in the display, and is related to the resolution of the display.
Currently, the small-pitch Display market still uses Liquid Crystal Display (LCD) as the main stream. Although Organic Light-Emitting diodes (OLEDs) are becoming the mainstream of replacing LCDs in some fields, OLEDs have problems such as burn-in. The micro light emitting diode (English: MicroLED) is a microminiature light emitting diode with the side length of 10-100 micrometers, has small volume, can be arranged together more densely to greatly improve the resolution, has self-luminous property, is superior to an LCD and an OLED in the aspects of high brightness, high contrast, fast response, power saving and the like, and is likely to further occupy the small-distance display market in the future.
In the course of implementing the present disclosure, the inventors found that the prior art has at least the following problems:
the volume and the spacing of the Micro LEDs are very small, and the two adjacent Micro LEDs are mutually interfered due to optical coupling, so that the boundary outline of a displayed image is fuzzy and unclear, and the Micro LEDs cannot be applied to a small-spacing display at present.
Disclosure of Invention
The embodiment of the disclosure provides a display array of Micro light emitting diodes and a manufacturing method thereof, which are beneficial to reducing optical coupling between two adjacent Micro LEDs and improving definition of a boundary outline of a displayed image.
The technical scheme is as follows:
in one aspect, the disclosed embodiments provide a display array of micro light emitting diodes, where the display array includes a circuit board and a plurality of light emitting chips arranged on the circuit board at intervals; each light-emitting chip comprises a P-type electrode, a hole generation layer, an active layer, an electron generation layer and an N-type electrode which are sequentially stacked on the circuit board; a groove extending towards the active layer is formed in a first surface area of the electron generation layer, and the distance between a point in the first surface area and the edge of the light emitting chip is smaller than a first threshold value; magnesium ions are implanted into a second surface area of the electron generation layer in the groove, the distance between a point in the second surface area and the edge of the light emitting chip is between a second threshold value and a third threshold value, the second threshold value is smaller than the third threshold value, and the third threshold value is smaller than the first threshold value.
Optionally, the thickness of the electron generation layer of the first surface region is 0.4 μm to 0.6 μm, and the minimum distance between magnesium ions in the electron generation layer of the second surface region and the active layer is 0.08 μm to 0.12 μm.
Further, the second threshold value is 0.25 to 0.35 μm, the third threshold value is 0.55 to 0.65 μm, and the first threshold value is 0.9 to 1.1 μm.
Optionally, the second surface region of the electron generation layer is further implanted with oxygen ions.
Optionally, the display array further includes a light absorption block, the light absorption block is disposed on the circuit board between two adjacent light emitting chips, and the height of the light absorption block is equal to the height of the light emitting chip.
Furthermore, a V-shaped opening is formed in the surface, opposite to the light emitting chip, of the light absorption block; in the V-shaped opening of the part of the light absorption block opposite to the electron generation layer, the side wall far away from the circuit board is parallel to the surface of the circuit board, and the included angle between the side wall close to the circuit board and the surface of the circuit board is an acute angle; in the V-shaped opening of the part of the light absorption block opposite to the active layer, an included angle between the side wall far away from the circuit board and the surface of the circuit board and an included angle between the side wall close to the circuit board and the surface of the circuit board are acute angles and have the same size; in the V-shaped opening of the part of the light absorption block opposite to the hole generation layer, an included angle between the side wall far away from the circuit board and the surface of the circuit board is an acute angle, and the side wall close to the circuit board is parallel to the surface of the circuit board.
In another aspect, an embodiment of the present disclosure provides a method for manufacturing a display array of micro light emitting diodes, where the method includes:
sequentially forming an electron generation layer, an active layer and a hole generation layer on a growth substrate to form an epitaxial wafer;
bonding the hole generating layer to a glass substrate;
removing the growth substrate by adopting a wet etching mode;
binding the electron generation layer to a sapphire substrate;
removing the glass substrate;
forming a P-type electrode on the hole generation layer;
bonding the P-type electrode to a circuit board;
removing the sapphire substrate by adopting a laser stripping mode;
forming a groove extending towards the active layer in a first surface region of the electron generation layer, wherein the distance between a point in the first surface region and the edge of the epitaxial wafer is smaller than a first threshold value;
magnesium ions are implanted into a second surface region of the electron generation layer in the groove, the distance between a point in the second surface region and the edge of the epitaxial wafer is between a second threshold value and a third threshold value, the second threshold value is smaller than the third threshold value, and the third threshold value is smaller than the first threshold value;
and forming an N-type electrode on the electron generation layer outside the groove to form a light-emitting chip.
Optionally, the manufacturing method further includes:
and before bonding the hole generation layer on the glass substrate, carrying out dry etching on a third surface area of the epitaxial wafer, wherein the distance between a point in the third surface area and the edge of the epitaxial wafer is less than a fourth threshold value.
Optionally, the manufacturing method further includes:
and injecting oxygen ions into the second surface region of the electron generation layer in the groove.
Optionally, the manufacturing method further includes:
and forming a light absorption block on the circuit board between two adjacent light emitting chips, wherein the height of the light absorption block is consistent with that of the light emitting chips.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
the groove is formed in the edge of the electron generation layer, current injected by the N-type electrode cannot extend to the edge of the electron generation layer and further extends to the edge of the active layer, so that the edge of the electron generation layer provided by the electron generation layer is prevented from being injected into the active layer, magnesium ions are injected into the electron generation layer in the sub-region in the groove, the magnesium ions can neutralize electrons in the electron generation layer, the resistivity is increased, the edge of the electron generation layer provided by the electron generation layer is further prevented from being injected into the active layer, the edge of the active layer basically has no electrons and holes to perform composite light emitting, optical coupling between two adjacent Micro LEDs is reduced, and the definition of the boundary outline of a display image is improved. And firstly, the edge of the electron generation layer is provided with a groove, and then magnesium ions are injected into the electron generation layer in the sub-area in the groove, so that the problem that the active layer is damaged due to too deep groove can be avoided, and the problem that the electrons in the whole thickness area of the edge of the electron generation layer can not be neutralized due to limited injection depth of the magnesium ions can be solved. That is to say, the opening of the groove is matched with the injection of magnesium ions, so that the edge luminescence of the active layer can be effectively avoided, and the adverse effect can also be avoided as far as possible.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display array of micro light emitting diodes according to an embodiment of the present disclosure;
fig. 2 is a top view of a light emitting chip provided by an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing a display array of micro light emitting diodes according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
The disclosed embodiments provide a display array of micro light emitting diodes. Fig. 1 is a schematic structural diagram of a display array of micro light emitting diodes according to an embodiment of the present disclosure. Referring to fig. 1, the display array includes a circuit board 10 and a plurality of light emitting chips 20 spaced apart on the circuit board 10. Each of the light emitting chips 20 includes a P-type electrode 21, a hole generation layer 22, an active layer 23, an electron generation layer 24, and an N-type electrode 25, which are sequentially stacked on the circuit board 10. Fig. 2 is a top view of a light emitting chip provided in an embodiment of the present disclosure. Referring to fig. 2 and 1, the first surface region of the electron generation layer 24 is provided with a groove 100 extending toward the active layer 23, and a distance between a point in the first surface region and an edge of the light emitting chip 20 is less than a first threshold value a. The second surface region of the electron generation layer 24 within the groove 100 is implanted with magnesium ions, and a distance between a point within the second surface region and the edge of the light emitting chip 20 is between a second threshold value b, which is smaller than the third threshold value c, and a third threshold value c, which is smaller than the first threshold value a.
According to the embodiment of the disclosure, the groove is formed in the edge of the electron generation layer, the current injected by the N-type electrode cannot be expanded to the edge of the electron generation layer and further to the edge of the active layer, so that the electron provided by the electron generation layer is prevented from being injected to the edge of the active layer, magnesium ions are injected into the electron generation layer in the sub-region in the groove, the magnesium ions can neutralize the electrons in the electron generation layer, the resistivity is increased, the electron provided by the electron generation layer is further prevented from being injected to the edge of the active layer, the edge of the active layer basically has no electrons and holes to perform composite light emission, the optical coupling between two adjacent Micro LEDs is reduced, and the definition of the boundary outline of the displayed image is improved. And firstly, the edge of the electron generation layer is provided with a groove, and then magnesium ions are injected into the electron generation layer in the sub-area in the groove, so that the problem that the active layer is damaged due to too deep groove can be avoided, and the problem that the electrons in the whole thickness area of the edge of the electron generation layer can not be neutralized due to limited injection depth of the magnesium ions can be solved. That is to say, the opening of the groove is matched with the injection of magnesium ions, so that the edge luminescence of the active layer can be effectively avoided, and the adverse effect can also be avoided as far as possible.
Alternatively, as shown in FIG. 1, the thickness d of the electron generation layer 24 of the first surface region may be 0.4 μm to 0.6 μm, such as 0.5 μm; the minimum distance e between the magnesium ions in the electron generation layer 24 of the second surface region and the active layer 23 may be 0.08 μm to 0.12 μm, such as 0.1 μm.
By limiting the thickness of the electron generation layer of the first surface area and the minimum distance between the magnesium ions and the active layer in the electron generation layer of the second surface area, the composite luminescence of the active layer can be effectively prevented from being influenced by the opening of the groove and the injection of the magnesium ions.
Accordingly, the thickness of the electron generation layer 24 in the non-first surface region may be 1.4 μm to 1.6 μm, such as 1.5 μm; the electron generation layer 24 of the second surface region may have an implantation depth of magnesium ions of 0.38 μm to 0.42 μm, such as 0.4 μm.
Further, as shown in fig. 2, the second threshold b may be 0.25 μm to 0.35 μm, such as 0.3 μm; the third threshold c may be in the range 0.55 μm to 0.65 μm, such as 0.6 μm; the first threshold a may be in the range of 0.9 μm to 1.1 μm, such as 1 μm.
By limiting the width of the groove and selecting a proper position to inject magnesium ions into the groove, the light-emitting area of the active layer can be kept as much as possible under the condition that the edge of the active layer emits light to cause optical coupling between two adjacent light-emitting chips, and the light-emitting brightness of the light-emitting chips is ensured.
Alternatively, the injection concentration of magnesium ions in the electron generation layer 24 of the second surface region may be7*1019/cm3～9*1019/cm3E.g. 8 x 1019/cm3To neutralize the electrons in the electron generation layer as exactly as possible, avoiding current spreading to the maximum extent.
In practical applications, a mask may be disposed in a region other than the second surface region, for example, a patterned photoresist may be formed by using a photolithography technique, and an electric field is established in the reaction chamber, so that magnesium ions move toward the second surface region and are implanted into the second surface region under the action of the electric field.
Optionally, the second surface region of the electron generation layer 24 may also be implanted with oxygen ions.
By injecting oxygen ions, the second surface area can be further insulated, the resistivity of the injection area is increased, the edge of an electron injection active layer provided by an electron generation layer is avoided, so that electrons and holes are basically not generated at the edge of the active layer for composite light emission, optical coupling between two adjacent Micro LEDs is reduced, and the definition of the boundary outline of a displayed image is improved.
Further, the injection concentration of oxygen ions in the electron generation layer 24 of the second surface region may be 1 × 1017/cm3～5*1017/cm3E.g. 3 x 1017/cm3To effectively insulate the second surface area.
In practice, oxygen ions may be implanted into the second surface in the same manner as magnesium ions.
Alternatively, as shown in fig. 1, the display array may further include a light absorption block 30, the light absorption block 30 is disposed on the circuit board 10 between two adjacent light emitting chips 20, and the height of the light absorption block 30 is equal to the height of the light emitting chip 20.
Through set up the light absorption piece between two adjacent luminescence chips, can effectively absorb two adjacent luminescence chips and carry out the light of optical coupling, further effectively reduce the optical coupling between two adjacent Micro LED, improve the definition that shows image boundary profile.
Further, a surface of the light absorption block 30 opposite to the light emitting chip 20 may be provided with a V-shaped opening 31. In the V-shaped opening 31 of the portion of the light absorbing block 30 opposite to the electron generation layer 24, the side wall far from the circuit board 10 is parallel to the surface of the circuit board 10, and the included angle between the side wall near the circuit board 10 and the surface of the circuit board 10 is an acute angle. In the V-shaped opening 31 of the portion of the light absorption block 30 opposite to the active layer 23, the included angle between the side wall far away from the circuit board 10 and the surface of the circuit board 10 and the included angle between the side wall close to the circuit board 10 and the surface of the circuit board 10 are acute angles and equal in size. In the V-shaped opening 31 of the portion of the light absorbing block 30 opposite to the cavity generating layer 22, the included angle between the side wall far away from the circuit board 10 and the surface of the circuit board 10 is an acute angle, and the side wall near the circuit board 10 is parallel to the surface of the circuit board 10.
According to the direction of light emitted by the active layer and emitted to different areas on the opposite surface of the light absorption block, the angle of the side wall of the V-shaped opening is correspondingly adjusted, so that the light emitted by the active layer is favorably emitted into the V-shaped opening and then absorbed by the light absorption block, the optical coupling between two adjacent Micro LEDs is effectively reduced, and the definition of the boundary outline of a displayed image is improved.
For example, the thickness of the light emitting chip 20 is 5 micrometers, the active layer 23 is located at a position 102.5 micrometers away from the circuit board, the portion of the light absorption block 30 opposite to the hole generation layer 22 is located at a position 101.5 micrometers away from the circuit board, the portion of the light absorption block 30 opposite to the active layer 23 is located at a position 101.5 micrometers to 3.5 micrometers away from the circuit board, the portion of the light absorption block 30 opposite to the electron generation layer 24 is located at a position 103.5 micrometers to 4.8 micrometers away from the circuit board, and the portion of the light absorption block 30 opposite to the light emitting chip 20 at a position 104.8 micrometers to 5 micrometers away from the circuit board is not provided with the V-shaped opening 31, so that the light absorption block has certain.
Illustratively, the material of the light absorption block 30 may be silicon oxynitride. In practical application, the content of nitrogen components in the silicon oxynitride can be adjusted to change the corrosion rate of each region, and finally V-shaped openings with different shapes can be realized.
In practice, the circuit board 10 provides the connection circuitry for the display array. Further, the circuit board 10 may include a carrier, a driving circuit, and a heat conducting insulating layer stacked in sequence, and the heat conducting insulating layer is provided with a through hole extending to the driving circuit to electrically connect the light emitting chip and the driving circuit. Illustratively, the carrier may be a silicon wafer, a silicon carbide wafer or a ceramic wafer, and the driving circuit may include a plurality of Metal oxide semiconductor field effect (MOS) transistors and connecting wires.
The P-type electrode 21 and the N-type electrode 25 are respectively communicated with the positive electrode and the negative electrode of a power supply, and current is injected into the chip; the N-type electrode can be made of gold germanium alloy, and the P-type electrode can be made of gold beryllium alloy.
The hole generating layer 22 provides holes for recombination light emission, and the material of the hole generating layer may be magnesium-doped AlInGaP. The electron generation layer 24 provides electrons for recombination light emission, and the material of the electron generation layer may be silicon-doped AlInGaP. The active layer 23 performs recombination light emission of electrons and holes, and the material of the active layer may be one of undoped AlInGaP, InGaN, and ZnO.
Optionally, as shown in fig. 1, the light emitting chip 20 may further include a transparent conductive layer 26, and the transparent conductive layer 26 is disposed between the hole generation layer 22 and the P-type electrode 21, and forms a good ohmic contact with the electrode on one hand, and spreads the current injected from the electrode on the other hand. Furthermore, the material of the transparent conductive layer 26 may be Indium Tin Oxide (ITO) or NiAu alloy.
Alternatively, the thickness of the light emitting chip 20 may be less than or equal to 5 micrometers. Because the Micro LED is small in size, the problem of current expansion does not exist, the whole thickness can be properly reduced, and the reduction of the volume resistance is facilitated.
Optionally, as shown in fig. 1, the light emitting chip 20 may further include a passivation protection layer 27, and the passivation protection layer 27 is disposed on the electron generation layer 24 and can effectively prevent oxygen and water vapor in the air from corroding the LED.
The embodiment of the disclosure provides a method for manufacturing a display array of a micro light-emitting diode, which is suitable for manufacturing the display array of the micro light-emitting diode shown in fig. 1. Fig. 3 is a flowchart of a method for manufacturing a display array of micro light emitting diodes according to an embodiment of the present disclosure. Referring to fig. 3, the manufacturing method includes:
step 201: an electron generation layer, an active layer and a hole generation layer are sequentially formed on a growth substrate to form an epitaxial wafer.
Alternatively, the material of the growth substrate may employ one of gallium arsenide, silicon, or germanium.
Optionally, the step 201 may include:
an electron generation layer, an active layer and a hole generation layer are sequentially formed on a growth substrate by using a Metal-organic Chemical vapor deposition (MOCVD) technology.
Illustratively, the thickness of the electron generation layer may be 1.5 micrometers, and the growth temperature may be 800 ℃; the active layer may include 5 pairs of quantum wells and quantum barriers using AlInGaP with different aluminum composition content.
In practical application, an etch stop layer is usually formed on a growth substrate, and then an electron generation layer, an active layer and a hole generation layer are sequentially grown on the etch stop layer, so that the electron generation layer, the active layer and the hole generation layer are protected by the etch stop layer in the subsequent wet etching process for removing the growth substrate.
Further, a buffer layer may also be grown prior to growing the N-type confinement layer to provide nucleation centers and to mitigate lattice mismatch between the foreign substrate and the epitaxial material. Illustratively, the thickness of the buffer layer may be 2 micrometers, and the growth temperature of the buffer layer may be 300 ℃.
Step 202: the hole generating layer is bonded to the glass substrate.
Optionally, this step 202 may include:
forming silicon oxide layers on the hole generation layer and the glass substrate, respectively;
polishing and activating the silicon oxide layer;
the hole generation layer and the silicon oxide layer on the glass substrate are bonded together by pressure.
Further, the activation treatment can be performed on the surface of the silicon oxide layer by using a KOH solution or a hydrochloric acid solution, so that the smoothness of the surface of the silicon oxide layer is improved, and the two silicon oxide layers can be bonded to form a layer.
Optionally, before step 202, the manufacturing method may further include:
and performing dry etching on a third surface area of the epitaxial wafer before bonding the hole generation layer on the glass substrate, wherein the distance between a point in the third surface area and the edge of the epitaxial wafer is less than a fourth threshold value.
Because the concentration of the reaction gas in the edge region of the substrate is higher than that in the middle region of the substrate in the epitaxial growth process, more epitaxial materials are deposited in the edge region of the substrate, so that the edge region of the substrate is raised, and the surface of the whole epitaxial product is uneven. And need carry out the substrate transfer in the manufacturing process of Micro LED display array, with the display array bonding to new substrate on, because there is the arch in the edge region, consequently the not firm condition of bonding can appear in the bonding process, and then causes the chip to appear dark injuries such as crackle, the problem that the epitaxial layer drops even, causes the hidden danger to the reliability of display array, is unfavorable for Micro LED's popularization and use.
According to the embodiment of the disclosure, the edge of the epitaxial wafer is etched before the substrate is transferred, so that the edge difference of the epitaxial wafer is not higher than that of the middle area, the condition of infirm bonding is avoided, the bonding quality is effectively improved, and the reliability of the Micro LED is improved.
Illustratively, the height of the bump is 0.5 microns, then the depth of the dry etching may be 1 micron; if the radial dimension of the protrusion is 1 μm, the fourth threshold may be 1.2 mm to 1.8 mm, for example, 1.5 mm, so as to ensure that the surface of the epitaxial wafer is flat, which is beneficial to subsequent bonding.
Step 203: and removing the growth substrate by adopting a wet etching mode.
In practical applications, after the substrate is removed, the etch stop layer is also removed.
Step 204: the electron generation layer is bonded to the sapphire substrate.
In practical application, the sapphire substrate can be replaced by a substrate formed by one of gallium phosphide, silicon carbide, zinc oxide, silicon nitride and glass.
Optionally, this step 204 may include:
the electron generation layer is bonded to the sapphire substrate using Polyimide (PI) tape or SU-8 photoresist.
Step 205: and removing the glass substrate.
Optionally, this step 205 may include:
and removing the glass substrate by using an etching solution.
Step 206: a P-type electrode is formed on the hole generation layer.
In practical application, the epitaxial wafer is arranged on the sapphire substrate, so that the P-type electrode can be directly formed by adopting the existing process.
Step 207: the P-type electrode is bonded to the circuit board.
Optionally, this step 207 may include:
respectively forming metal layers on the P-type electrode and the circuit board;
and bonding the P-type electrode and the metal layer on the circuit board together by heating.
Step 208: and removing the sapphire substrate by adopting a laser stripping mode.
The sapphire substrate is transparent and can be removed in a laser stripping mode, so that the circuit board is prevented from being damaged by wet corrosion.
Step 209: a groove extending towards the active layer is formed in the first surface area of the electron generation layer, and the distance between a point in the first surface area and the edge of the epitaxial wafer is smaller than a first threshold value.
Optionally, this step 209 may include:
forming photoresist on the non-first surface area of the electron generation layer by adopting a photoetching technology;
dry etching the first surface area of the electron generation layer to form a groove;
and removing the photoresist.
Step 210: magnesium ions are implanted into a second surface region of the electron generation layer in the groove, the distance between a point in the second surface region and the edge of the epitaxial wafer is between a second threshold value and a third threshold value, the second threshold value is smaller than the third threshold value, and the third threshold value is smaller than the first threshold value.
Optionally, the manufacturing method may further include:
oxygen ions are implanted into the second surface region of the electron generation layer in the recess.
Step 211: and forming an N-type electrode on the electron generation layer outside the groove to form a light-emitting chip.
Optionally, before step 211, the manufacturing method may further include:
laying a passivation protective material on the electron generation layer;
forming photoresist with a set pattern on the passivation protection material;
etching the passivation protective material which is not covered by the photoresist by a wet method, and forming a passivation protective layer by the left passivation protective material;
and removing the photoresist.
Illustratively, the passivation protection material may be applied using a CVD technique and the photoresist may be formed using a photolithography technique.
Optionally, the manufacturing method may further include:
and a light absorption block is formed between two adjacent light emitting chips, and the height of the light absorption block is consistent with that of the light emitting chips.
Further, the surface of the light absorption block opposite to the light emitting chip may be provided with a V-shaped opening. In the V-shaped opening of the part of the light absorption block opposite to the electron generation layer, the side wall far away from the circuit board is parallel to the surface of the circuit board, and the included angle between the side wall close to the circuit board and the surface of the circuit board is an acute angle. In the V-shaped opening of the part of the light absorption block opposite to the active layer, the included angle between the side wall far away from the circuit board and the surface of the circuit board and the included angle between the side wall close to the circuit board and the surface of the circuit board are acute angles and equal in size. In the V-shaped opening of the part of the light absorption block opposite to the cavity generation layer, the included angle between the side wall far away from the circuit board and the surface of the circuit board is an acute angle, and the side wall close to the circuit board is parallel to the surface of the circuit board.
According to the direction of light emitted by the active layer and emitted to different areas on the opposite surface of the light absorption block, the angle of the side wall of the V-shaped opening is correspondingly adjusted, so that the light emitted by the active layer is favorably emitted into the V-shaped opening and then absorbed by the light absorption block, the optical coupling between two adjacent Micro LEDs is effectively reduced, and the definition of the boundary outline of a displayed image is improved.
For example, the thickness of the light-emitting chip is 5 micrometers, the active layer is at a position 2.5 micrometers away from the circuit board, the part of the light-absorbing block opposite to the hole generation layer is at a position 1.5 micrometers to 3.5 micrometers away from the circuit board, the part of the light-absorbing block opposite to the active layer is at a position 3.5 micrometers to 4.8 micrometers away from the circuit board, and the part of the light-absorbing block opposite to the light-emitting chip at a position 4.8 micrometers to 4.8 micrometers away from the circuit board is not provided with a V-shaped opening, so that the light-absorbing block has certain firmness.
Illustratively, the material of the light absorption block may adopt silicon oxynitride. In practical application, the content of nitrogen components in the silicon oxynitride can be adjusted to change the corrosion rate of each region, and finally V-shaped openings with different shapes can be realized.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. The display array of the miniature light-emitting diode is characterized by comprising a circuit board (10) and a plurality of light-emitting chips (20) which are arranged on the circuit board (10) at intervals; each light-emitting chip (20) comprises a P-type electrode (21), a hole generation layer (22), an active layer (23), an electron generation layer (24) and an N-type electrode (25) which are sequentially stacked on the circuit board (10); a first surface region of the electron generation layer (24) is provided with a groove (100) extending towards the active layer (23), and a distance between a point in the first surface region and an edge of the light emitting chip (20) is smaller than a first threshold value; a second surface region of the electron generation layer (24) within the recess (100) is implanted with magnesium ions, a distance between a point within the second surface region and an edge of the light emitting chip (20) is between a second threshold value and a third threshold value, the second threshold value being smaller than the third threshold value, the third threshold value being smaller than the first threshold value.
2. The display array according to claim 1, wherein the thickness of the electron generation layer (24) of the first surface region is 0.4 μm to 0.6 μm, and the minimum distance between the magnesium ions in the electron generation layer (24) of the second surface region and the active layer (23) is 0.08 μm to 0.12 μm.
3. The display array of claim 2, wherein the second threshold is 0.25 μm to 0.35 μm, the third threshold is 0.55 μm to 0.65 μm, and the first threshold is 0.9 μm to 1.1 μm.
4. A display array according to any of claims 1 to 3, wherein the second surface region of the electron generating layer (24) is further implanted with oxygen ions.
5. The display array according to any of claims 1 to 3, further comprising a light absorption block (30), wherein the light absorption block (30) is disposed on the circuit board (10) between two adjacent light emitting chips (20), and the height of the light absorption block (30) is equal to the height of the light emitting chips (20).
6. The display array according to claim 5, wherein the surface of the light absorbing block (30) opposite to the light emitting chip (20) is provided with a V-shaped opening (31); in the V-shaped opening (31) of the part of the light absorption block (30) opposite to the electron generation layer (24), the side wall far away from the circuit board (10) is parallel to the surface of the circuit board (10), and the included angle between the side wall close to the circuit board (10) and the surface of the circuit board (10) is an acute angle; in the V-shaped opening (31) of the part, opposite to the active layer (23), of the light absorption block (30), the included angle between the side wall far away from the circuit board (10) and the surface of the circuit board (10) and the included angle between the side wall close to the circuit board (10) and the surface of the circuit board (10) are acute angles and equal in size; in the V-shaped opening (31) of the relative part of the light absorption block (30) and the cavity generation layer (22), an included angle between the side wall far away from the circuit board (10) and the surface of the circuit board (10) is an acute angle, and the side wall close to the circuit board (10) is parallel to the surface of the circuit board (10).
7. A manufacturing method of a display array of a micro light emitting diode is characterized by comprising the following steps:
sequentially forming an electron generation layer, an active layer and a hole generation layer on a growth substrate to form an epitaxial wafer;
bonding the hole generating layer to a glass substrate;
removing the growth substrate by adopting a wet etching mode;
binding the electron generation layer to a sapphire substrate;
removing the glass substrate;
forming a P-type electrode on the hole generation layer;
bonding the P-type electrode to a circuit board;
removing the sapphire substrate by adopting a laser stripping mode;
forming a groove extending towards the active layer in a first surface region of the electron generation layer, wherein the distance between a point in the first surface region and the edge of the epitaxial wafer is smaller than a first threshold value;
magnesium ions are implanted into a second surface region of the electron generation layer in the groove, the distance between a point in the second surface region and the edge of the epitaxial wafer is between a second threshold value and a third threshold value, the second threshold value is smaller than the third threshold value, and the third threshold value is smaller than the first threshold value;
and forming an N-type electrode on the electron generation layer outside the groove to form a light-emitting chip.
8. The method of manufacturing of claim 7, further comprising:
and before bonding the hole generation layer on the glass substrate, carrying out dry etching on a third surface area of the epitaxial wafer, wherein the distance between a point in the third surface area and the edge of the epitaxial wafer is less than a fourth threshold value.
9. The method of manufacturing according to claim 7 or 8, further comprising:
and injecting oxygen ions into the second surface region of the electron generation layer in the groove.
10. The method of manufacturing according to claim 7 or 8, further comprising:
and forming a light absorption block on the circuit board between two adjacent light emitting chips, wherein the height of the light absorption block is consistent with that of the light emitting chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911051010.7A CN110993758B (en) | 2019-10-31 | 2019-10-31 | Display array of micro light-emitting diode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911051010.7A CN110993758B (en) | 2019-10-31 | 2019-10-31 | Display array of micro light-emitting diode and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110993758A true CN110993758A (en) | 2020-04-10 |
| CN110993758B CN110993758B (en) | 2020-12-22 |
Family
ID=70082710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911051010.7A Active CN110993758B (en) | 2019-10-31 | 2019-10-31 | Display array of micro light-emitting diode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110993758B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038333A (en) * | 2020-07-16 | 2020-12-04 | 华灿光电（浙江）有限公司 | Micro light-emitting diode display array and manufacturing method thereof |
| WO2023142142A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led, micro led array panel and manufacuturing method thereof |
| WO2023142140A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led, micro led array panel and manufacuturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5827753A (en) * | 1997-03-20 | 1998-10-27 | Motorola, Inc. | Monolithic integration of driver circuits with LED array and methods of manufacture |
| CN101164209A (en) * | 2005-03-14 | 2008-04-16 | 飞利浦拉米尔德斯照明设备有限责任公司 | Polarization-reversed iii-nitride light emitting device |
| CN102227954A (en) * | 2008-12-01 | 2011-10-26 | 伊菲雷知识产权公司 | Surface-emission light source with uniform illumination |
| CN109216516A (en) * | 2017-06-30 | 2019-01-15 | 英属开曼群岛商錼创科技股份有限公司 | Micro-led and display panel |
-
2019
- 2019-10-31 CN CN201911051010.7A patent/CN110993758B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5827753A (en) * | 1997-03-20 | 1998-10-27 | Motorola, Inc. | Monolithic integration of driver circuits with LED array and methods of manufacture |
| CN101164209A (en) * | 2005-03-14 | 2008-04-16 | 飞利浦拉米尔德斯照明设备有限责任公司 | Polarization-reversed iii-nitride light emitting device |
| CN102227954A (en) * | 2008-12-01 | 2011-10-26 | 伊菲雷知识产权公司 | Surface-emission light source with uniform illumination |
| CN109216516A (en) * | 2017-06-30 | 2019-01-15 | 英属开曼群岛商錼创科技股份有限公司 | Micro-led and display panel |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038333A (en) * | 2020-07-16 | 2020-12-04 | 华灿光电（浙江）有限公司 | Micro light-emitting diode display array and manufacturing method thereof |
| WO2023142142A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led, micro led array panel and manufacuturing method thereof |
| WO2023142140A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led, micro led array panel and manufacuturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110993758B (en) | 2020-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110993758B (en) | Display array of micro light-emitting diode and manufacturing method thereof | |
| US10249789B2 (en) | Light emitting diode chip and fabrication method | |
| KR101393785B1 (en) | Semiconductor light emitting device and manufacturing method thereof | |
| US7544971B2 (en) | Lateral current blocking light-emitting diode and method for manufacturing the same | |
| KR100872717B1 (en) | Light emitting device and manufacturing method thereof | |
| EP3089225B1 (en) | Micro-light-emitting diode | |
| US6781147B2 (en) | Lateral current blocking light emitting diode and method of making the same | |
| US10020422B1 (en) | Mesa shaped micro light emitting diode with bottom N-contact | |
| JPH06296041A (en) | Gallium nitride compound semiconductor light-emitting element | |
| KR20110077707A (en) | Vertical light emitting diode and manufacturing method of the same | |
| CN112038333B (en) | Micro light-emitting diode display array and manufacturing method thereof | |
| CN111446335B (en) | Light emitting diode and preparation method thereof | |
| US10418510B1 (en) | Mesa shaped micro light emitting diode with electroless plated N-contact | |
| US10535797B2 (en) | Light emitting diode apparatus and method of manufacturing the same | |
| KR101525913B1 (en) | Verticle light emitting diodes and its fabricating method | |
| KR100699056B1 (en) | Light emitting diode having a plurality of light emitting cells and mehod for fabricating the same | |
| TWI453968B (en) | Semiconductor light-emitting structure | |
| CN101855737B (en) | Light-emitting element and a production method therefor | |
| CN101116191A (en) | Light emitting device having a plurality of light emitting cells and method of fabricating the same | |
| JP7398794B2 (en) | Semiconductor light emitting device array | |
| CN111180478B (en) | Micro light-emitting diode epitaxial wafer, display array and manufacturing method thereof | |
| CN111180379B (en) | Micro light-emitting diode epitaxial wafer, display array and manufacturing method thereof | |
| KR100693408B1 (en) | Silicon-Based LED and Fabricating Method Thereof | |
| KR102563505B1 (en) | Led device and method of manufacturing the same | |
| TWI436497B (en) | Method for forming a light-emitting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |