CN110993652A - Camera structure under screen - Google Patents
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- CN110993652A CN110993652A CN201911157270.2A CN201911157270A CN110993652A CN 110993652 A CN110993652 A CN 110993652A CN 201911157270 A CN201911157270 A CN 201911157270A CN 110993652 A CN110993652 A CN 110993652A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
Abstract
A camera structure under a screen comprises a display screen, wherein the display screen comprises an anti-reflection OLED panel, a lens module is arranged under the anti-reflection OLED panel, the anti-reflection OLED panel is manufactured through the following steps that a buffer layer is formed on a substrate, an active layer is patterned on the buffer layer in a thin film transistor area, a grid electrode insulating layer is patterned on the active layer, a first conductive film layer and a grid electrode layer are integrally formed, all grid metal is etched in a capacitor area, the grid metal and the first conductive film layer are reserved in the thin film transistor area, and the grid metal and the conductive film layer are etched in other areas according to the patterning requirements; patterning the second insulating layer to expose the active layer in the thin film transistor region and cover the first conductive film layer in the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor area, and reserving a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is in contact with the active layer through the second conductive film layer. Above-mentioned scheme has been solved and can be shown the regional below and set up the problem of the module of making a video recording.
Description
Technical Field
The invention relates to the field of new comprehensive screen design, in particular to a comprehensive screen structure for increasing the light transmittance of a panel camera part area.
Background
With the development of display technology, various new technologies are emerging, and the transparent display technology is receiving more and more attention due to the characteristic of the transparent display panel and its unique application.
The core of the transparent display technology is a transparent display panel, which is a transparent panel capable of displaying images, unlike a double-sided display panel, which is a display device capable of displaying images on both sides of a display panel simultaneously. When the transparent display panel is closed, the panel is like a piece of transparent glass, and when the transparent display panel works, a viewer can view the content displayed on the panel and can see objects behind the panel through the panel.
Smart mobile phones have developed to now, and the function that can realize has been more and more, and people have used gradually to carry out social contact, play games and see the indispensable activity in daily life such as video with the cell-phone, and people also more and more like the visual angle big simultaneously, the cell-phone of large screen, but leading camera has occupied a lot of screen positions, accounts for in order to reach higher screen, improves display effect, and the concept of comprehensive screen is in the future born. The 'comprehensive' of the full-face screen is a good desire of the people, but due to various technical reasons, the full-face screen cannot achieve true completeness, and although the visual tendency makes the mechanical design of automatically popping and pushing the sliding cover great, the design scheme which considers the aesthetic feeling and the use efficiency is the final way of designing the mobile phone without question. An off-screen camera is just a design solution that is both aesthetic and efficient to use, and seems to be the trend.
Disclosure of Invention
Therefore, it is desirable to provide a new screen structure design to improve the transmittance of the capacitor area and design the overall screen structure of the camera under the screen accordingly.
In order to achieve the above object, the present invention provides a camera structure under a screen, which includes a display screen, wherein the display screen includes an anti-reflection OLED panel, a lens module is disposed under the anti-reflection panel, and the anti-reflection OLED panel is manufactured by forming a film on a substrate as a buffer layer, patterning an active layer on the buffer layer in a thin film transistor area, patterning a gate insulating layer on the active layer, forming a first conductive film layer and a gate layer as a whole, etching all gate metals in a capacitor area, leaving the gate metals and the first conductive film layer in the thin film transistor area, and etching the gate metals and the conductive film layers in other areas according to patterning requirements; patterning the second insulating layer to expose the active layer in the thin film transistor region and cover the first conductive film layer in the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor area, and reserving a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is in contact with the active layer through the second conductive film layer. The method also comprises a manufacturing step of manufacturing a passivation layer and etching to expose the drain metal, then arranging a flat layer and a pixel definition layer, and etching the flat layer and the pixel definition layer on the capacitor area.
Further, all the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer are remained in the thin film transistor region, and the gate metal and the conductive film layer are etched in other regions according to the patterning requirement, specifically,
coating a photoresist on a grid layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a grid wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the grid metal of the capacitance area and the photoresist of the grid wiring part.
Further, all electrode metal is etched in the capacitor area, and a source drain and a second conductive film layer are reserved in the thin film transistor area, specifically,
coating a photoresist on an electrode layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a source drain wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the electrode metal and the second conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the electrode metal of the capacitance area and the photoresist of the electrode wiring part.
The transparent conductive film and the metal film layer are partially formed on the lens module in the screen, and the gray-scale photomask is combined, so that only the transparent conductive film is reserved in the pixel capacitance area, and no metal or flat layer exists, the area of the metal film layer of the panel is further reduced, the light transmittance of the panel is increased, the capacitance area and the transmission window are integrated, the pixel density is improved, and the technical effect of clearer photographing of the lens module under the screen is achieved.
Drawings
FIG. 1 is a schematic cross-sectional view of an OLED panel according to an embodiment;
FIG. 2 is a schematic diagram comparing the prior art with the present embodiment;
FIG. 3 is a schematic diagram of a pixel design according to an embodiment;
fig. 4 is a schematic structural diagram of an array substrate according to an embodiment;
FIG. 5 is a schematic diagram of a panel manufacturing process according to an embodiment;
FIG. 6 is an embodiment of a transparent capacitor plate according to an embodiment;
fig. 7 is a schematic structural diagram of an array substrate according to an embodiment;
FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment;
FIG. 9 is a flow chart illustrating a panel manufacturing process according to an embodiment;
FIG. 10 is a diagram of a basic array structure according to an embodiment;
FIG. 11 is a schematic diagram of a full screen according to an embodiment;
fig. 12 is a schematic structural diagram of an off-screen lens module according to an embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Fig. 1 is a design diagram of a novel OLED panel according to the present invention, and an OLED panel includes a thin film transistor region and a capacitor region, as shown in the figure, the thin film transistor region (hereinafter referred to as TFT region) is located at the center of a cross-sectional view, i.e., a portion for routing lines, in the figure, the left side shows a structure of the capacitor region, and the right side is a light-transmitting region. From the figure we can see. The capacitor region includes capacitor plates, which can be used to stabilize the electrical operation of the TFT. In the technical scheme, the capacitor area does not comprise a metal layer, and the polar plates of the capacitor area are changed into transparent conductive film layers by not arranging the light-shielding metal layer. The scheme of the invention also enables the source electrode and the drain electrode to be lapped with the active layer through the transparent conductive film, so that the ohmic resistance can be reduced, and the electrical characteristics of the thin film transistor are further improved.
Fig. 2 further shows the effect of the present invention compared with the conventional design, the capacitor metal layer in the conventional technical scheme is compatible with the source drain metal and the gate metal on the TFT plate in the manufacturing process, and the patterning is simple and convenient, but the transparency of the panel is not improved only by the transmission window under the condition that the capacitor region occupies a large pixel position. FIG. 3 shows some embodiments of pixel designs, in which the transparency of the whole panel is greatly improved when the capacitor region is designed to be transparent.
Fig. 4 shows an embodiment of the present invention, which shows a specific structure of the array substrate in the panel. The film layer structure of the TFT area sequentially comprises a transparent substrate as a base, a grid scanning line GE, a grid insulating layer GI, an active layer IGZO, an etching barrier layer ES, a source and drain signal line SD and a passivation layer PV from bottom to top. In a specific design, we can see that the capacitor plates include a gate insulating layer or an etching barrier layer therebetween. The capacitor area comprises a substrate, a capacitor lower electrode plate, a grid electrode insulating layer, an etching barrier layer, a capacitor upper electrode plate, a passivation layer and a flat layer which are arranged from bottom to top. And in the thin film transistor area, the conductive film layers are arranged between the source and drain electrodes and the active layer and between the grid scanning line and the substrate. Besides the passivation layer, a flat layer is arranged. The thin film transistor area comprises a substrate, a first conductive film layer, a grid electrode insulating layer, an active layer, a second conductive film layer, an etching barrier layer, a source drain electrode layer, a passivation layer and a flat layer which are arranged from bottom to top. The panel structure designed by the scheme can increase the transmissivity of the capacitor and simultaneously improve the electrical property of the active layer.
In order to manufacture the panel of the transparent capacitor, the method for manufacturing the OLED panel comprises the following steps of preparing a substrate, sequentially forming a first conductive film layer and a gate electrode layer on the substrate, etching all gate metal in a capacitor area, reserving the gate metal and the first conductive film layer in a thin film transistor area, and etching the gate metal and the conductive film layer in other areas according to patterning requirements;
and then, manufacturing a gate insulating layer, manufacturing an active layer in a thin film transistor area, manufacturing an etching barrier layer and reserving a via hole, sequentially forming a second conductive film layer and an electrode layer, etching all electrode metal in a capacitor area, reserving a source drain electrode and the second conductive film layer in the thin film transistor area, and enabling the source drain electrode to be in contact with the active layer through the second conductive film layer. Further, the method comprises the step of manufacturing a flat layer and a pixel definition layer.
Specific implementation details we can look from one of fig. 5. As shown in fig. 5, the preparation of the OLED panel in the scheme of the present invention includes the following steps:
01. GE: forming a first metal layer on a substrate to manufacture a gate drive circuit and a first electrode plate of a capacitor area;
02. GI: manufacturing a grid electrode insulating layer on the grid electrode;
03. and SE: manufacturing an active layer IGZO or other metal oxides and other materials on the grid;
04. ES: manufacturing an etching barrier layer on the active layer, protecting a channel of the active layer, and etching a via hole to connect the active layer with a source/drain;
05. SD: manufacturing a source/drain circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;
06. PV: manufacturing a passivation layer on the source/drain electrode, etching a through hole to expose the surface of the drain electrode, and etching a through hole at the transmission window to expose the surface of the substrate to increase the transparency of the panel;
07. OP: manufacturing an organic flat layer on the passivation layer, developing an OP through hole exposed drain electrode on the PV through hole, and exposing the surface of the substrate at the projection window;
08. AN: manufacturing transparent anodes such as ITO on the flat layer and patterning, wherein the anode AN is connected with the drain electrode through the OP/IP through hole;
09. PD: manufacturing an organic pixel definition layer, and developing an RGB pattern opening and a transmission window through hole;
10. PS: patterning the PS layer of the supporting substrate and the packaging cover plate;
11. an OLED light emitting layer: an organic light-emitting layer is evaporated on the anode at the PD via hole;
12. metal cathode: and evaporating a transparent metal cathode.
An embodiment of the fabrication of transparent capacitor plates on a substrate is shown in the example of fig. 6, comprising the steps of,
step1, continuously forming a transparent conductive layer and a metal film layer, wherein the transparent conductive layer can be preferably ITO (indium tin oxide), the material is not particularly limited, and the metal film layer can be one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity and alloys;
step2, exposing by using a half-color mask, wherein the light transmittance of the capacitor area is 50%, the transmittance of the grid wiring area is 0%, and the transmittance of the other areas is 100%;
step3, developing the photoresist layer by using a developing solution after exposure, completely removing the photoresist in the 100% transmittance area of the photomask, keeping the photoresist in the 50% and 0% transmittance areas, and thinning the photoresist in the 50% transmittance area compared with the photoresist in the 0% transmittance area;
step4, etching the film layer to primarily transfer the photomask pattern, wherein the metal and ITO etching can be performed for one-time etching or secondary etching according to the film material;
step5, removing the 50% light transmittance area light resistance through ashing treatment;
and step6, etching is carried out again after ashing treatment, metal above the 50% light transmittance area is removed through etching time control or selectivity of etching liquid medicine, square ITO is remained, and then residual photoresist is removed to finish pattern transfer.
Therefore, referring to fig. 6, all the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer remain in the tft region, and the gate metal and the conductive film layer are etched in other regions according to the patterning requirement, specifically,
coating a photoresist on a grid layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a grid wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the grid metal of the capacitance area and the photoresist of the grid wiring part.
On the other hand, all electrode metals are etched in the capacitor area, and a source drain and a second conductive film layer are reserved in the thin film transistor area, which is also basically similar, and the method comprises the following steps:
coating a photoresist on an electrode layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a source drain wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the electrode metal and the second conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the electrode metal of the capacitance area and the photoresist of the electrode wiring part.
In other preferred embodiments, when the metal cathode is evaporated, the light transmittance can be further increased by adopting a mask plate for evaporation, and a cathode metal film layer structure is not remained in the transmission window area.
In the embodiment shown in fig. 7, another structural scheme of the array substrate is shown, and a film structure in a TFT thin film transistor region is formed by sequentially forming a gate scan line GE, a gate insulating layer GI (first insulating layer), an active layer SE, a source/drain signal line SD, and a passivation layer PV on a transparent substrate. The transparent capacitor region also includes first and second conductive film layers sandwiching the first insulating layer therebetween in this configuration.
Fig. 8 shows another structure of an array substrate in the embodiment, the TFT film structure of the present invention sequentially includes, from bottom to top:
BF: buffer layer
2, SE: active layer (Metal oxide)
3, GI: gate insulating layer (first insulating layer)
4, GE: metal grid (first metal layer)
IL: a second insulating layer
SD: metal source drain (second metal layer)
PV: a passivation layer (third insulating layer).
Fig. 9 illustrates a method of manufacture corresponding to the configuration of fig. 8, including the steps of:
01. BF: forming a film buffer layer on the glass substrate, wherein the optional material is organic material, SiOx, SiNx, titanium oxide, aluminum oxide and the like;
02. and SE: forming a film on the buffer layer and patterning the active layer IGZO or other metal oxide materials;
03. GI: forming a film on the active layer and patterning a gate insulating layer, wherein SiOx, SiNx, titanium oxide, aluminum oxide and the like can be selected;
04. GE: forming a first metal layer on the gate insulating layer to manufacture a gate drive circuit and a first electrode plate of the capacitor region, wherein one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium and the like and alloys are adopted;
05. IL: forming a film on the grid metal layer and patterning a second insulating layer, wherein SiOx, SiNx, titanium oxide, aluminum oxide and the like can be selected;
06. SD: manufacturing a source/drain circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;
07. PV: and forming a film on the source/drain electrode and patterning a passivation layer, wherein the metal surface of the drain electrode and the surface of the glass substrate are exposed and made of organic materials, SiOx, SiNx, titanium oxide, aluminum oxide and the like.
By the scheme, the OLED panel structure with the transparent capacitor area can be manufactured.
Therefore, the scheme also comprises the following steps of forming a buffer layer on the substrate, patterning an active layer on the buffer layer in the thin film transistor area, patterning a grid insulation layer on the active layer, integrally forming a first conductive film layer and a grid layer, etching all grid metal in the capacitor area, reserving the grid metal and the first conductive film layer in the thin film transistor area, and etching the grid metal and the conductive film layer in other areas according to the patterning requirement; patterning the second insulating layer to expose the active layer in the thin film transistor region and cover the first conductive film layer in the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor area, and reserving a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is in contact with the active layer through the second conductive film layer.
Specifically, the method further comprises the steps of manufacturing a passivation layer, etching to expose the drain metal, and arranging a flat layer and a pixel defining layer.
Further, all the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer are remained in the thin film transistor region, and the gate metal and the conductive film layer are etched in other regions according to the patterning requirement, specifically,
coating a photoresist on a grid layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a grid wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the grid metal of the capacitance area and the photoresist of the grid wiring part.
Further, all electrode metal is etched in the capacitor area, and a source drain and a second conductive film layer are reserved in the thin film transistor area, specifically,
coating a photoresist on an electrode layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a source drain wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the electrode metal and the second conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the electrode metal of the capacitance area and the photoresist of the electrode wiring part.
In the method, the transparent conductive film and the metal film layer are formed, and the gray-scale photomask is combined, so that only the transparent conductive film is reserved in the pixel capacitance area, the area of the metal film layer of the panel is further reduced, and the light transmittance of the panel is increased.
In other embodiments, as shown in fig. 10, our solution can be further modified to reduce the original solution that the transmission window is separated from the transparent capacitor, and the planarization layer and the pixel definition layer on the capacitor area are removed by patterning or etching. The method comprises the steps of manufacturing a passivation layer, etching to expose a drain metal, and disposing a planarization layer and a pixel defining layer, wherein the pixel defining layer is in contact with the drain metal, and an organic light emitting layer is formed on the pixel defining layer in the thin film transistor region. The flat layer and the pixel defining layer in the capacitor region are all etched, and as can be seen from the figure, the capacitor region only has the first conductive film layer and the second conductive film layer of the transparent capacitor, and the etching barrier layer and the gate insulating layer are arranged between the first conductive film layer and the second conductive film layer; there is also a passivation layer designed on the transparent capacitor. The planarization layer and the pixel definition layer are etched. Forming a V-shaped opening. Through such design, can make electric capacity region and open region obtain integrating in the space, when guaranteeing the panel light transmissivity, also saved the space demand better, improved the pixel ratio of panel.
In the embodiment of fig. 11, an application example of the high-transparency panel is shown, in the full-screen, the above-mentioned OLED high-transparency panel may be used, so that a plurality of anti-reflection areas may be formed in the full-screen, the anti-reflection areas may be in various embodiments such as a circle, a square at a bang position, and the like, and the rest of the panels are normally displayed, and a common OLED panel in the prior art may be used. The anti-reflection area uses the high-transparency OLED panel in the scheme, a camera module can be arranged below the anti-reflection area and used for acquiring image data, a specific setting of a camera structure under a screen is shown in FIG. 12, in an actual situation, the area of a transparent capacitor is far larger than that of an opaque area, the anti-reflection area can ensure normal light intake, a light-emitting signal of the panel in the anti-reflection area can be cancelled through preset program setting during use, and the influence of pixel light emission on a camera collecting signal can be reduced or avoided. The technical effect that the optical input signals are collected by the camera under the screen is achieved.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (3)
1. A camera structure under screen comprises a display screen, the display screen comprises an OLED panel, a lens module is arranged under the panel, the OLED panel is manufactured by the following steps,
forming a buffer layer on a substrate, patterning an active layer on the buffer layer in a thin film transistor area, patterning a gate insulating layer on the active layer, integrally forming a first conductive film layer and a gate electrode layer, etching all gate metal in a capacitor area, reserving the gate metal and the first conductive film layer in the thin film transistor area, and etching the gate metal and the conductive film layer in other areas according to the patterning requirement; patterning the second insulating layer to expose the active layer in the thin film transistor region and cover the first conductive film layer in the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitance area, keeping a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is in contact with the active layer through the second conductive film layer.
2. The under-screen camera structure of claim 1, wherein all of the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer remain in the thin film transistor region, and the gate metal and the conductive film layer are etched in other regions according to patterning requirements, specifically,
coating a photoresist on a grid layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a grid wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the grid metal of the capacitance area and the photoresist of the grid wiring part.
3. The underscreen camera structure of claim 1, wherein all electrode metal is etched in the capacitor region, and source and drain electrodes and the second conductive film layer are remained in the thin film transistor region, specifically,
coating a photoresist on an electrode layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a source drain wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the electrode metal and the second conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the electrode metal of the capacitance area and the photoresist of the electrode wiring part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911157270.2A CN110993652B (en) | 2019-11-22 | 2019-11-22 | Under-screen camera structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911157270.2A CN110993652B (en) | 2019-11-22 | 2019-11-22 | Under-screen camera structure |
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|---|---|
| CN110993652A true CN110993652A (en) | 2020-04-10 |
| CN110993652B CN110993652B (en) | 2023-05-19 |
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| CN111863907A (en) * | 2020-07-28 | 2020-10-30 | 福建华佳彩有限公司 | Display panel with fingerprint identification function |
| CN111969015A (en) * | 2020-08-19 | 2020-11-20 | 福建华佳彩有限公司 | Array substrate film layer structure and preparation method thereof |
| CN112420944A (en) * | 2020-11-11 | 2021-02-26 | 深圳市华星光电半导体显示技术有限公司 | Display panel, manufacturing method and display device |
| CN112687704A (en) * | 2020-12-25 | 2021-04-20 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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