CN110993563B

CN110993563B - OLED panel and manufacturing method

Info

Publication number: CN110993563B
Application number: CN201911158893.1A
Authority: CN
Inventors: 陈宇怀; 黄志杰; 苏智昱
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2023-05-19
Anticipated expiration: 2039-11-22
Also published as: CN110993563A

Abstract

A method for manufacturing OLED panel includes forming buffer layer on substrate, patterning active layer on buffer layer of thin film transistor region, patterning gate insulating layer on active layer, forming first conductive film layer and gate layer integrally, etching all gate metal in capacitor region, retaining gate metal and first conductive film layer in thin film transistor region, etching gate metal and conductive film layer in other regions according to patterning requirement; according to the invention, the transparent conductive film and the metal film layer are formed on the OLED panel, and the gray-scale photomask is combined, so that only the transparent conductive film is reserved in the capacitor area of the panel, the area of the metal film layer of the panel is further reduced, the light transmittance of the panel is increased, and the technical effect of clearer shooting of the under-screen lens module is achieved.

Description

OLED panel and manufacturing method

Technical Field

The invention relates to the field of novel comprehensive screen design, in particular to an OLED panel for increasing the light transmittance of a capacitor area.

Background

With the increasing development of display technology, various new technologies are continuously emerging, and the transparent display technology is receiving more and more attention due to the characteristic of a transparent display panel and the unique application thereof.

The core of the transparent display technology is a transparent display panel, which is a transparent panel capable of displaying images, unlike a double-sided display panel, which is a display device capable of simultaneously displaying images on both sides of the display panel. When the transparent display panel is closed, the panel looks like a piece of transparent glass, and when the transparent display panel works, a viewer can not only watch the content displayed on the panel, but also watch the object behind the panel through the panel.

The smart phone has been developed to the present, and the functions that can be realized are more and more, people have gradually learned the conventional mobile phone to perform activities that are indispensable in daily life such as social interaction, game playing and video watching, meanwhile, people also have more and more liked mobile phones with large visual angles and large screens, but the front camera occupies a plurality of screen positions, so that in order to achieve a higher screen ratio, the display effect is improved, and the concept of a comprehensive screen is generated. The comprehensive screen is 'comprehensive', so to speak, but for various technical reasons, the comprehensive screen cannot achieve true comprehensive, and the mechanical design of the automatic pop-up and push-up cover is enabled by visual trend, but the design scheme which has no doubt about aesthetic feeling and use efficiency is the final way of the mobile phone design. The under-screen camera is just a design scheme which has aesthetic and use efficiency, and is about to become trend.

Disclosure of Invention

Accordingly, there is a need to provide a new oled panel design that achieves improved light transmittance in the capacitive region and a corresponding design of the overall screen structure of the off-screen camera.

In order to achieve the above object, the present inventors provide a method for fabricating an OLED panel, comprising the steps of forming a buffer layer on a substrate, patterning an active layer on the buffer layer in a thin film transistor region, patterning a gate insulating layer on the active layer, integrally forming a first conductive film layer and a gate layer, etching all gate metals in a capacitor region, retaining the gate metals and the first conductive film layer in the thin film transistor region, and etching the gate metals and the conductive film layer in other regions according to patterning requirements; patterning the second insulating layer to expose the active layer of the thin film transistor region and cover the first conductive film layer of the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor region, and reserving a source drain electrode and the second conductive film layer in the thin film transistor region, wherein the source drain electrode is contacted with the active layer through the second conductive film layer. The manufacturing method also comprises the manufacturing steps of manufacturing the passivation layer, etching and exposing the drain metal, arranging the flat layer and the pixel definition layer, and etching the flat layer and the pixel definition layer on the capacitor region.

Further, etching all the gate metal in the capacitor region, retaining the gate metal and the first conductive film layer in the thin film transistor region, and etching the gate metal and the conductive film layer in other regions according to patterning requirements, specifically,

and coating photoresist on the grid layer, exposing by using a half-tone mask plate, setting the light transmittance of the capacitor region to be 50%, setting the light transmittance of the grid wiring part of the thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution to remove the photoresist of other parts, etching and transferring the photomask pattern to completely remove the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitor region by ashing, and etching again to remove the photoresist of the grid metal and the grid wiring part of the capacitor region.

Further, etching all electrode metals in the capacitor region, and reserving the source and drain electrodes and the second conductive film layer in the thin film transistor region, specifically,

coating photoresist on the electrode layer, exposing by using a half-tone mask plate, setting the light transmittance of the capacitor region to be 50%, setting the light transmittance of the source/drain wiring part of the thin film transistor to be 100%, setting the light transmittance of the other part to be 100%, developing by using a developing solution to remove the photoresist of the other part, etching and transferring the photomask pattern to completely remove the electrode metal and the second conductive film layer of the other part, removing the photoresist of the capacitor region by ashing, and etching again to remove the electrode metal and the photoresist of the electrode wiring part of the capacitor region.

OLED panel prepared by the method

According to the invention, the transparent conductive film and the metal film layer are formed on the OLED panel, and the gray-scale photomask is combined, so that only the transparent conductive film is reserved in the capacitor area of the panel, the area of the metal film layer of the panel is further reduced, the light transmittance of the panel is increased, and the technical effect of clearer shooting of the under-screen lens module is achieved.

Drawings

FIG. 1 is a schematic cross-sectional view of an OLED panel according to an embodiment;

FIG. 2 is a schematic diagram of the prior art and the present embodiment according to the present embodiment;

FIG. 3 is a schematic diagram of a pixel design according to an embodiment;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment;

FIG. 5 is a schematic diagram of a panel manufacturing process according to an embodiment;

FIG. 6 is an embodiment of a transparent capacitive plate according to an embodiment;

fig. 7 is a schematic structural diagram of an array substrate according to an embodiment;

fig. 8 is a schematic structural diagram of an array substrate according to an embodiment;

FIG. 9 is a flow chart of a panel manufacturing process according to an embodiment;

FIG. 10 is a basic block diagram of an array according to an embodiment;

FIG. 11 is a schematic view of a full screen according to an embodiment;

fig. 12 is a schematic view of an under-screen lens module according to an embodiment.

Detailed Description

In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.

Fig. 1 is a design diagram of a novel OLED panel of the present invention, wherein the OLED panel includes a thin film transistor region (hereinafter referred to as TFT region) and a capacitor region, as shown in the figure, the thin film transistor region (hereinafter referred to as TFT region) is located at the center of the cross-sectional view, that is, a portion for routing, in which the left side of the figure shows the structure of the capacitor region portion, and the right side is a light-transmitting region. From the figure we can see. The capacitive region includes a capacitive plate that can be used to stabilize the electrical operation of the TFT. In our technical scheme, the capacitor area does not include a metal layer, and the polar plates of the capacitor area are changed into transparent conductive film layers by not arranging a shading metal layer. The scheme of the invention also enables the source electrode and the drain electrode to be overlapped with the active layer through the transparent conductive film, thereby reducing ohmic resistance and further improving the electrical characteristics of the thin film transistor.

Fig. 2 further shows the comparison effect of the present invention with the conventional design, in which the capacitor metal layer in the conventional technical scheme is compatible with the source-drain metal and the gate metal on the TFT board in the manufacturing process, and the patterning is simple and convenient, but in the case that the capacitor area occupies a large position of the pixel, it is not enough to improve the transparency of the panel only by the transmission window. Fig. 3 shows some embodiments of the pixel design, where the capacitive area is designed to be transparent, the transparency of the entire panel will be greatly improved.

Fig. 4 shows an embodiment of the present invention, which shows a specific structure of the array substrate in the panel. The film structure of the TFT region is based on a transparent substrate, and then a gate scan line GE, a gate insulating layer GI, an active layer IGZO, an etch stopper ES, a source drain signal line SD, and a passivation layer PV. Specific design we can see from the figure that the capacitor plates include a gate insulating layer or an etch stop layer between them. The capacitor region comprises a substrate, a capacitor lower polar plate, a gate insulating layer, an etching barrier layer, a capacitor upper polar plate, a passivation layer and a flat layer which are arranged from bottom to top. And a conductive film layer is arranged between the source electrode and the drain electrode and between the grid scanning line and the substrate in the thin film transistor area. A planarization layer is provided in addition to the passivation layer. The thin film transistor region comprises a substrate, a first conductive film layer, a gate insulating layer, an active layer, a second conductive film layer, an etching barrier layer, a source drain layer, a passivation layer and a flat layer which are arranged from bottom to top. Through the panel structure designed by the scheme, the transmissivity of the capacitor can be increased, and meanwhile, the electrical property of the active layer is improved.

In order to manufacture the panel of the transparent capacitor, the invention also provides a manufacturing method of the OLED panel, which comprises the following steps of preparing a substrate, sequentially forming a first conductive film layer and a grid layer on the substrate, etching all grid metals in a capacitor area, reserving the grid metals and the first conductive film layer in a thin film transistor area, and etching the grid metals and the conductive film layer in other areas according to patterning requirements;

and then, manufacturing a grid insulating layer, manufacturing an active layer in a thin film transistor area, manufacturing an etching barrier layer, leaving a via hole, sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in a capacitor area, and reserving a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is contacted with the active layer through the second conductive film layer. Further, the method further comprises the step of manufacturing a flat layer and a pixel definition layer.

Specific implementation details we can look at from fig. 5. As shown in fig. 5, the preparation of the OLED panel in the scheme of the present invention includes the following steps:

01. GE: forming a first metal layer on a substrate to manufacture a grid driving circuit and a first electrode plate of a capacitor region;

02. GI: manufacturing a gate insulating layer on the gate;

03. SE: manufacturing an active layer IGZO or other metal oxide materials on the grid electrode;

04. ES: manufacturing an etching barrier layer on the active layer to protect the channel of the active layer and etching a via hole to connect the active layer and the source/drain electrode;

05. SD: manufacturing a source electrode/drain electrode circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;

06. PV: manufacturing a passivation layer on the source electrode/drain electrode, etching a through hole to expose the surface of the drain electrode, and etching a through hole at the transmission window to expose the surface of the substrate so as to increase the transparency of the panel;

07. OP: manufacturing an organic flat layer on the passivation layer, developing the PV via hole to form an OP via hole to expose the drain electrode, and exposing the surface of the substrate at the projection window;

08. AN: manufacturing and patterning transparent anodes such as ITO (indium tin oxide) on the flat layer, wherein AN anode AN is connected with a drain electrode through AN OP/IP (operational frequency/internet protocol) via hole;

09. PD: manufacturing an organic pixel definition layer, and developing an RGB pattern opening and a transmission window through hole;

10. PS: patterning a PS layer of the supporting substrate and the packaging cover plate;

11. OLED light emitting layer: evaporating an organic light-emitting layer on the PD via hole and the anode;

12. metal cathode: evaporating transparent metal cathode.

An embodiment of fabricating a transparent capacitive plate on a substrate is shown in the example shown in fig. 6, comprising the steps of,

step1. Continuously forming a transparent conductive layer and a metal film layer, wherein the transparent conductive film can be preferably ITO, the material is not particularly limited, and the metal film layer can be one or more of metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium and the like, and alloys;

step2, exposing by using a half-tone mask, wherein the light transmittance of the capacitor area is 50%, the transmittance of the grid wiring area is 0%, and the light transmittance of other areas is 100%;

step3, developing the photoresist layer by using a developing solution after exposure, completely removing the photoresist in a 100% transmittance region of the photomask, wherein the photoresist in a 50% transmittance region and a 0% transmittance region is still reserved, and the photoresist in the 50% transmittance region is thinned compared with the photoresist in the 0% transmittance region;

step4, primarily transferring the mask pattern by etching the film layer, wherein the metal and ITO etching can be performed by one-time etching or secondary etching according to the film material;

step5, removing the photoresist in the area with 50% light transmittance through ashing treatment;

step6, etching again after ashing treatment, removing metal above the 50% light transmittance area by etching time control or selectivity of etching liquid, retaining ITO, and removing residual photoresist to complete pattern transfer.

Thus, referring to fig. 6, all gate metal is etched in the capacitor region, the gate metal and the first conductive film layer remain in the thin film transistor region, and the gate metal and the conductive film layer are etched in other regions according to patterning requirements, specifically,

On the other hand, etching all the electrode metals in the capacitor region and reserving the source and drain electrodes and the second conductive film layer in the thin film transistor region, which is basically similar, comprises the following steps:

In other preferred embodiments, when evaporating the metal cathode, the mask plate is adopted to evaporate, so that the cathode metal film layer structure is not reserved in the transmission window area, and the transmittance is further increased.

In the embodiment shown in fig. 7, another structural scheme of the array substrate is shown, and the film layer structure in the TFT thin film transistor area is sequentially formed by a gate scanning line GE, a gate insulating layer GI (first insulating layer), an active layer SE, a source drain signal line SD, and a passivation layer PV on the transparent substrate. The transparent capacitor region also includes first and second conductive film layers sandwiching the first insulating layer therebetween in this configuration.

In the embodiment shown in fig. 8, another structure of the array substrate is shown, and the TFT film structure of the present invention sequentially comprises, from bottom to top:

bf: buffer layer

Se: active layer (Metal oxide)

Gi: grid insulating layer (first insulating layer)

Ge: metal grid (first metal layer)

Il: second insulating layer

Sd: metal source drain electrode (second metal layer)

Pv: passivation layer (third insulating layer).

Fig. 9 illustrates a method of preparation corresponding to the configuration of fig. 8, comprising the steps of:

01. BF: forming a buffer layer on a glass substrate, wherein the optional materials are organic materials, siOx, siNx, titanium oxide, aluminum oxide and the like;

02. SE: forming a film on the buffer layer and patterning an active layer IGZO or other metal oxide and other materials;

03. GI: forming a gate insulating layer on the active layer and patterning the gate insulating layer, wherein SiOx, siNx, titanium oxide, aluminum oxide and the like are selected;

04. GE: forming a first metal layer on the gate insulating layer to manufacture a gate driving circuit and a first electrode plate of a capacitor region, wherein one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium and the like and alloys are adopted;

05. IL: forming a second insulating layer on the gate metal layer and patterning the second insulating layer, wherein SiOx, siNx, titanium oxide, aluminum oxide and the like are selected;

06. SD: manufacturing a source electrode/drain electrode circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;

07. PV: a passivation layer is formed and patterned over the source/drain electrodes exposing the drain metal surface and the glass substrate surface, optionally of organic material, siOx, siNx, titania, alumina, etc.

Through the scheme, the OLED panel structure with the transparent capacitor area can be manufactured.

Therefore, the scheme further comprises the steps of forming a buffer layer on the substrate, patterning an active layer on the buffer layer of the thin film transistor region, patterning a gate insulating layer on the active layer, integrally forming a first conductive film layer and a gate layer, etching all gate metals in the capacitor region, reserving the gate metals and the first conductive film layer in the thin film transistor region, and etching the gate metals and the conductive film layer in other regions according to patterning requirements; patterning the second insulating layer to expose the active layer of the thin film transistor region and cover the first conductive film layer of the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor region, and reserving a source drain electrode and the second conductive film layer in the thin film transistor region, wherein the source drain electrode is contacted with the active layer through the second conductive film layer.

Specifically, the method further comprises the steps of manufacturing a passivation layer, etching and exposing the drain metal, and arranging a flat layer and a pixel definition layer.

According to the method, the transparent conductive film and the metal film layer are formed, and the gray scale photomask is combined, so that only the transparent conductive film is reserved in the pixel capacitor region, the area of the metal film layer of the panel is further reduced, and the light transmittance of the panel is increased.

In other embodiments, as shown in fig. 10, the technical scheme of the present invention may be modified by reducing the technical scheme that the original transmission window and the transparent capacitor are separately disposed, and removing the planarization layer and the pixel definition layer on the capacitor region by patterning or etching. Specifically, the method includes the steps of fabricating a passivation layer, etching the passivation layer to expose drain metal, and disposing a planarization layer and a pixel defining layer, wherein the pixel defining layer is in contact with the drain metal, and an organic light emitting layer is formed on the pixel defining layer in the thin film transistor region. The flat layer and the pixel definition layer in the capacitor region are etched, and as can be seen from the figure, only the first conductive film layer and the second conductive film layer of the transparent capacitor are left in the capacitor region, and an etching barrier layer and a gate insulating layer are arranged between the first conductive film layer and the second conductive film layer; there is also a passivation layer designed on the transparent capacitor. The planarization layer and the pixel defining layer thereon are etched. Forming a V-shaped opening. Through such design, can make capacitive region and opening region obtain integrating in the space, when guaranteeing the panel light transmissivity, also saved the space demand better, improved the pixel ratio of panel.

In the embodiment of fig. 11, an application example of a high-transparency panel is shown, in a full-face screen, the OLED high-transparency panel can be used, so that a plurality of anti-reflection areas can be formed in the full-face screen, the anti-reflection areas can be in various embodiments of a circle, a square at a bang position and the like, and the rest parts are normally displayed, so that a common OLED panel in the prior art can be adopted. The high-transparency OLED panel of the scheme is used in the anti-reflection area, the camera shooting module can be arranged below the anti-reflection area and used for acquiring image data, the specific setting of the under-screen camera shooting structure is shown in fig. 12, the transparent capacitance area is far greater than the opaque area in practical situation, the anti-reflection area can ensure normal light intake, when the anti-reflection area is used, the luminous signals of the panel in the anti-reflection area can be canceled through the preset program setting, and the influence of pixel luminescence on the acquisition signals of the camera can be reduced or avoided. The technical effect that the under-screen camera collects optical input signals is achieved.

It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims

1. The manufacturing method of the OLED panel is characterized by comprising the following steps,

forming a buffer layer on a substrate, patterning an active layer on the buffer layer of a thin film transistor region, patterning a gate insulating layer on the active layer, integrally forming a first conductive film layer and a gate layer, etching all gate metals in a capacitor region, reserving the gate metals and the first conductive film layer in the thin film transistor region, and etching the gate metals and the conductive film layer in other regions according to patterning requirements; patterning the second insulating layer to expose the active layer of the thin film transistor region and cover the first conductive film layer of the capacitor region; sequentially forming a second conductive film layer and an electrode layer,

etching all electrode metals in the capacitor region, reserving a source drain electrode and a second conductive film layer in the thin film transistor region, specifically, coating a photoresist on the electrode layer, exposing by using a half-tone mask plate, setting the light transmittance of the capacitor region to be 50%, the light transmittance of the source drain electrode wiring part of the thin film transistor to be 100%, and the light transmittance of other parts to be 100%, developing by a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern to completely remove the electrode metals and the second conductive film layer of other parts, removing the photoresist of the capacitor region by ashing, etching again to remove the electrode metals and the photoresist of the electrode wiring part of the capacitor region, contacting the source drain electrode with the active layer through the second conductive film layer,

the method comprises the steps of manufacturing a passivation layer, etching and exposing drain metal, and arranging a flat layer and a pixel definition layer, wherein the thin film transistor region further comprises an anode, a cathode and an organic light-emitting layer, the anode is in contact with the drain, the organic light-emitting layer is arranged between the anode and the cathode, the flat layer and the pixel definition layer on the capacitor region are etched to form a V-shaped opening, and the passivation layer of the capacitor region is exposed.

2. The method of claim 1, further comprising etching all gate metal in the capacitor region, retaining the gate metal and the first conductive film layer in the thin film transistor region, and etching the gate metal and the conductive film layer in other regions according to patterning requirements,

3. An OLED panel produced by the production method according to any one of claims 1-2.