CN110993590A - Packaging structure for reducing size of 3D NAND product and manufacturing method thereof - Google Patents
Packaging structure for reducing size of 3D NAND product and manufacturing method thereof Download PDFInfo
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- CN110993590A CN110993590A CN201911316708.7A CN201911316708A CN110993590A CN 110993590 A CN110993590 A CN 110993590A CN 201911316708 A CN201911316708 A CN 201911316708A CN 110993590 A CN110993590 A CN 110993590A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A packaging structure for reducing the size of a 3D NAND product and a manufacturing method thereof are disclosed, the packaging structure comprises a substrate, a product unit connected with the substrate is arranged on the upper surface of the substrate, the upper surface of the substrate and the product unit are packaged by a plastic package material, and a plurality of solder balls are arranged on the lower surface of the substrate; the product unit comprises a first 3D NAND memory chip set, a second 3D NAND memory chip set, a current control device and a read-write control chip which are connected with the substrate respectively; the first 3D NAND storage chip set and the second 3D NAND storage chip set are formed by stacking a plurality of layers of 3D NAND storage chips in a step shape, and the current control device and the read-write control chip are arranged in a space formed by the first 3D NAND storage chip set and the second 3D NAND storage chip set. The invention can save space, lead the NAND memory chip to be capable of stacking more layers and increase the product capacity.
Description
Technical Field
The invention belongs to the field of chip packaging, and relates to a packaging structure for reducing the size of a 3D NAND product and a manufacturing method thereof.
Background
eMMC/eMCP: the eMMC (embedded Multi Media card) is the standard specification of an embedded memory which is established by the MMC association and mainly aims at products such as mobile phones or tablet computers; the eMCP (Embedded Multi-Chip Package) refers to an Embedded Multi-layer Package Chip, and since a NAND product requires a large enough product capacity and a large number of stacked layers, the limited space cannot meet the requirement of a Multi-stack volume due to the limitation of the size and space of a single product.
Disclosure of Invention
The invention aims to provide a packaging structure for reducing the size of a 3D NAND product and a manufacturing method thereof aiming at the problem that the chip packaging structure in the prior art cannot provide enough space for stacking multiple layers of chips, so that the space requirement for stacking multiple layers of chips is met.
In order to achieve the purpose, the invention has the following technical scheme:
a packaging structure for reducing the size of a 3D NAND product comprises a substrate, wherein a plurality of product units connected with the substrate are arranged on the upper surface of the substrate, the upper surface of the substrate and the product units are packaged through a plastic package material, and a plurality of solder balls are arranged on the lower surface of the substrate; the product unit comprises a first 3D NAND memory chip set, a second 3D NAND memory chip set, a current control device and a read-write control chip which are connected with the substrate respectively; the first 3D NAND storage chip group and the second 3D NAND storage chip group are formed by stacking a plurality of layers of 3D NAND storage chips in a step shape, the 3D NAND storage chips in the groups are connected with each other through bonding wires, and the first 3D NAND storage chip group and the second 3D NAND storage chip group are stacked oppositely from bottom to top; the current control device and the read-write control chip are arranged in a space formed by the first 3D NAND memory chip set and the second 3D NAND memory chip set.
As a preferred embodiment of the packaging structure for reducing the product size, the first 3D NAND memory chip set and the second 3D NAND memory chip set bond the multiple layers of 3D NAND memory chips after the chip mounting by an adhesive film and bake and cure the multiple layers of 3D NAND memory chips; the bonding wire is a gold wire with the diameter of 0.8mil and is connected in a pressure welding mode.
As a preferred embodiment of the package structure for reducing the size of the product according to the present invention, the current control device includes a capacitor, a resistor, and an inductor, and the current magnitude during the operation is controlled by the capacitor, the resistor, and the inductor.
As a preferred embodiment of the package structure for reducing the product size of the present invention, the first 3D NAND memory chip set, the second 3D NAND memory chip set, the current control device, and the read-write control chip form a closed circuit through the substrate, and the read-write of the 3D NAND memory chip is controlled by the read-write control chip.
As a preferred embodiment of the package structure for reducing the product size of the present invention, DRAM chips are stacked on the first 3D NAND memory chip set and the second 3D NAND memory chip set. The packaging structure is applied to eMMC products, and can be also applied to eMMC products, the eMCP is formed by overlapping DRAM chips at the position where NAND memory chips are overlapped, the positions of a current control device and a read-write control chip are unchanged, and the overlapping structure of the products is not influenced.
The invention also provides a manufacturing method of the packaging structure for reducing the size of the 3D NAND product, which comprises the following steps:
1) fixing a current control device and a read-write control chip on the upper surface of the substrate, and electrically connecting the set current control device and the read-write control chip with the upper surface of the substrate;
2) the current control device and the read-write control chip are arranged in a space formed by the first 3D NAND storage chip set and the second 3D NAND storage chip set respectively, the first 3D NAND storage chip set and the second 3D NAND storage chip set are formed by stacking a plurality of layers of 3D NAND storage chips in a step shape, the first 3D NAND storage chip set and the second 3D NAND storage chip set are stacked oppositely from bottom to top, and the stacked plurality of layers of 3D NAND storage chips are bonded and fixed, so that the current control device and the read-write control chip are arranged in the space formed by the first 3D NAND storage chip set and the second 3D NAND storage chip set;
3) connecting the 3D NAND memory chips in each group with each other through bonding wires, and simultaneously electrically connecting the head and tail two 3D NAND memory chips with the upper surface of the substrate through the bonding wires;
4) packaging the upper surface of the substrate, the first 3D NAND memory chip set, the second 3D NAND memory chip set, the bonding wire, the current control device and the read-write control chip through plastic packaging materials;
5) arranging a plurality of solder balls on the lower surface of the substrate;
6) and manufacturing a plurality of product units on the substrate at the same time, and cutting to obtain a 3D NAND product.
Compared with the prior art, the packaging structure for reducing the size of the 3D NAND product has the following beneficial effects: the three-dimensional NAND flash memory comprises a first 3D NAND memory chip set and a second 3D NAND memory chip set which are formed by stacking a plurality of layers of 3D NAND memory chips in a stepped manner, wherein the first 3D NAND memory chip set and the second 3D NAND memory chip set are stacked oppositely from bottom to top, a triangular suspended part is formed between the two NAND memory chip sets, a current control device and a read-write control chip are arranged in a space formed by the first 3D NAND memory chip set and the second 3D NAND memory chip set, and the utilization rate of a product space is maximized under the condition that the requirement on the size specification of a product is smaller and smaller.
Compared with the prior art, the manufacturing method of the packaging structure is simple and convenient in operation process, the current control device and the read-write control chip are arranged in the space formed by the first 3D NAND memory chip group and the second 3D NAND memory chip group, the space can be effectively saved, the NAND memory chips can be stacked with more layers, and the capacity of products is increased.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of the arrangement of the upper surface of the substrate of the package structure of the present invention;
FIG. 2 is a general schematic diagram of a package structure according to the present invention;
FIG. 3 is a schematic diagram of steps of a method for manufacturing a package structure according to the present invention, wherein the lower number indicates the sequence of the steps.
In the drawings: 1-a substrate; 2-a first 3D NAND memory chipset; 3-a second 3D NAND memory chip set; 4-a bonding wire; 5-a current control device; 6-read-write control chip; 7-solder ball; 8-plastic packaging material.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention.
Based on the embodiments of the present invention, those skilled in the art can make several simple modifications and decorations without creative efforts, and all other embodiments obtained belong to the protection scope of the present invention.
Reference in the present specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example may be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by one skilled in the art that the embodiments described in the present invention can be combined with other embodiments.
Referring to fig. 1-2, the embodiment of the packaging structure for reducing the size of the 3D NAND product of the invention includes a substrate 1, a product unit connected to the substrate 1 is disposed on the upper surface of the substrate 1, the upper surface of the substrate 1 and the product unit are packaged by a molding compound 8, and a plurality of solder balls 7 are disposed on the lower surface of the substrate 1. The product unit comprises a first 3D NAND memory chip set 2, a second 3D NAND memory chip set 3, a current control device 5 and a read-write control chip 6 which are respectively connected with a substrate 1.
The first 3D NAND memory chip group 2 and the second 3D NAND memory chip group 3 are formed by stacking a plurality of layers of 3D NAND memory chips in a ladder shape, the first 3D NAND memory chip group 2 and the second 3D NAND memory chip group 3 are used for bonding the plurality of layers of 3D NAND memory chips after the chip mounting process is completed through adhesive films and baking and curing, and the bonding wire 4 is a gold wire with the wire diameter of 0.8mil and is connected in a pressure welding mode. The 3D NAND memory chips in the group are connected to each other by bonding wires 4, and the head and tail two 3D NAND memory chips are electrically connected to the upper surface of the substrate 1 by the bonding wires 4.
In the embodiment of the invention, the first 3D NAND memory chip set 2 and the second 3D NAND memory chip set 3 are oppositely stacked from bottom to top, a triangular suspended part is formed between the two NAND memory chip sets, and the current control device 5 and the read-write control chip 6 are arranged in a space formed by the first 3D NAND memory chip set 2 and the second 3D NAND memory chip set 3. The current control device 5 comprises a capacitor, a resistor and an inductor, and the first 3D NAND memory chip set 2, the second 3D NAND memory chip set 3, the current control device 5 and the read-write control chip 6 form a closed circuit through the substrate 1. The current in the working process is controlled through the capacitor, the resistor and the inductor, and the read-write of the 3D NAND memory chip is controlled through the read-write control chip.
The foregoing embodiment has been described with an eMMC product as an example, and the package structure of the present invention may not only be applied to an eMMC product, but also be applied to an eMMP product. Therefore, DRAM chips may also be superimposed on the first 3D NAND memory chip set 2 and the second 3D NAND memory chip set 3.
Referring to fig. 3, the package structure for reducing the size of the 3D NAND product of the present invention can be implemented as follows:
1) the current control device 5 and the read-write control chip 6 are fixed on the upper surface of the substrate 1, the mounting sequence of the current control device 5 and the read-write control chip 6 can be adjusted according to the actual situation, and the figure shows the situation that the current control device 5 is mounted firstly. And electrically connecting the set current control device 5 and the read-write control chip 6 with the upper surface of the substrate 1.
2) The current control device 5 and the read-write control chip 6 are respectively provided with a first 3D NAND storage chip group 2 and a second 3D NAND storage chip group 3 on two sides respectively, the first 3D NAND storage chip group 2 and the second 3D NAND storage chip group 3 are formed by stacking a plurality of layers of 3D NAND storage chips in a step shape, the first 3D NAND storage chip group 2 and the second 3D NAND storage chip group 3 are stacked oppositely from bottom to top, and the stacked plurality of layers of 3D NAND storage chips are bonded and fixed, so that the current control device 5 and the read-write control chip 6 which are installed in the step 1) are arranged in a triangular space formed by the first 3D NAND storage chip group 2 and the second 3D NAND storage chip group 3.
3) The 3D NAND memory chips in each group are connected with each other through bonding wires 4, and the head and tail two 3D NAND memory chips are electrically connected with the upper surface of the substrate 1 through the bonding wires 4; to this end, the first 3D NAND memory chip set 2, the second 3D NAND memory chip set 3, the current control device 5, and the read-write control chip 6 form a closed circuit through the substrate 1, and the read-write of the 3D NAND memory chip can be controlled by the read-write control chip 6.
4) The upper surface of the substrate 1, the first 3D NAND memory chip group 2, the second 3D NAND memory chip group 3, the bonding wire 4, the current control device 5 and the read-write control chip 6 are packaged through a plastic package material 8, and contents are printed on the surfaces.
5) A plurality of solder balls 7 are disposed on the lower surface of the substrate 1.
6) A plurality of product units can be simultaneously manufactured on the substrate 1, and then a 3D NAND product is obtained by cutting.
In the manufacturing method of the present invention, the following aspects need to be noted in the implementation process:
1. when the NAND memory chips are stacked in a staggered mode, the number of layers is large, the NAND memory chips need to be thinned, the thickness of the chips is small, chip cracking is easily caused in the process, and the requirement on the capacity of the process is high.
2. The requirement of the size of a finished product chip of a 3D NAND product is met, the lower suspension space of the stacked NAND memory chips is small, and the risk of not being placed is possibly caused when the current control device 5 and the read-write control chip 6 are installed.
3. The triangular suspended part formed by the first 3D NAND storage chip group 2 and the second 3D NAND storage chip group 3 is small in space, and hollow layering risks can be caused if plastic packaging materials cannot be completely filled in the plastic packaging process.
The packaging structure and the manufacturing method thereof have the outstanding characteristics that the manufacturing method is simple and convenient in operation process, the current control device and the read-write control chip are arranged in the space formed by the first 3D NAND memory chip group and the second 3D NAND memory chip group, the space can be effectively saved, the NAND memory chips can be stacked with more layers, and the capacity of products is increased. Under the condition that the requirements of the product size specification are smaller and smaller, the invention realizes the maximum utilization rate of the product space.
While the invention has been described above with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention, and those modifications and variations are within the scope of the claims of the invention and their equivalents.
Claims (6)
1. A packaging structure for reducing the size of a 3D NAND product is characterized in that: the packaging structure comprises a substrate (1), wherein a plurality of product units connected with the substrate are arranged on the upper surface of the substrate (1), the upper surface of the substrate (1) and the product units are packaged through a plastic packaging material (8), and a plurality of solder balls (7) are arranged on the lower surface of the substrate (1); the product unit comprises a first 3D NAND memory chip set (2), a second 3D NAND memory chip set (3), a current control device (5) and a read-write control chip (6), wherein the first 3D NAND memory chip set, the second 3D NAND memory chip set, the current control device and the read-write control chip are respectively connected with a substrate (1); the first 3D NAND memory chip set (2) and the second 3D NAND memory chip set (3) are formed by stacking a plurality of layers of 3D NAND memory chips in a step shape, the 3D NAND memory chips in the sets are connected with each other through bonding wires (4), and the first 3D NAND memory chip set (2) and the second 3D NAND memory chip set (3) are stacked from bottom to top in opposite directions; the current control device (5) and the read-write control chip (6) are arranged in a space formed by the first 3D NAND memory chip group (2) and the second 3D NAND memory chip group (3).
2. The package structure for reducing the size of a 3D NAND product in accordance with claim 1, wherein: the first 3D NAND memory chip group (2) and the second 3D NAND memory chip group (3) are used for bonding the multiple layers of 3D NAND memory chips after being pasted with the chips through adhesive films and baking and curing the chips; the bonding wire (4) is a gold wire with the diameter of 0.8mil and is connected in a pressure welding mode.
3. The package structure for reducing the size of a 3D NAND product in accordance with claim 1, wherein: the current control device (5) comprises a capacitor, a resistor and an inductor, and the current in the working process is controlled through the capacitor, the resistor and the inductor.
4. The package structure for reducing the size of a 3D NAND product in accordance with claim 1, wherein: the first 3D NAND storage chip group (2), the second 3D NAND storage chip group (3), the current control device (5) and the read-write control chip (6) form a closed circuit through the substrate (1), and the read-write control chip (6) controls the read-write of the 3D NAND storage chip.
5. The package structure for reducing the size of a 3D NAND product in accordance with claim 1, wherein: DRAM chips are superposed on the first 3D NAND memory chip group (2) and the second 3D NAND memory chip group (3).
6. A manufacturing method of a packaging structure for reducing the size of a 3D NAND product is characterized in that:
1) fixing a current control device (5) and a read-write control chip (6) on the upper surface of the substrate (1), and electrically connecting the set current control device (5) and the read-write control chip (6) with the upper surface of the substrate (1);
2) a first 3D NAND storage chip group (2) and a second 3D NAND storage chip group (3) are respectively arranged on two sides of a current control device (5) and a read-write control chip (6), the first 3D NAND storage chip group (2) and the second 3D NAND storage chip group (3) are formed by stacking a plurality of layers of 3D NAND storage chips in a step shape, the first 3D NAND storage chip group (2) and the second 3D NAND storage chip group (3) are oppositely stacked from bottom to top, and the stacked plurality of layers of 3D NAND storage chips are bonded and fixed, so that the current control device (5) and the read-write control chip (6) are arranged in a space formed by the first 3D NAND storage chip group (2) and the second 3D NAND storage chip group (3);
3) the 3D NAND memory chips in each group are connected with each other through bonding wires (4), and the head and the tail of the two 3D NAND memory chips are electrically connected with the upper surface of the substrate (1) through the bonding wires (4);
4) the upper surface of the substrate (1), the first 3D NAND memory chip set (2), the second 3D NAND memory chip set (3), the bonding wire (4), the current control device (5) and the read-write control chip (6) are packaged through a plastic package material (8);
5) arranging a plurality of solder balls (7) on the lower surface of the substrate (1);
6) a plurality of product units are manufactured on the substrate (1) at the same time, and a 3D NAND product is obtained through cutting.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911316708.7A CN110993590A (en) | 2019-12-19 | 2019-12-19 | Packaging structure for reducing size of 3D NAND product and manufacturing method thereof |
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| CN201911316708.7A CN110993590A (en) | 2019-12-19 | 2019-12-19 | Packaging structure for reducing size of 3D NAND product and manufacturing method thereof |
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| CN111639739A (en) * | 2020-06-05 | 2020-09-08 | 华天科技(南京)有限公司 | Storage device with eMMC specification and preparation method thereof |
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| CN117133727A (en) * | 2023-08-29 | 2023-11-28 | 江苏柒捌玖电子科技有限公司 | Three-dimensional stacked packaging structure and packaging method thereof |
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