CN110990317A - In-place signal processing method and device during server debugging - Google Patents
In-place signal processing method and device during server debugging Download PDFInfo
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- CN110990317A CN110990317A CN201911053217.8A CN201911053217A CN110990317A CN 110990317 A CN110990317 A CN 110990317A CN 201911053217 A CN201911053217 A CN 201911053217A CN 110990317 A CN110990317 A CN 110990317A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention provides an in-place signal processing method during server debugging, which comprises the following steps: setting a switching device, and connecting an in-place signal end of the server equipment to the ground through the switching device; in response to debugging the server, closing the switching device to pull the in-place signal low, simulating the server device being in place. According to the invention, the dial switch is added, so that the on-site signals of the server CPU and the equipment are connected to the ground through the dial switch, thereby meeting the power-on time sequence condition of the CPLD, avoiding the need of installing the CPU or inserting the equipment, saving a large amount of time and avoiding resource waste.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to an in-place signal processing method and apparatus during server debugging.
Background
In the process of testing the return board of the server, the power supply of the server and the power-on time sequence of the equipment need to be debugged. The power-on and power-off time sequence control in the server is realized by a CPLD. However, the CPU or the device is a necessary condition for powering on the server power supply or the device in place, and if it is desired to verify the power supply of the server power supply or the power-on timing of the device, the CPU or the device needs to be installed or plugged in first, and a corresponding debugging environment is built.
As shown in fig. 1 and 2, the present method of connecting signals in place is shown. In fig. 1, Present1 in Slot is grounded, Present2 is connected to CPLD, 3V3_ STBY, 9555 respectively, and Present1 and Present2 in Device are connected together. When the Device inserts the Slot, Present2 is pulled low, telling the CPLD and BMC Device that they are in place. Similarly, in fig. 2, the Present in the Slot is respectively connected to the CPLD, 3V3_ STBY, 9555, and the Present in the Device is grounded. When the Device inserts the Slot, the Present in the Slot is pulled low, informing the CPLD and BMC Device that they are in place. The presence signal is located in each connector slot and can only be pulled low when a device is inserted into the corresponding slot. Verifying that different devices need to build different server connection topologies wastes a lot of time and resources.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide an in-place signal processing method and apparatus for debugging a server, so as to simulate the in-place of a device, thereby satisfying the power-on timing condition of a CPLD without installing a CPU or inserting a device.
Based on the above purpose, an aspect of the embodiments of the present invention provides an in-place signal processing method during server debugging, including the following steps:
setting a switching device, and connecting an in-place signal end of the server equipment to the ground through the switching device;
in response to debugging the server, closing the switching device to pull the in-place signal low, simulating the server device being in place.
In some embodiments, debugging the server includes implementing, by the CPLD, debugging power-up and power-down timing of the server device.
In some embodiments, the providing a switching device through which the on-bit signal terminal of the server device is connected to ground comprises:
one end of the switch device is connected with an on-position signal end of the equipment slot, and the other end of the switch device is grounded, wherein the on-position signal end is connected to a power supply through a pull-up resistor.
In some embodiments, the switching device is a dip switch.
In some embodiments, the switching device is a flip cap.
Another aspect of the embodiments of the present invention provides an in-place signal processing apparatus during server debugging, including: the device comprises a CPLD, a device slot and a switch device, wherein the CPLD is connected to an on-site signal end of the device slot; one end of the switch device is connected with the in-place signal end of the equipment slot, the other end of the switch device is grounded, and the switch device is closed to pull down the in-place signal when the server is debugged, so that the CPLD is simulated that the server equipment is in place.
In some embodiments, the in-place signal terminal of the device socket is connected to a power supply through a pull-up resistor.
In some embodiments, when debugging the power-up and power-down timing of the server device is achieved through the CPLD, the switching device is closed to pull down the presence signal, simulating that the server device is in place.
In some embodiments, the switching device is a dip switch.
In some embodiments, the switching device is a flip cap.
The invention has the following beneficial technical effects: according to the method and the device for processing the in-place signals during server debugging, provided by the embodiment of the invention, the dial switch is additionally arranged, and the in-place signals of the CPU and the equipment of the server are connected to the ground through the dial switch, so that the power-on time sequence condition of the CPLD is met, the CPU does not need to be installed or the equipment does not need to be inserted to build different server connection topologies, a large amount of time is saved, and resource waste is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art in-place signal connection;
FIG. 2 is another prior art in-place signal connection schematic;
FIG. 3 is a flow chart of an in-place signal processing method during server debugging according to the present invention;
FIG. 4 is a schematic diagram of server in-place signal processing according to the present invention;
FIG. 5 is a schematic diagram of device power-up by a CPLD in accordance with the present invention;
FIG. 6 is a schematic diagram of an in-place signal connection modified from FIG. 1 in accordance with the present invention;
fig. 7 is a schematic diagram of an improved in-place signal connection of fig. 2 according to the present invention.
Detailed Description
Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present invention may be desired for certain specific applications or implementations.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
Based on the above purpose, an embodiment of the present invention provides an in-place signal processing method during server debugging, as shown in fig. 3, including the following steps:
step S301: setting a switching device, and connecting an in-place signal end of the server equipment to the ground through the switching device;
step S302: in response to debugging the server, closing the switching device to pull the in-place signal low, simulating the server device being in place.
In some embodiments, debugging the server includes enabling, by the CPLD, debugging power-up and power-down timing of the server device. In the process of testing the return board of the server, the power supply of the server and the power-on time sequence of the equipment need to be debugged, and the power-on and power-off time sequence control in the server is realized through a CPLD.
In some embodiments, the providing a switching device through which the on-bit signal terminal of the server device is connected to ground includes: one end of the switch device is connected with an on-position signal end of the equipment slot, and the other end of the switch device is grounded, wherein the on-position signal end is connected to a power supply through a pull-up resistor. In some embodiments, the switching device is a dip switch. As shown in fig. 4, by adding a dial switch, the server CPU and other devices are connected to the ground through the dial switch. When the power supply of the power supply and the equipment are debugged, the corresponding dial switch is dialed to be connected to the ground, the on-site signal is pulled down, and the equipment is simulated to be on site.
As shown in fig. 5, when the power-on sequence of the server device is controlled by the CPLD, after the CPLD receives the motherboard 3V3_ power _ on signal and the PRESENT bit signal, the CPLD sends a MAIN _ PWREN signal to control the device to power on. When the device is not in place, the power-on condition cannot be met, and the CPLD does not send the MAIN _ PWREN signal. By using the method of the invention, the CPLD power-on time sequence condition is satisfied, and a CPU or an inserted device is not required to be installed, thereby saving a large amount of time and avoiding resource waste.
In some embodiments, the same function may be achieved by pulling the in-place signal low through a jumper cap or other suitable device of the present invention.
Where technically feasible, the technical features listed above for the different embodiments may be combined with each other or changed, added, omitted, etc. to form further embodiments within the scope of the invention.
It can be seen from the foregoing embodiments that, in the in-place signal processing method for server debugging according to the embodiments of the present invention, the dial switch is added, and the in-place signals of the server CPU and the device are connected to the ground through the dial switch, so that the power-on time sequence condition of the CPLD is satisfied, and the CPU does not need to be installed or the device does not need to be inserted to build different server connection topologies, thereby saving a lot of time and avoiding resource waste.
In view of the above object, another aspect of the embodiments of the present invention provides an in-place signal processing apparatus during server debugging, including: the device comprises a CPLD, a device slot and a switch device, wherein the CPLD is connected to an on-site signal end of the device slot; one end of the switch device is connected with the in-place signal end of the equipment slot, the other end of the switch device is grounded, and the switch device is closed to pull down the in-place signal when the server is debugged, so that the CPLD is simulated that the server equipment is in place.
In some embodiments, the in-place signal terminal of the device socket is connected to a power supply through a pull-up resistor.
In some embodiments, when debugging the power-up and power-down timing of the server device is realized through the CPLD, the switching device is closed to pull down the presence signal, simulating that the server device is in place.
In some embodiments, the switching device is a dip switch.
In some embodiments, the switching device is a flip cap.
In one embodiment according to the Present invention, as shown in fig. 6, the Present1 in the Slot is grounded, the Present2 is connected to the CPLD, 3V3_ STBY, 9555 respectively, and the Present1 and the Present2 in the Device are connected together. The Present2 connection CPLD of Slot is for monitoring the device presence and controlling the power-on timing, the Present2 connection 9555 is for BMC monitoring the device presence, and the Present2 connection 3V3_ STBY is through the pull-up resistor to provide the default status. When the Device is inserted into the Slot, corresponding to Present1 in the Slot connecting Present2 to ground, Present2 is pulled low, informing the CPLD and BMC Device that they are in place. However, in this embodiment, the Present2 in Slot is also connected to ground through the dip switch, so that even if the Device is not inserted into Slot, pulling down the Present2 can still be achieved by closing the dip switch, signaling the CPLD that the Device is in place. The same applies to the connection shown in fig. 7.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.
The above-described embodiments are possible examples of implementations and are presented merely for a clear understanding of the principles of the invention. Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. An in-place signal processing method during server debugging is characterized by comprising the following steps:
setting a switching device, and connecting an in-place signal end of the server equipment to the ground through the switching device;
in response to debugging the server, closing the switching device to pull the in-place signal low, simulating the server device being in place.
2. The method of claim 1, wherein debugging the server comprises implementing debugging power-up and power-down timing of the server device through a CPLD.
3. The method of claim 1, wherein the providing a switching device through which the on-bit signal terminal of the server device is connected to ground comprises:
one end of the switch device is connected with an on-position signal end of the equipment slot, and the other end of the switch device is grounded, wherein the on-position signal end is connected to a power supply through a pull-up resistor.
4. The method of claim 1, wherein the switching device is a dip switch.
5. The method of claim 1, wherein the switching device is a flip cap.
6. An in-place signal processing device during server debugging, comprising: the device comprises a CPLD, a device slot and a switch device, wherein the CPLD is connected to an on-site signal end of the device slot; one end of the switch device is connected with the in-place signal end of the equipment slot, the other end of the switch device is grounded, and the switch device is closed to pull down the in-place signal when the server is debugged, so that the CPLD is simulated that the server equipment is in place.
7. The apparatus of claim 6, wherein the in-place signal terminal of the device slot is connected to a power source through a pull-up resistor.
8. The apparatus according to claim 7, wherein when debugging the power-up and power-down timing of the server device is realized by the CPLD, the switch device is closed to pull down the presence signal, simulating that the server device is in a presence.
9. The apparatus of claim 6, wherein the switching device is a dip switch.
10. The apparatus of claim 6, wherein the switching device is a flip cap.
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| CN201911053217.8A CN110990317A (en) | 2019-10-31 | 2019-10-31 | In-place signal processing method and device during server debugging |
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| CN201911053217.8A CN110990317A (en) | 2019-10-31 | 2019-10-31 | In-place signal processing method and device during server debugging |
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