CN110988447A - Circuit diagram of surge current impact tester - Google Patents

Circuit diagram of surge current impact tester Download PDF

Info

Publication number
CN110988447A
CN110988447A CN202010007389.8A CN202010007389A CN110988447A CN 110988447 A CN110988447 A CN 110988447A CN 202010007389 A CN202010007389 A CN 202010007389A CN 110988447 A CN110988447 A CN 110988447A
Authority
CN
China
Prior art keywords
surge current
resistive element
circuit diagram
inrush current
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010007389.8A
Other languages
Chinese (zh)
Inventor
陈健武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Xincheng Technology Industry Co Ltd
Original Assignee
Guangdong Xincheng Technology Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Xincheng Technology Industry Co Ltd filed Critical Guangdong Xincheng Technology Industry Co Ltd
Priority to CN202010007389.8A priority Critical patent/CN110988447A/en
Publication of CN110988447A publication Critical patent/CN110988447A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/22Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of ac into dc
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00Arrangements for displaying electric variables or waveforms
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The invention discloses a surge current impact tester circuit diagram, which comprises a case and a handle, wherein the case is movably connected with the handle, the front side of the case is provided with a screen, a key and a test terminal, the back side of the case is provided with a power socket and a cooling fan, and the inside of the case is provided with a detection circuit for detecting surge current. The instrument is mainly used for surge current impact test of resistive elements, particularly NTC thermistors, and is particularly suitable for the following application occasions: 1. and (3) testing the resistance of the resistive element to surge current impact, namely, testing the service life of the resistive element. 2. The suppression capability of the resistive element on surge current surge is evaluated through the peak current. 3. For the design of the power supply type circuit, the selection of the element for restraining the surge current, particularly the NTC thermistor, can be facilitated.

Description

Circuit diagram of surge current impact tester
Technical Field
The invention relates to the technical field of electricity, in particular to a circuit diagram of an inrush current impact tester.
Background
The surge current refers to the peak current flowing into the power supply equipment at the moment the power supply is turned on. This peak current is much greater than the steady state input current due to the rapid charging of the input filter capacitor. The power supply should limit the surge levels that the AC switch, rectifier bridge, fuse, EMI filter devices can withstand. The loop is repeatedly switched and the AC input voltage should not damage the power supply or cause the fuse to blow.
Therefore, the surge current detection is very important, and most of the existing surge current detection equipment is large in size, complex to operate and inconvenient to use.
Disclosure of Invention
The present invention is directed to a circuit diagram of an inrush current surge tester, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
the utility model provides a surge current impact tester circuit diagram, includes quick-witted case and handle, quick-witted case and handle swing joint, the front of machine case is equipped with screen, button and test terminal, and the back of machine case is equipped with supply socket and radiator fan, and the inside of machine case is equipped with the detection circuitry who is used for detecting surge current.
As a further scheme of the invention: the number of the keys is multiple.
As a further scheme of the invention: the detection circuit comprises a rectifier bridge T, a resistive element Rx to be detected, a capacitor Cx and a load Ro, wherein input ends 1 and 3 of the rectifier bridge T are respectively connected with two ends of an alternating current power supply to be detected, an anode output end 2 of the rectifier bridge T is connected with the resistive element Rx to be detected, the other end of the resistive element Rx to be detected is connected with the capacitor Cx and the load Ro, and the other end of the load Ro is connected with the capacitor Cx and a cathode output end 4 of the rectifier bridge T.
As a further scheme of the invention: the resistive element to be tested is an NTC thermistor.
As a further scheme of the invention: the capacitance Cx is a filter capacitance.
As a further scheme of the invention: the screen adopts a 5-inch liquid crystal screen.
As a further scheme of the invention: the test terminals include a test terminal RX and a test terminal CX.
Compared with the prior art, the invention has the beneficial effects that: the invention can rapidly obtain the surge peak current and the surge current waveform. The instrument is mainly used for surge current impact test of resistive elements, particularly NTC thermistors, and is particularly suitable for the following application occasions: 1. and (3) testing the resistance of the resistive element to surge current impact, namely, testing the service life of the resistive element. 2. The suppression capability of the resistive element on surge current surge is evaluated through the peak current. 3. For the design of the power supply type circuit, the selection of the element for restraining the surge current, particularly the NTC thermistor, can be facilitated.
Drawings
Fig. 1 is a front structural view of the present invention.
Fig. 2 is a rear view of the present invention.
Fig. 3 is a circuit diagram illustrating the testing principle of the present invention.
In the figure: 1-screen, 2-key, 3-chassis, 4-test terminal, 5-handle, 6-power socket, 7-radiator fan.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1: referring to fig. 1-3, in an embodiment of the present invention, a circuit diagram of an inrush current surge tester includes a case 3 and a handle 5, where the case 3 is movably connected to the handle 5, a screen 1, a key 2, and a test terminal 4 are disposed on a front surface of the case 3, a power socket 6 and a heat dissipation fan 7 are disposed on a back surface of the case 3, and a detection circuit for detecting an inrush current is disposed inside the case. The key 2 is plural.
The detection circuit comprises a rectifier bridge T, a resistive element Rx to be detected, a capacitor Cx and a load Ro, wherein input ends 1 and 3 of the rectifier bridge T are respectively connected with two ends of an alternating current power supply to be detected, an anode output end 2 of the rectifier bridge T is connected with the resistive element Rx to be detected, the other end of the resistive element Rx to be detected is connected with the capacitor Cx and the load Ro, and the resistive element to be detected of the load Ro is an NTC thermistor. The capacitance Cx is a filter capacitance. Test terminal 4 includes test terminal RX and test terminal CX, and during the wiring, test terminal RX connects the resistance that awaits measuring, and filter capacitance is connected to test terminal CX, if filter capacitance adopts electrolytic capacitor, pays attention to the differentiation of positive negative pole. The terminal 1 pin is a positive electrode, and the other pin is a negative electrode.
The interface of the ICT-2015A type surge current impact tester is mainly divided into the following parts:
1. title bar: the model and the name of the instrument are displayed;
2. a pattern area: the method is used for displaying the waveform of the surge current in real time. The lower right corner of the graph area displays current curve resolution information and an instrument working state;
current curve resolution: the longitudinal direction of the graph, the magnitude of the current represented by each grid. Shown on the instrument as "RES: xx A";
the instrument automatically selects a proper resolution according to an actual measurement result, wherein the minimum resolution is 1A/lattice, and the maximum resolution is 20A/lattice;
the working state is as follows: in the test process, the instrument displays 'test' and displays 'standby' when the instrument is not in the test state;
3. data area: the device is used for displaying the test result in real time, wherein the test result comprises peak current and test times;
4. parameter area: the test parameters for setting the instrument comprise 4 parameters of load, impact time, impact interval time and impact times.
Example 2: on the basis of the embodiment 1, the screen 1 adopts a 167-thousand-color 5-inch liquid crystal screen, the input voltage is AC220V ± 20%, the size of a chassis is 278mm × 93mm × 315mm, the load current is 0.1-15.0A, the resolution is 0.1A, and the precision is < = 3%.
The circuit is characterized in that the circuit can not only accurately detect two stable states of the closing and the opening of the wind pressure switch, but also carry out corresponding detection and judgment when the wind pressure switch is in a shaking state. When the wind pressure switch S1 is in an off state, the voltage of the non-inverting terminal of the 3 rd pin of the comparator IC circuit U1A is zero, and at this time, the voltage of the inverting terminal of the 2 nd pin of the comparator IC circuit U1A is the voltage drop of the conducting tube of the diode D1, which is about 0.35 to 0.7V, so that the output port of the 1 st pin of the comparator IC circuit U1A is constantly at a low level, and thus the voltage of the TEST _ IO terminal is also constantly at a low level; when the wind pressure switch S1 is in a closed state, the voltage of the 3 rd pin in the phase of the comparator IC circuit U1A is greater than the voltage drop of the forward conducting tube of the diode D1 under the partial pressure of the resistors R1 and R2, so the output port of the 1 st pin of the comparator IC circuit U1A is constantly at a high level, and thus the voltage of the TEST _ IO terminal is also constantly at a high level; when the wind pressure switch S1 is in "shaking" state, the output port voltage of the 1 st pin of the corresponding comparator IC circuit U1A is in pulse state, and under the charging and discharging and filtering action of the capacitors C1 and C2, the TEST _ IO terminal voltage is in a certain intermediate voltage state between high level and low level. When the signal output end TEST _ IO level is detected to be a constant low level, the wind pressure switch S1 can be judged to be in a disconnected state; when the signal output end TEST _ IO level is detected to be a constant high level, the wind pressure switch S1 can be judged to be in a closed state; when the voltage of the signal output terminal TEST _ IO is detected to be between the high level and the low level, it can be determined that the wind pressure switch S1 is in the third state "jitter" state.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (7)

1. The utility model provides an inrush current impact tester circuit diagram, includes quick-witted case (3) and handle (5), its characterized in that, quick-witted case (3) and handle (5) swing joint, the front of quick-witted case (3) is equipped with screen (1), button (2) and test terminal (4), and the back of quick-witted case (3) is equipped with supply socket (6) and radiator fan (7), and the inside of quick-witted case is equipped with the detection circuitry who is used for detecting inrush current.
2. An inrush current surge tester circuit diagram according to claim 1, wherein there are a plurality of keys (2).
3. The circuit diagram of claim 1, wherein the detection circuit comprises a rectifier bridge T, a resistive element to be tested Rx, a capacitor Cx, and a load Ro, wherein input terminals 1 and 3 of the rectifier bridge T are respectively connected to two ends of the ac power to be tested, a positive output terminal 2 of the rectifier bridge T is connected to the resistive element to be tested Rx, the other end of the resistive element to be tested Rx is connected to the capacitor Cx and the load Ro, and the other end of the load Ro is connected to the capacitor Cx and a negative output terminal 4 of the rectifier bridge T.
4. The inrush current surge tester circuit of claim 3, wherein the resistive element to be tested is an NTC thermistor.
5. The inrush current surge tester circuit of claim 3, wherein the capacitor Cx is a filter capacitor.
6. The circuit diagram of an inrush current surge tester of claim 1, wherein the screen (1) is a 5-inch liquid crystal screen.
7. An inrush current surge tester circuit according to claim 1, wherein the test terminals (4) comprise a test terminal RX and a test terminal CX.
CN202010007389.8A 2020-01-04 2020-01-04 Circuit diagram of surge current impact tester Pending CN110988447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010007389.8A CN110988447A (en) 2020-01-04 2020-01-04 Circuit diagram of surge current impact tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010007389.8A CN110988447A (en) 2020-01-04 2020-01-04 Circuit diagram of surge current impact tester

Publications (1)

Publication Number Publication Date
CN110988447A true CN110988447A (en) 2020-04-10

Family

ID=70080804

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010007389.8A Pending CN110988447A (en) 2020-01-04 2020-01-04 Circuit diagram of surge current impact tester

Country Status (1)

Country Link
CN (1) CN110988447A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202075333U (en) * 2011-05-09 2011-12-14 深圳市航嘉驰源电气股份有限公司 Surge current tester
CN202797949U (en) * 2012-09-19 2013-03-13 苏州工业园区科佳自动化有限公司 Three-phase fixed-value surge suppressor
CN203368015U (en) * 2013-07-18 2013-12-25 江苏省黑马高科技发展有限责任公司 A surge inhibition current protective device
CN205608075U (en) * 2016-05-23 2016-09-28 重庆灿源电子有限公司 Surge current test fixture
CN107069688A (en) * 2017-05-05 2017-08-18 西安太世德航空电器有限公司 A kind of surge restraint circuit and Surge suppression method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202075333U (en) * 2011-05-09 2011-12-14 深圳市航嘉驰源电气股份有限公司 Surge current tester
CN202797949U (en) * 2012-09-19 2013-03-13 苏州工业园区科佳自动化有限公司 Three-phase fixed-value surge suppressor
CN203368015U (en) * 2013-07-18 2013-12-25 江苏省黑马高科技发展有限责任公司 A surge inhibition current protective device
CN205608075U (en) * 2016-05-23 2016-09-28 重庆灿源电子有限公司 Surge current test fixture
CN107069688A (en) * 2017-05-05 2017-08-18 西安太世德航空电器有限公司 A kind of surge restraint circuit and Surge suppression method

Similar Documents

Publication Publication Date Title
JP5292295B2 (en) Digital multimeter with automatic selection of measurement functions
CN105911353A (en) Automobile insulation resistance detection circuit and method
CN202057732U (en) Capacitor and device for detecting ripple current of high-voltage aluminium electrolytic capacitor of switch power supply
CN104502665A (en) Device and method for testing residual voltage
CN110988447A (en) Circuit diagram of surge current impact tester
CN201285436Y (en) Circuit for testing maximum starting impact current of switch electric power source
TW201222920A (en) Battery capacitance detecting system
CN112180265A (en) Battery tester
CN112433172A (en) Power failure detection device
CN214895504U (en) Novel live-line detection device of lightning arrester online monitor
CN205509565U (en) Safe charging device
CN211180079U (en) Discrete component comprehensive parameter tester
CN204330989U (en) A kind of accumulator overload performance pick-up unit
CN104181370A (en) Load current detection circuit and detection device
CN213750282U (en) Power-off detection circuit
CN215867837U (en) Device for verifying normal work of RTC chip during switching of power supply
CN216848070U (en) Storage battery test circuit without distinguishing positive electrode and negative electrode and device thereof
CN216697018U (en) Anti-surge fast transient radio frequency conduction open input hardware module
CN214097696U (en) Electronic component identification and parameter measurement device
CN219799702U (en) Battery testing system
CN217639295U (en) Square wave amplitude detection circuit and capacitance pen detection device
CN215071612U (en) Automatic protection circuit is used in laboratory
CN215116748U (en) Arrester discharge counter calibrator
CN220381209U (en) Inductance measuring device
CN217879452U (en) Full-automatic discrete component tester

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200410