CN110970348A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN110970348A CN110970348A CN201911065482.8A CN201911065482A CN110970348A CN 110970348 A CN110970348 A CN 110970348A CN 201911065482 A CN201911065482 A CN 201911065482A CN 110970348 A CN110970348 A CN 110970348A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
The invention provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole; forming an isolation layer on the inner wall surface of the through contact hole based on an oxidation process; the semiconductor structure and the preparation of the invention adopt an oxidation process to form the isolation layer, so that an etching process is not needed in the preparation process of the isolation layer, thereby being beneficial to reducing the damage of a device structure caused by plasma.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to address the difficulties encountered with flat flash memories and to pursue lower production costs per unit cell, three-dimensional memory structures have come to be developed, such as NAND memories, which can enable a greater number of memory cells per memory die in a memory device.
However, in the preparation of the existing three-dimensional memory structure, the more etching processes cause the more serious PID (plasma induced damage) problem, which may cause damage to the device structure layer, such as damage to the device gate oxide layer, resulting in reliability problem, and the method of reducing over-etching (ET OE) or etching Power (ET Power) to improve the PID problem is complex in process, which may easily result in not achieving the ideal etching preparation effect, therefore, the PID problem is difficult to be solved effectively.
Therefore, how to provide a semiconductor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art is necessary.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a semiconductor structure and a method for fabricating the same, which can solve the problems of the prior art, such as the difficulty of effectively improving the PID problem.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a first substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole;
forming an isolation layer on the inner wall surface of the through contact hole on the basis of an oxidation process; and
and filling a conductive material in the through contact hole to form a through contact part, wherein the through contact part is at least formed on the surface of the isolation layer and is electrically connected with the interconnection structure.
Optionally, the preparation method further comprises the steps of: and forming an insulating medium layer on one side of the semiconductor substrate far away from the device structure layer, wherein the through contact hole also extends through the upper surface and the lower surface of the insulating medium layer, and the through contact part is in contact with the surrounding insulating medium layer.
Optionally, the step of forming the insulating dielectric layer and the through contact hole includes:
forming an insulating medium material layer on one side of the semiconductor substrate far away from the device structure layer;
forming a patterned mask layer on the insulating medium material layer;
and etching the insulating medium material layer and the semiconductor substrate based on the patterned mask layer to form the insulating medium layer and the through contact hole.
Optionally, before forming the insulating dielectric material layer, a step of thinning a side of the semiconductor substrate away from the device structure layer is further included.
Optionally, a thinning stop portion in contact with the device structure layer is further formed in the semiconductor substrate, and a space is formed between the thinning stop portion and the through contact hole, wherein the thinning stop portion and an alignment structure in the semiconductor substrate are formed on the basis of the same process.
Optionally, the method further includes, after forming the through contact portion: and forming a welding pad lead which is electrically connected with the through contact part on the insulating medium layer.
Optionally, the method for manufacturing a semiconductor structure further includes: and providing a second base, and bonding the front surface of the second base with the surface of the side, away from the semiconductor substrate, of the device structure layer, wherein a peripheral circuit is formed in the second base, and the peripheral circuit is electrically connected with the interconnection structure.
Optionally, before forming the isolation layer, a step of cleaning at least the semiconductor substrate exposed through the contact hole is further included.
Optionally, the oxidation process comprises an in-situ water vapor generation process, wherein the oxidation temperature of the in-situ water vapor generation process is between 1000 ℃ and 1200 ℃, and the oxidation time is between 15min and 25 min.
The invention also provides a semiconductor structure, which is preferably prepared by the preparation method of the semiconductor structure, wherein the semiconductor structure comprises the following components:
the semiconductor device comprises a first substrate and a second substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole;
the isolation layer is formed on the surface of the semiconductor substrate exposed by the through contact hole;
a through contact part filled in the through contact hole, wherein the through contact part is at least formed on the surface of the isolation layer and is electrically connected with the interconnection structure;
the insulating medium layer is formed on one side, far away from the device structure layer, of the semiconductor substrate, the penetrating contact hole further extends through the upper surface and the lower surface of the insulating medium layer, and the penetrating contact portion is in contact with the surrounding insulating medium layer.
Optionally, the semiconductor structure further includes a pad lead formed on the insulating dielectric layer, and the pad lead is electrically connected to the through contact.
Optionally, a thinning stop portion contacting the device structure layer is further formed in the semiconductor substrate, and a space is formed between the thinning stop portion and the through contact hole.
Optionally, the semiconductor structure further includes a second base, and a front surface of the second base is bonded to a surface of the device structure layer on a side away from the semiconductor substrate, wherein a peripheral circuit is formed in the second base, and the peripheral circuit is electrically connected to the interconnect structure.
Optionally, the thickness of the isolation layer is between 50nm and 70nm, and the material of the semiconductor substrate comprises silicon; the material of the isolation layer comprises silicon oxide; the material of the through contact includes tungsten.
As mentioned above, the semiconductor structure and the preparation method thereof of the invention adopt the oxidation process to form the isolation layer, so that the etching process is not needed in the preparation process of the isolation layer, thereby being beneficial to reducing the damage of the device structure caused by the plasma, reducing one etching process by adopting the process of the invention, and simplifying the preparation process of the semiconductor structure.
Drawings
Fig. 1 shows a flow chart of a process for fabricating a semiconductor structure according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram illustrating a first substrate provided in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 3 is a diagram illustrating the formation of an isolation layer and a through contact in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram illustrating the formation of an insulating dielectric material layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating the formation of an insulating dielectric layer and a through contact hole in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating another example of forming an isolation layer in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 7 is a diagram illustrating another example of forming a through contact in the fabrication of a semiconductor structure provided for embodiments of the present invention.
Fig. 8 is a diagram illustrating bonding of a first substrate to a second substrate in the fabrication of a semiconductor structure provided by an embodiment of the present invention.
FIG. 9 is a schematic diagram showing a structure of forming a through contact hole in the fabrication of a semiconductor structure according to a comparative example of the present invention.
Fig. 10 is a schematic view showing a structure of forming an isolation layer in the preparation of a semiconductor structure according to a comparative example of the present invention.
Fig. 11 is a schematic structural view showing the removal of the bottom isolation layer in the preparation of the semiconductor structure according to the comparative example of the present invention.
Fig. 12 is a schematic structural view showing formation of a through contact in the preparation of a semiconductor structure according to a comparative example of the present invention.
Description of the element reference numerals
100 first substrate
101,301 semiconductor substrate
102,302 device structure layer
103,303 interconnect structure
104,304 through the contact hole
105,305 isolating layer
106,306 through the contact
107 layer of insulating dielectric material
108,307 insulating medium layer
200 second substrate
201 peripheral circuit
S1-S3
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a first substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole;
forming an isolation layer on the inner wall surface of the through contact hole on the basis of an oxidation process; and
and filling a conductive material in the through contact hole to form a through contact part, wherein the through contact part is at least formed on the surface of the isolation layer and is electrically connected with the interconnection structure.
The method of fabricating a semiconductor structure according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in S1 in fig. 1 and fig. 2 and 4-5, a first base 100 is provided, the first base 100 includes a semiconductor substrate 101 and a device structure layer 102 formed on a surface of the semiconductor substrate 101, wherein an interconnection structure 103 is formed in the device structure layer 102, a through contact hole 104 penetrating through upper and lower surfaces of the semiconductor substrate 101 is formed in the semiconductor substrate 101, and the interconnection structure 103 is exposed through the through contact hole 104.
Specifically, the semiconductor substrate 101 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) substrate, a GOI (germanium on insulator) substrate, or the like, and the semiconductor substrate 101 may also be an N-type or P-type doped substrate as needed. The skilled person can select suitable substrate materials according to practical requirements, and the substrate materials are not limited herein. In this embodiment, the semiconductor substrate 101 is a single crystal silicon wafer.
In one example, the semiconductor substrate 101 has opposing front and back surfaces, and the forming of the first base 100 includes: forming the device structure layer 102 on the front surface of the semiconductor substrate 101, that is, the front surface refers to a surface on which a device is formed, that is, device preparation is performed on the front surface of the semiconductor substrate, and optionally, ion implantation and other operations may be performed on the front surface of the semiconductor substrate 101 to form an active region and the like, so as to prepare for forming the device structure layer 102 subsequently.
In an optional example, a semiconductor device may be further formed in the device structure layer 102, a portion of the interconnect structure 103 is connected to the semiconductor device, the semiconductor device may be a transistor, a capacitor, a resistor, or the like, which needs to be electrically connected to the outside, and the interconnect structure 103 may be electrically led out based on a subsequently formed through contact 106. In this embodiment, the semiconductor structure is a memory, and a memory structure, an interconnect structure 103, a dielectric layer covering the memory structure and the interconnect structure 103, and the like are formed in the device structure layer 102 on the front surface of the semiconductor substrate 101.
In addition, the device structure layer 102 is formed with the interconnect structure 103, wherein a portion of the interconnect structure 103 exposed in the through contact hole 104 is used for electrically connecting with other conductive structures, such as a subsequently formed through contact 106, to form an electrically connected contact portion, the interconnect structure may further include other contacts and interconnect lines, etc., which are only illustrated in the figure, and in addition, the interconnect structure 103 may also be a connecting contact penetrating through the device structure layer 102.
In one example, the memory structure comprises a core region and a step region arranged around the core region, wherein the step region is formed by alternately stacking isolation layers and control gate layers, and a channel column structure penetrating through the memory structure is formed in the core region. The interconnect structure 103 within the device structure layer 102 includes vertically disposed contacts and laterally disposed interconnect lines. Optionally, the vertically arranged contact includes a contact portion to realize electrical connection with the semiconductor substrate 101, and the contact includes a word line contact connected with the step region gate layer, a channel contact connected with the top of the channel pillar structure, a common source contact penetrating the memory structure, and the like, which are arranged perpendicular to the surface direction of the semiconductor substrate 101; the laterally arranged interconnection lines include word lines, source lines, bit lines, and the like arranged in parallel to the surface direction of the semiconductor substrate 101 and connected to vertically arranged contacts. The contact portion and the interconnect line cooperate with each other to lead out a structure, which is electrically connected between the internal storage structure and the outside, in the device structure layer 102 to the bottom portion, where the structure is formed on the surface of the semiconductor substrate 101, where only a portion of the contact portion of the interconnect structure 103, which is formed on the front surface of the semiconductor substrate 101, is shown in the figure, and of course, the contact portion may be a contact portion penetrating through the device structure layer 102, or may be only located on the lower portion of the device structure layer 102.
In one example, the contact portions may be disposed in the peripheral region of the memory structure or other semiconductor devices by appropriate wiring, so as to avoid affecting the memory structure or other semiconductor devices when forming the through contact 106 penetrating through the semiconductor substrate 101.
As shown in fig. 4-5, the method for fabricating a semiconductor structure further includes, as an example, the steps of: an insulating dielectric layer 108 is formed on a side of the semiconductor substrate 101 away from the device structure layer 102, wherein the through contact hole 104 further extends through upper and lower surfaces of the insulating dielectric layer 108, and the through contact portion 106 is in contact with the surrounding insulating dielectric layer 108.
As an example, the step of forming the insulating dielectric layer 108 and the through contact hole 104 includes:
forming an insulating dielectric material layer 107 on the side of the semiconductor substrate 101 away from the device structure layer 102;
forming a patterned mask layer on the insulating dielectric material layer 107;
and etching the insulating dielectric material layer 107 and the semiconductor substrate 101 based on the patterned mask layer to form the insulating dielectric layer 108 and the through contact hole 104.
As an example, before forming the insulating dielectric material layer 107, a step of thinning a side of the semiconductor substrate 101 away from the device structure layer 102 is further included.
Specifically, in an example, the method further includes a step of forming the insulating medium layer 108, wherein the device structure layer is formed on the front surface of the semiconductor substrate 101, and the insulating medium layer 108 is formed on the back surface of the semiconductor substrate 101. The through contact holes 104 are integrally formed at corresponding positions above and below the insulating dielectric layer 108 and the semiconductor substrate 101, and simultaneously penetrate through the upper and lower surfaces of the insulating dielectric layer 108 and the upper and lower surfaces of the semiconductor substrate 101.
In an example of forming the insulating dielectric layer 108, the insulating dielectric material layer 107 may be formed by a chemical vapor deposition or the like, the insulating dielectric material layer 107 is used for protecting the semiconductor substrate 101 on one hand, and is used as an interlayer dielectric layer on the top of the semiconductor substrate 101 on the other hand, and then a structure such as an interconnection line may be formed on the surface of the insulating dielectric material layer 107. The insulating dielectric material layer 107 may be made of an insulating dielectric material commonly used in semiconductor processes, such as silicon oxide, silicon nitride, or silicon oxynitride. Then, the insulating medium material layer 107 and the semiconductor substrate 101 are etched, in an example, a photoresist layer may be formed on the insulating medium material layer 107, and patterned by photolithography to form the patterned mask layer, and then the insulating medium material layer 107 and the semiconductor substrate 101 are sequentially etched using the patterned mask layer as a mask to form a through hole penetrating through the insulating medium material layer 107 and the semiconductor substrate 101, that is, the through Contact hole 104, and simultaneously form the insulating medium layer 108, the through Contact hole 104 may be a tsc (through Si Contact), which is a Contact penetrating from the back side after the wafer is thinned, the through Contact hole 104 exposes the interconnection structure 103, in an example, the through Contact hole 104 exposes the Contact portion of the interconnection structure 103, in a specific implementation manner, the contact part surface is covered with an adhesion layer, such as a TiN layer or a TaN layer, and the like, and is easy to be silicided in chemical vapor deposition or other high-temperature processes to form titanium silicide or tantalum silicide and the like, and the resistance is high. In order to reduce the contact resistance between the through contact 106 and the contact portion, which are formed later, the metal silicide layer on the surface of the contact portion may be further etched and removed after the contact portion is exposed during the formation of the through contact hole 104.
In an optional example, after the device structure layer 102 is formed on the front surface of the semiconductor substrate 101 and before the insulating medium layer 108 is formed, the back surface of the semiconductor substrate 101 is thinned, a chemical mechanical polishing process may be adopted to thin the back surface of the semiconductor substrate 101, so as to reduce the thickness of the semiconductor substrate 101, thereby reducing the etching depth of a through hole penetrating through the semiconductor substrate 101 in subsequent formation.
In an optional example, before the device structure layer 102 is formed, a thinning stop portion may be formed on one side of the semiconductor substrate 101 where the device structure layer 102 is formed, a recess may be formed on the surface of the semiconductor substrate 101, and the recess is filled with an insulating material to form the thinning stop portion, the insulating material may be silicon oxide, and then the semiconductor substrate 101 is stopped on the thinning stop portion when the back surface of the semiconductor substrate 101 is mechanically ground and thinned, the grinding rate control of the chemical mechanical grinding process is relatively complex, and the grinding process is controlled by time to easily cause over grinding, so that the thickness of the semiconductor substrate 101 after grinding is smaller than a preset thickness, the thinning stop portion is provided to facilitate the control of the chemical mechanical grinding, so as to improve the thinning accuracy, optionally, the thinning stop portion may be prepared based on the same process as an alignment structure in the semiconductor structure, thereby, the thinning efficiency can be improved on the basis of forming the thinning stop portion without wasting the process. In addition, the thinning stopping part is made of insulating materials, and when metal structures such as a welding pad lead and the like are formed on the insulating medium layer subsequently, the area of the metal structures of the welding pad lead opposite to the semiconductor substrate can be reduced, so that the reduction of parasitic capacitance can be facilitated.
As shown in S2 of fig. 1 and fig. 3 and 6, an isolation layer 105 is formed on the inner wall surface of the through contact hole 104 based on an oxidation process.
As an example, the oxidation process includes an in-situ water vapor generation process (ISSG), the oxidation temperature of the in-situ water vapor generation process is between 1000 ℃ and 1200 ℃, and the oxidation time is between 15min and 25min, and the in-situ water vapor generation process is beneficial to improving the compactness and the insulation of the obtained oxide layer (the isolation layer), and is beneficial to improving the device performance.
As an example, before forming the isolation layer 105, a step of cleaning at least the semiconductor substrate 101 exposed by the through contact hole 104 is further included.
Specifically, the isolation layer 105 is formed by an oxidation process, the isolation layer 105 can isolate the semiconductor substrate 101 from the filling material in the through contact hole 104, the isolation layer 105 can be made of silicon oxide, the isolation layer 105 can be directly formed on the surface of the semiconductor substrate 101 exposed by the through contact hole 104 by the oxidation process, and thus, processes such as etching and the like are not required to be introduced, the PID problem caused by etching is avoided, and the influence of plasma on the device structure is prevented, wherein in an example of using an etching process, an isolation material layer is generally deposited on the sidewall and the bottom surface of the through contact hole 104, for example, an Atomic Layer Deposition (ALD) process can be used for deposition, then the bottom isolation material layer is removed by the etching process to form the isolation layer 105 on the sidewall, and in this process, charges in the etching process can remain in the device, when a conductive structure, such as the through contact 106, is subsequently formed, charge movement may occur to flow to other structures, such that the charge movement may cause damage to the surrounding device structure, such as by damaging a gate oxide (gate OX) of the device, wherein the accumulation of residual charge may cause a potential difference to be formed, thereby causing an abnormal tunneling current in the gate OX, which may cause damage to the gate OX structure, thereby causing reliability problems. As shown in fig. 6, when the insulating dielectric layer 108 is present, the isolation layer 105 formed based on an oxidation process is only formed on the exposed surface of the semiconductor substrate 101, and is not formed on the surface of the insulating dielectric layer 108 exposed by the through contact hole 104, and the exposed surface of the insulating dielectric layer 108 is in direct contact with the through contact 106 subsequently filled in the through contact hole 104, which may also increase the size of the conductive contact and reduce the resistance, in an example, the material of the insulating dielectric layer 108 is the same as the material of the isolation layer 105.
In one example, the oxidation process includes an in-situ water vapor generation process, and a dry oxidation process is adopted, wherein an oxidation temperature of the in-situ water vapor generation process is between 1000 ℃ and 1200 ℃, 1050 ℃, 1100 ℃, 1150 ℃ and the like, an oxidation time is between 15min and 25min, 18min, 20min, 22min and the like, and a thickness of the isolation layer 105 is between 50nm and 70nm, 55nm, 60nm, 65nm and the like.
In addition, in an example, the semiconductor substrate 101 may be cleaned before the isolation layer 105 is formed by the following oxidation, and what may be used for cleaning, for example, SC1 may be used for cleaning to form a good interface, such as a good silicon interface, to facilitate the implementation of the subsequent oxidation process.
As an example, as shown in fig. 8, the method for manufacturing a semiconductor structure further includes the steps of: providing a second base 200, and bonding the front surface of the second base 200 with the surface of the device structure layer 102 far away from the semiconductor substrate 101, wherein a peripheral circuit 201 is formed in the second base 200, and the peripheral circuit 201 is electrically connected with the interconnection structure 103.
Specifically, in an example, the front surface of the first substrate 100 is bonded to the front surface of the second substrate 200, in an example, the front surface refers to a surface on which a device is fabricated, a peripheral circuit 201 is formed in the second substrate 200, the interconnect structure 103 in the first substrate 100 is connected to the peripheral circuit 201, the peripheral circuit 201 is used to form an electrical connection with a memory structure in the device structure layer 102, a control voltage is applied to the memory structure, and the like, and the second substrate 200 may be a CMOS wafer. Only a part of vertically arranged contacts in the second substrate 200 is illustrated as a peripheral circuit 201, and part of the contacts in the peripheral circuit 201 and the interconnect structure 103 in the device structure layer 102 are electrically connected through metal bonding, so that the electrical connection is formed with a memory structure or other semiconductor devices in the device structure layer 102. In an example, the first base 100 and the second base 200 may be bonded after the device structure layer 102 is formed and before the insulating dielectric material layer 107 is formed, and further, may be bonded before the back surface of the semiconductor substrate 101 is thinned.
As shown in S3 of fig. 1 and fig. 3 and 7, the through contact hole 104 is filled with a conductive material to form a through contact 106, which is formed at least on the surface of the isolation layer 105 and electrically connected to the interconnect structure 103.
As an example, the step of forming the through contact 106 further includes: a pad lead electrically connected to the through contact 106 is formed on the insulating dielectric layer 108.
Specifically, a chemical vapor deposition process, a sputtering process, or the like may be used to form a conductive material filling the through contact hole 104, and when the insulating dielectric layer 108 is present, the conductive material further extends to cover the insulating dielectric layer 108, and planarizes the conductive material to form the through contact 106 located in the through contact hole 104. The conductive material may be a metal material, such as W, Cu, Al, etc., and may also be polysilicon, etc. In one embodiment, the conductive material is W. In another embodiment, a conductive adhesion layer, such as TiN or TaN, may be deposited on the inner wall surface of the through contact hole 104 and the surface of the isolation layer, and then a conductive pillar is formed in the through contact hole 104, where the through contact 106 includes the adhesion layer and the conductive pillar, the adhesion layer may improve adhesion between the through contact 106 and the semiconductor substrate 101 and the insulating dielectric layer 108, and may block out diffusion of conductive pillar atoms when the conductive pillar material is a readily diffusible metal material.
In addition, in an example, a step of forming a pad lead is further included, for example, a metal layer may be formed and then etched to form a pad lead (pad lead), the metal layer may be an aluminum layer, but is not limited thereto, and when the insulating dielectric layer 108 is present, the pad lead is formed on a side of the insulating dielectric layer 108 away from the semiconductor substrate 101.
As shown in fig. 7 and referring to fig. 1-6, the present invention also provides a semiconductor structure, which is preferably prepared by the method for preparing a semiconductor structure of the present invention, but can be prepared by other methods, wherein the semiconductor structure comprises:
a first substrate 100 including a semiconductor substrate 101 and a device structure layer 102 formed on a surface of the semiconductor substrate 101, wherein an interconnection structure 103 is formed in the device structure layer 102, a through contact hole 104 penetrating through upper and lower surfaces of the semiconductor substrate 101 is formed in the semiconductor substrate 101, and the through contact hole exposes the interconnection structure 103;
an isolation layer 105 formed on the surface of the semiconductor substrate 101 exposed by the through contact hole 104;
and a through contact 106 filled in the through contact hole 104, wherein the through contact 106 is formed at least on the surface of the isolation layer 105 and electrically connected to the interconnect structure 103.
As an example, the first substrate 100 further includes an insulating dielectric layer 108 formed on a side of the semiconductor substrate 101 away from the device structure layer 102, wherein the through contact hole 104 further extends through upper and lower surfaces of the insulating dielectric layer 108, and the through contact 106 is in contact with the surrounding insulating dielectric layer 108.
Specifically, the semiconductor substrate 101 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) substrate, a GOI (germanium on insulator) substrate, or the like, and the semiconductor substrate 101 may also be an N-type or P-type doped substrate as needed. The skilled person can select suitable substrate materials according to practical requirements, and the substrate materials are not limited herein. In this embodiment, the semiconductor substrate 101 is a single crystal silicon wafer.
In one example, the semiconductor substrate 101 has opposing front and back surfaces, and the forming of the first base 100 includes: the device structure layer 102 is formed on the front surface of the semiconductor substrate 101, and optionally, operations such as ion implantation may be performed on the front surface of the semiconductor substrate 101 to form an active region and the like, so as to prepare for the subsequent formation of the device structure layer 102.
In an alternative example, a semiconductor device may be further formed in the device structure layer 102, and a portion of the interconnect structure 103 is connected to the semiconductor device, where the semiconductor device may be a transistor, a capacitor, a resistor, or the like that needs to be electrically connected to the outside. In this embodiment, the semiconductor structure is a memory, and a memory structure, an interconnect structure 103, a dielectric layer covering the memory structure and the interconnect structure 103, and the like are formed in the device structure layer 102 on the front surface of the semiconductor substrate 101.
In addition, the device structure layer 102 is formed with the interconnect structure 103, wherein a portion of the interconnect structure 103 exposed in the through contact hole 104 is used for electrically connecting with other conductive structures, such as a subsequently formed through contact 106, to form an electrically connected contact portion, the interconnect structure may further include other contacts and interconnect lines, etc., which are only illustrated in the figure, and in addition, the interconnect structure 103 may also be a connecting contact penetrating through the device structure layer 102.
In one example, the memory structure includes a core region and a step region disposed around the core region, the step region is formed by alternately stacking isolation layers 105 and control gate layers, and a channel pillar structure penetrating through the memory structure is formed in the core region. The interconnect structure 103 within the device structure layer 102 includes vertically disposed contacts and laterally disposed interconnect lines. Alternatively, the vertically arranged contact includes a contact portion for electrical connection to achieve electrical connection with the semiconductor substrate 101, and the contact includes: a word line contact portion connected to the step region gate layer, a channel contact portion connected to the top of the channel pillar structure, a common source contact portion penetrating the memory structure, and the like, which are provided in a direction perpendicular to the surface of the semiconductor substrate 101; the interconnect lines that are laterally disposed include: word lines, source lines, bit lines, and the like connected to vertically arranged contacts arranged in parallel to the surface direction of the semiconductor substrate 101. The contact part and the interconnection line are mutually matched, and the structure which is electrically connected with the outside and is stored in the device structural layer 102 is led out to the contact part or the interconnection line which is formed on the surface of the semiconductor substrate 101 at the bottom. Only a part of the contact portion of the interconnect structure 103, the bottom of which is formed on the front surface of the semiconductor substrate 101, is shown in the figure, but of course, the contact portion may be a contact portion penetrating through the device structure layer 102, or may be located only at the lower portion of the device structure layer 102. The memory structure is subsequently electrically connected to the outside by forming through contacts 106 through the semiconductor substrate 101, connecting with the contacts or interconnect lines.
In one example, the contact portions may be disposed in the peripheral region of the memory structure or other semiconductor devices by appropriate wiring, so as to avoid affecting the memory structure or other semiconductor devices when forming the through contact 106 penetrating through the semiconductor substrate 101.
Specifically, the isolation layer 105 may isolate the semiconductor substrate 101 from the filling material in the through contact hole 104, and the thickness of the isolation layer 105 is between 50nm and 70nm, and may be 55nm, 60nm, 65nm, or the like. The material of the through contact 106 may be a metal material, such as W, Cu, Al, or the like, or may be polysilicon, or the like. In one embodiment, the material of the through contact 106 is W. In an example, the first base 100 further includes the insulating medium layer 108, wherein the valence structure layer is formed on the front surface of the semiconductor substrate 101, and the insulating medium layer 108 is formed on the back surface of the semiconductor substrate 101. The through contact holes 104 are integrally formed at the corresponding positions above and below the insulating dielectric layer 108 and the semiconductor substrate 101, and simultaneously penetrate through the upper and lower surfaces of the insulating dielectric layer 108 and the upper and lower surfaces of the semiconductor substrate 101. In this example, the isolation layer 105 formed based on the oxidation process is formed only on the exposed surface of the semiconductor substrate 101, and is not formed on the surface of the insulating dielectric layer 108 exposed by the through contact hole 104, and the exposed surface of the insulating dielectric layer 108 is in direct contact with the through contact 106 subsequently filled in the through contact hole 104, and the size of the conductive contact can be increased, and the resistance can be reduced, in one example, the material of the insulating dielectric layer 108 is the same as that of the isolation layer 105.
As an example, a thinning stop portion contacting the device structure layer is further formed in the semiconductor substrate, and a space is provided between the thinning stop portion and the through contact hole.
Specifically, a thinning stop portion is formed on the semiconductor substrate 101 at the side where the device structure layer 102 is formed, a recess may be formed in the surface of the semiconductor substrate 101, and the thinning stop portion may be formed by filling the recess with an insulating material, which may be silicon oxide, furthermore, when the back surface of the semiconductor substrate 101 is thinned by mechanical polishing, the back surface is stopped at the thinning stop portion, the polishing rate control in the chemical mechanical polishing process is complicated, over-polishing is easily caused by controlling the polishing process with time, so that the thickness of the semiconductor substrate 101 after polishing is smaller than a predetermined thickness, the arrangement of the thinning stop part is beneficial to the control of chemical mechanical polishing, improves the thinning precision, alternatively, the thinning stop may be fabricated on the same process as the alignment structure in the semiconductor structure, thereby, the thinning efficiency can be improved on the basis of forming the thinning stop portion without wasting the process. In addition, the thinning stopping part is made of insulating materials, and when metal structures such as a welding pad lead and the like are formed on the insulating medium layer subsequently, the area of the metal structures of the welding pad lead opposite to the semiconductor substrate can be reduced, so that the reduction of parasitic capacitance can be facilitated.
Illustratively, the semiconductor structure further includes a pad lead formed on the insulating dielectric layer 108, the pad lead being electrically connected to the through contact 106. For example, a metal layer may be formed and then etched to form a pad wire (pad wire), the metal layer may be an aluminum layer, but not limited to this, and when the insulating dielectric layer 108 is present, the pad wire is formed on a side of the insulating dielectric layer 108 away from the semiconductor substrate 101.
As an example, the semiconductor structure further includes a second base 200, and a front surface of the second base 200 is bonded to a surface of the device structure layer 102 on a side away from the semiconductor substrate 101, wherein a peripheral circuit 201 is formed in the second base 200, and the peripheral circuit 201 is electrically connected to the interconnect structure 103.
Specifically, in an example, the front surface of the first substrate 100 is bonded to the front surface of the second substrate 200, a peripheral circuit 201 is formed in the second substrate 200, the interconnect structure 103 in the first substrate 100 is connected to the peripheral circuit 201, the peripheral circuit 201 is used to form an electrical connection with a memory structure in the device structure layer 102, a control voltage is applied to the memory structure, and the like, and the second substrate 200 may be a CMOS wafer. Only a part of vertically arranged contacts in the second substrate 200 is illustrated as a peripheral circuit 201, and part of the contacts in the peripheral circuit 201 and the interconnect structure 103 in the device structure layer 102 are electrically connected through metal bonding, so that the electrical connection is formed with a memory structure or other semiconductor devices in the device structure layer 102.
Comparative example:
the present invention further provides a comparative example, as shown in fig. 9-12, in the process of forming the semiconductor structure of the present comparative example, after forming the through contact hole in the semiconductor substrate and the insulating dielectric layer, an atomic layer deposition process is first used to form an isolation material layer on the bottom and inner wall surface of the through contact hole, as shown in fig. 10, the isolation material layer further extends to the insulating dielectric layer around the through contact hole, then an etching process is used to remove the material at the bottom of the through contact hole to expose the interconnection structure in the device structure layer, as shown in fig. 11, then the through contact hole is filled with a tungsten material to form a conductive contact portion, as shown in fig. 12, by using this method, during the process of etching to remove the isolation material layer at the bottom of the through contact hole, charges may remain in the device, when the conductive through contact portion is formed subsequently, charge migration may occur to other structures, causing damage to surrounding device structures. By adopting the scheme of the embodiment of the invention, the oxidation process is adopted to replace the deposition and etching processes in the comparative example, so that the etching process can be reduced, the damage of the plasma to the device in the etching process can be reduced, the process is simplified and the PID problem is reduced compared with the process of the comparative example.
In summary, the present invention provides a semiconductor structure and a method for fabricating the same, the method comprising: providing a first substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole; forming an isolation layer on the inner wall surface of the through contact hole on the basis of an oxidation process; according to the semiconductor structure and the preparation method thereof, the isolation layer is formed by adopting an oxidation process, so that an etching process is not needed in the preparation process of the isolation layer, the damage of the device structure caused by plasma can be reduced, and the preparation process of the semiconductor structure is simplified by adopting the process of the invention to reduce one etching process. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method for fabricating a semiconductor structure, the method comprising:
providing a first substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole;
forming an isolation layer on the inner wall surface of the through contact hole on the basis of an oxidation process; and
and filling a conductive material in the through contact hole to form a through contact part, wherein the through contact part is at least formed on the surface of the isolation layer and is electrically connected with the interconnection structure.
2. The method of claim 1, further comprising: and forming an insulating medium layer on one side of the semiconductor substrate far away from the device structure layer, wherein the through contact hole also extends through the upper surface and the lower surface of the insulating medium layer, and the through contact part is in contact with the surrounding insulating medium layer.
3. The method of claim 2, wherein the step of forming the insulating dielectric layer and the through contact hole comprises:
forming an insulating medium material layer on one side of the semiconductor substrate far away from the device structure layer;
forming a patterned mask layer on the insulating medium material layer;
and etching the insulating medium material layer and the semiconductor substrate based on the patterned mask layer to form the insulating medium layer and the through contact hole.
4. The method of claim 3, further comprising thinning a side of the semiconductor substrate away from the device structure layer before forming the insulating dielectric material layer.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein a thinning stop portion in contact with the device structure layer is further formed in the semiconductor substrate, and a space is provided between the thinning stop portion and the through contact hole, wherein the thinning stop portion and the alignment structure in the semiconductor substrate are formed based on the same process.
6. The method for manufacturing a semiconductor structure according to claim 2, further comprising, after forming the through contact, the steps of: and forming a welding pad lead which is electrically connected with the through contact part on the insulating medium layer.
7. The method of claim 1, further comprising: and providing a second base, and bonding the front surface of the second base with the surface of the side, away from the semiconductor substrate, of the device structure layer, wherein a peripheral circuit is formed in the second base, and the peripheral circuit is electrically connected with the interconnection structure.
8. The method of fabricating a semiconductor structure according to claim 1, further comprising, before forming the isolation layer, the steps of: and cleaning at least the surface of the semiconductor substrate exposed by the through contact hole.
9. The method of any one of claims 1-8, wherein the oxidation process comprises an in-situ water vapor generation process, wherein the in-situ water vapor generation process is performed at an oxidation temperature of between 1000 ℃ and 1200 ℃ and for an oxidation time of between 15min and 25 min.
10. A semiconductor structure, comprising:
the semiconductor device comprises a first substrate and a second substrate, wherein the first substrate comprises a semiconductor substrate and a device structure layer formed on the surface of the semiconductor substrate, an interconnection structure is formed in the device structure layer, a through contact hole penetrating through the upper surface and the lower surface of the semiconductor substrate is formed in the semiconductor substrate, and the interconnection structure is exposed through the through contact hole;
the isolation layer is formed on the surface of the semiconductor substrate exposed by the through contact hole; and
a through contact part filled in the through contact hole, wherein the through contact part is at least formed on the surface of the isolation layer and is electrically connected with the interconnection structure;
the insulating medium layer is formed on one side, far away from the device structure layer, of the semiconductor substrate, the penetrating contact hole further extends through the upper surface and the lower surface of the insulating medium layer, and the penetrating contact portion is in contact with the surrounding insulating medium layer.
11. The semiconductor structure of claim 10, further comprising a pad lead formed on the insulating dielectric layer, the pad lead being electrically connected to the through contact.
12. The semiconductor structure according to claim 10, wherein a thinning stop portion in contact with the device structure layer is further formed in the semiconductor substrate, the thinning stop portion having a space from the through-contact hole.
13. The semiconductor structure of claim 10, further comprising a second base having a front surface bonded to a surface of the device structure layer on a side away from the semiconductor substrate, wherein a peripheral circuit is formed in the second base and electrically connected to the interconnect structure.
14. The semiconductor structure of any of claims 10-13, wherein the spacer layer has a thickness between 50nm and 70 nm; the material of the semiconductor substrate comprises silicon; the material of the isolation layer comprises silicon oxide; the material of the through contact includes tungsten.
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