CN110967885B - Liquid crystal display panel and array substrate thereof - Google Patents

Liquid crystal display panel and array substrate thereof Download PDF

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Publication number
CN110967885B
CN110967885B CN201911325075.6A CN201911325075A CN110967885B CN 110967885 B CN110967885 B CN 110967885B CN 201911325075 A CN201911325075 A CN 201911325075A CN 110967885 B CN110967885 B CN 110967885B
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pixel electrode
sub
scan line
switching element
main
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CN110967885A (en
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肖偏
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)

Abstract

The invention discloses a liquid crystal display panel and an array substrate thereof. The array substrate comprises a plurality of pixel units, and each pixel unit comprises a pixel electrode, a main switch element, a sub-switch element and a shared switch element. Wherein each two of the plurality of pixel units share one data line and two scan lines, and the two scan lines are disposed on the same side, such that the pixel electrodes cross the two scan lines and are connected to the data line and the two scan lines through the main switching element, the sub-switching element and/or the shared switching element.

Description

Liquid crystal display panel and array substrate thereof
Technical Field
The present invention relates to a display device, and more particularly to a liquid crystal display panel.
Background
The liquid crystal display device has the advantages of low cost, low power consumption and high performance, and is widely applied to the fields of electronics, digital products and the like. The driving of the pixel units in the display device is realized by driving the corresponding scan lines and data lines through the gate driving circuit and the source driving circuit. With the increasing demand for panel size, resolution, and large-viewing-angle image quality, and further improving user experience and saving cost, various manufacturers have developed many manufacturing technologies related to the display field, such as Half Source Driver (HSD) technology.
Referring to fig. 1, in the most common design of the half-source driving in the prior art, the brightness of the left and right pixels P1 and P2 is controlled by a single Thin Film Transistor (TFT), and the left and right adjacent sub-pixels P1 and P2 share a data line DmAnd using a different sweeping line GN-1,GNAddressing is performed to achieve a liquid crystal display frame with halved data lines. By the technology, half of the source driving chip can be saved.
In some designs, for example, for a Vertical Alignment (VA) mode liquid crystal display, two rows of pixel units are connected to the same data line, and the doubled number of scan lines shortens the scan time of the pixel units, so that the problems of insufficient driving capability, inconsistent charging efficiency, unbalanced parasitic capacitance between the pixel units, delay distortion of signal waveforms, and the like are easily caused, and the phenomena of large viewing angle color shift, vertical bright and dark lines, and the like of the display device are caused.
Therefore, it is necessary to provide a liquid crystal display panel to solve the problems of the prior art.
Disclosure of Invention
The present invention is directed to a liquid crystal display panel and an array substrate thereof, which can solve the problem of color shift of viewing angle and improve the stability and quality of the display panel.
To achieve the above object, an embodiment of the present invention provides an array substrate of a liquid crystal display panel, wherein the array substrate of the liquid crystal display panel includes:
a plurality of pixel units, each pixel unit including a pixel electrode, a main switching element, a sub-switching element, and a shared switching element;
each two of the pixel units share one data line and two scanning lines, and the two scanning lines are arranged on the same side, so that the pixel electrodes cross the two scanning lines and are connected to the data line and the two scanning lines through the main switching element, the sub-switching element and/or the shared switching element.
According to a preferred embodiment of the present invention, each of the plurality of pixel units includes a first pixel unit and a second pixel unit, the first pixel unit includes a first main pixel electrode, a first sub-pixel electrode, a first main switch element, a first sub-switch element and a first shared switch element, the second pixel unit includes a second main pixel electrode, a second sub-pixel electrode, a second main switch element, a second sub-switch element and a second shared switch element, and the two scan lines are disposed between the first main pixel electrode and/or the second main pixel electrode and the first sub-pixel electrode and/or the second sub-pixel electrode.
According to a preferred embodiment of the present invention, the two scan lines include a first scan line and a second scan line, the first scan line is disposed near the first main pixel electrode and/or the second main pixel electrode, the second scan line is disposed near the first sub-pixel electrode and/or the second sub-pixel electrode, the first sub-pixel electrode crosses the second scan line and is connected to the first scan line and the data line through the first sub-switch element, and the second sub-pixel electrode is connected to the second scan line and the data line through the second sub-switch element.
According to a preferred embodiment of the present invention, the first main pixel electrode is connected to the first scan line and the data line through the first main switching element, and the second main pixel electrode is connected to the second scan line and the data line through the second main switching element across the first scan line.
According to a preferred embodiment of the present invention, the first sub-pixel electrode is connected to the first scan line through the first shared switching element across the second scan line, and the second sub-pixel electrode is connected to the second scan line through the second shared switching element.
According to a preferred embodiment of the present invention, the main switching element, the sub-switching elements and the shared switching element are thin film transistors.
Furthermore, another embodiment of the present invention provides a liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, and the array substrate includes:
a plurality of pixel units, each pixel unit including a pixel electrode, a main switching element, a sub-switching element, and a shared switching element;
wherein each two of the plurality of pixel units share one data line and two scan lines, and the two scan lines are disposed on the same side, such that the pixel electrodes cross the two scan lines and are connected to the data line and the two scan lines through the main switching element, the sub-switching element and/or the shared switching element.
According to a preferred embodiment of the present invention, each of the plurality of pixel units includes a first pixel unit and a second pixel unit, the first pixel unit includes a first main pixel electrode, a first sub-pixel electrode, a first main switch element, a first sub-switch element and a first shared switch element, the second pixel unit includes a second main pixel electrode, a second sub-pixel electrode, a second main switch element, a second sub-switch element and a second shared switch element, and the two scan lines are disposed between the first main pixel electrode and/or the second main pixel electrode and the first sub-pixel electrode and/or the second sub-pixel electrode.
According to a preferred embodiment of the present invention, the two scan lines include a first scan line and a second scan line, the first scan line is disposed near the first main pixel electrode and/or the second main pixel electrode, the second scan line is disposed near the first sub-pixel electrode and/or the second sub-pixel electrode, the first sub-pixel electrode crosses the second scan line and is connected to the first scan line and the data line through the first sub-switching element, and the second sub-pixel electrode is connected to the second scan line and the data line through the second sub-switching element.
According to a preferred embodiment of the present invention, the first main pixel electrode is connected to the first scan line and the data line through the first main switching element, and the second main pixel electrode is connected to the second scan line and the data line through the second main switching element across the first scan line.
According to a preferred embodiment of the present invention, the first sub-pixel electrode is connected to the first scan line through the first shared switching element across the second scan line, and the second sub-pixel electrode is connected to the second scan line through the second shared switching element.
According to a preferred embodiment of the present invention, the main switching element, the sub-switching elements and the shared switching element are thin film transistors
Compared with the prior art, the invention provides an eight-area (8-domian) design under a semi-source electrode driving framework, wherein the left and right adjacent pixels are controlled by three thin film transistors crossing two scanning lines and one data line.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
Fig. 1 is a schematic diagram of a prior art pixel circuit.
Fig. 2 is a schematic diagram of a pixel circuit of an array substrate according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a display panel module according to an embodiment of the invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Furthermore, directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
Referring to fig. 2, fig. 2 is a schematic diagram of a pixel circuit of an array substrate according to an embodiment of the invention. The first embodiment of the present invention provides an array substrate 200 of a liquid crystal display panel, which includes a plurality of pixel units 201,202, etc. (not fully shown), a plurality of data lines D0,D1…Dm(not fully shown) and a plurality of scan lines G0,…GN-1,GN(not fully shown). In an embodiment of the invention, two pixel units adjacent to each other on the left and right are used as a group, and share a data line DmAnd two scanning lines GN,GN-1. For example, the two pixel units respectively include a first pixel unit 201 and a second pixel unit 202. The first pixel unit 201 includes a first main pixel electrode 211, a first sub-pixel electrode 212, a first main switch element 231, a first sub-switch element 241 and a first shared switch element 251. The second pixel unit 202 includes a second main pixel electrode 221, a second sub-pixel electrode 222, a second main switch element 232, a second sub-switch element 242, and a second shared switch element 252. Preferably, the main switch device, the sub-switch device and the shared switch device are Thin Film Transistors (TFTs), but not limited thereto.
In the inventionIn one embodiment, the first main pixel electrode 211 and the second main pixel electrode 221 are located in the same row, and the first sub-pixel electrode 212 and the second sub-pixel electrode 222 are located in the same row. The areas of the first sub-pixel electrode 212 and the second sub-pixel electrode 222 are respectively larger than the areas of the first main pixel electrode 211 and the second main pixel electrode 221. The first pixel unit 201 and the second pixel unit 202 share the data line DmA first scanning line GN-1And a second scanning line GN. Data line DmDisposed between the first pixel unit 201 and the second pixel unit 202. First scanning line GN-1And a second scanning line GNAre arranged on the same side. Preferably, the first scanning line GN-1And a second scanning line GNAre disposed in the space between the first main pixel electrode 211 and/or the second main pixel electrode 221 and the first sub-pixel electrode 212 and/or the second sub-pixel electrode 222.
In an embodiment of the present invention, the first scan line GN-1A second scan line G disposed near the first main pixel electrode 211 and/or the second main pixel electrode 222NIs disposed near the first sub-pixel electrode 212 and/or the second sub-pixel electrode 222. The first main switch element 231 is disposed on the first main pixel electrode 211 and the first scan line GN-1In the meantime. The first sub-switch element 241 and the first shared switch element 251 are disposed on the first scan line GN-1And a second scanning line GNIn between. The second main switch element 232 is disposed on the first scan line GN-1And a second scanning line GNIn between. The second sub-switching element 242 and the second shared switching element 252 are disposed on the second scan line GNAnd the second sub-pixel electrode 222.
With such a design, the connection line of the first sub-pixel electrode 212 crosses the second scan line GNIs coupled to a first terminal (a left terminal in the drawing) of the first sub-switching element 241 and a second terminal (a right terminal in the drawing) of the first shared switching element 251. A second terminal of the first sub-switching element 241 is coupled to the data line Dm. The gate terminals of the first sub-switch device 241 and the first common device 251 are coupled to the first scan line GN-1. A first main pixelThe connection line of the pole 211 is not required to be coupled to the first terminal of the first main switching element 231 across any scan line. The second terminal of the first main switch element 231 is coupled to the data line DmAnd the gate terminal of the first main switch element 231 is coupled to the first scan line GN-1。
Under the same design, the connection line of the second main pixel electrode 221 crosses the first scan line GN-1To a second terminal (right terminal in the drawing) of the second main switching element 232. The first terminal (the left terminal in the figure) and the gate terminal of the second main switch element 232 are respectively coupled to the data line DmAnd the second scanning line GN. The connection line of the second sub-pixel electrode 222 need not be coupled to the second terminal of the second sub-switching element 242 and the first terminal of the second shared switching element 252 across any scan line. The second end of the second sub-switch element 242 is coupled to the data line Dm. The gate terminal of the second sub-switch device 242 and the gate terminal of the second shared switch device 252 are coupled to the second scan line GN。
Because each pixel unit is additionally provided with a shared switch element for dividing part of the current received by the sub-pixel electrode, the voltage value of the sub-pixel electrode is reduced. Preferably, the channel width of the thin film transistor as the shared switching element may be different from the channel width of the thin film transistor of the sub-switching element.
Referring to fig. 3, fig. 3 is a schematic view of a display panel module according to an embodiment of the invention. In another embodiment of the present invention, a liquid crystal display panel 300 is provided, wherein the liquid crystal display panel 300 includes the array substrate 200. The structure or operation principle of the display panel 300 is the same as or similar to that of the array substrate 200, and thus, the description thereof is omitted.
Compared with the prior art, the pixel circuit and the structure provided by the invention not only enhance the charging efficiency of the display panel, but also solve the problem of color cast of the viewing angle, and improve the stability and the quality of the display panel.
The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the invention.

Claims (5)

1. An array substrate for a liquid crystal display panel, comprising:
the first pixel unit comprises a first main pixel electrode, a first sub-pixel electrode, a first main switch element, a first sub-switch element and a first shared switch element;
a second pixel unit including a second main pixel electrode, a second sub-pixel electrode, a second main switching element, a second sub-switching element, and a second shared switching element;
a plurality of scan lines including a first scan line and a second scan line; and
a plurality of data lines;
wherein the first pixel unit and the second pixel unit share one data line D of the data linesmThe first scan line and the second scan line are disposed between the first main pixel electrode and the first sub-pixel electrode and/or between the second main pixel electrode and the second sub-pixel electrode, the first scan line is disposed near the first main pixel electrode and/or the second main pixel electrode, the second scan line is disposed near the first sub-pixel electrode and/or the second sub-pixel electrode, the first shared switching element is disposed between the first scan line and the second scan line, and the second shared switching element is disposed between the second scan line and the second sub-pixel electrode.
2. The array substrate for a liquid crystal display panel according to claim 1, wherein: the first sub-pixel electrode crosses the second scan line and is connected to the first scan line and the data line D through the first sub-switching elementmAnd the second sub-pixel electrode is connected to the second scan line and the data line D through the second sub-switching elementm。
3. The array substrate for a liquid crystal display panel according to claim 2, wherein: the first main pixel electrode is connected to the first scan line and the data line D through the first main switching elementmAnd the second main pixel electrode is connected to the second scan line and the data line D through the second main switching element across the first scan linem。
4. The array substrate for a liquid crystal display panel according to claim 2, wherein: the first sub-pixel electrode is connected to the first scan line through the first shared switching element across the second scan line, and the second sub-pixel electrode is connected to the second scan line through the second shared switching element
5. A liquid crystal display panel comprising the array substrate according to claim 1.
CN201911325075.6A 2019-12-20 2019-12-20 Liquid crystal display panel and array substrate thereof Active CN110967885B (en)

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CN102902120A (en) * 2012-08-17 2013-01-30 友达光电股份有限公司 Stereoscopic display panel, display panel and driving method thereof
CN103616785A (en) * 2013-11-08 2014-03-05 友达光电股份有限公司 Pixel array
CN105301854A (en) * 2015-09-15 2016-02-03 友达光电股份有限公司 Pixel structure and display panel
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