CN110958030B - Method and device for preventing harmonic interference, and data processing method and device - Google Patents
Method and device for preventing harmonic interference, and data processing method and device Download PDFInfo
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- CN110958030B CN110958030B CN201911221648.0A CN201911221648A CN110958030B CN 110958030 B CN110958030 B CN 110958030B CN 201911221648 A CN201911221648 A CN 201911221648A CN 110958030 B CN110958030 B CN 110958030B
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Abstract
The present disclosure provides a method and apparatus for preventing harmonic interference, a data processing method and apparatus, including: the frequency conversion module sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end respectively, the instruction carries frequency conversion parameters, the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, sends the frequency division clock frequency after the frequency division processing to the digital front end, and combines the frequency conversion module and the baseband phase-locked loop to adjust the clock frequency of a clock source compared with the prior art, so that a new method for preventing harmonic interference is provided, and the diversity and the flexibility for preventing the harmonic interference are realized.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method and an apparatus for preventing harmonic interference, and a method and an apparatus for data processing.
Background
Communication based on the radio frequency module becomes a part of daily life, communication quality greatly affects the daily life of people, interference of harmonic waves of the digital clock to the radio frequency module is one of important factors affecting the communication quality, and therefore how to avoid the interference of the harmonic waves to the radio frequency module is a problem to be solved urgently.
In the prior art, the frequency of the digital clock source is usually modified to prevent the harmonic from interfering the rf module.
Disclosure of Invention
The present disclosure provides a method and an apparatus for preventing harmonic interference, and a data processing method and an apparatus for achieving diversity and flexibility of preventing harmonic interference.
In one aspect, an embodiment of the present disclosure provides a method for preventing harmonic interference, where the method includes:
the frequency conversion module respectively sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
and the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end.
In some embodiments, the method further comprises:
and the digital front end carries out sampling rate conversion on the frequency division clock frequency according to the frequency conversion parameters.
In some embodiments, the sample rate converting the divided clock frequency by the digital front end according to the conversion parameter comprises:
and performing gated clock processing on the frequency division clock frequency according to the frequency conversion parameter so as to send the clock frequency after the gated clock processing to the baseband physical layer.
In some embodiments, the target clock frequency is (m/n) the initial clock frequency, wherein m > n > 1.
In another aspect, an embodiment of the present disclosure further provides an apparatus for preventing harmonic interference, where the apparatus includes:
the frequency conversion module is used for respectively sending an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
and the baseband phase-locked loop is used for adjusting the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performing frequency division processing on the target clock frequency, and sending the frequency division clock frequency after the frequency division processing to the digital front end.
In some embodiments, the digital front end is configured to sample rate convert the divided clock frequency according to the conversion parameter.
In some embodiments, the digital front end is specifically configured to perform clock gating processing on the frequency-divided clock frequency according to the frequency conversion parameter, and send the clock frequency after the clock gating processing to the baseband physical layer.
In some embodiments, the target clock frequency is (m/n) the initial clock frequency, wherein m > n > 1.
On the other hand, the embodiment of the present disclosure further provides a data processing method, where the method includes:
the frequency conversion module respectively sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target frequency, performs frequency division processing on the target frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end;
the digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters and sends the clock frequency after gated clock processing to a baseband physical layer;
the digital front end responds to received data to be processed sent by a radio frequency module and transmits the data to be processed to the baseband physical layer;
and the baseband physical layer samples the data to be processed based on the clock frequency processed by the gating clock.
In another aspect, an embodiment of the present disclosure further provides a data processing apparatus, where the apparatus includes:
the frequency conversion module is used for respectively sending an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop is used for adjusting the initial clock frequency according to the frequency conversion parameters to obtain a target frequency, performing frequency division processing on the target frequency and sending the frequency division clock frequency after the frequency division processing to the digital front end;
the digital front end is used for performing gated clock processing according to the frequency division clock frequency and sending the clock frequency after the gated clock processing to the baseband physical layer;
the digital front end is further used for responding to the received data to be processed sent by the radio frequency module and transmitting the data to be processed to the baseband physical layer;
and the baseband physical layer is used for sampling the data to be processed based on the clock frequency processed by the gated clock.
The present disclosure provides a method and an apparatus for preventing harmonic interference, and a data processing method and an apparatus, including: the frequency conversion module sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end respectively, the instruction carries frequency conversion parameters, the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, sends the frequency division clock frequency after the frequency division processing to the digital front end, and combines the frequency conversion module and the baseband phase-locked loop to adjust the clock frequency of a clock source compared with the prior art, so that a new method for preventing harmonic interference is provided, and the diversity and the flexibility for preventing the harmonic interference are realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic view of an application scenario for preventing harmonic interference according to an embodiment of the disclosure;
FIG. 2 is a schematic flow chart illustrating a method for preventing harmonic interference according to an embodiment of the present disclosure;
FIG. 3 is a flow chart illustrating a method for preventing harmonic interference according to another embodiment of the disclosure;
FIG. 4 is a schematic diagram illustrating a method for preventing harmonic interference according to an embodiment of the disclosure;
FIG. 5 is a schematic diagram of an apparatus for preventing harmonic interference according to an embodiment of the disclosure;
FIG. 6 is a schematic flow chart diagram illustrating a data processing method according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a data processing apparatus according to an embodiment of the disclosure.
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The method for preventing harmonic interference provided by the embodiment of the disclosure can be applied to the scene shown in fig. 1.
In the application scenario shown in fig. 1, calling user 100 may initiate a call request to called user terminal 300 through calling user terminal 200.
When the called subscriber terminal 300 receives the call request initiated by the calling subscriber terminal 200, it performs an operation of vibration and/or ringing (which the called subscriber 400 previously set in the called subscriber terminal 300) so as to let the called subscriber 400 know that there is telephone access by means of vibration and/or ringing. The called subscriber 400 can listen to the call by clicking an "answer" key provided on the called subscriber terminal 300.
A Radio Frequency Integrated Circuit (RFIC) and a baseband module on the called ue 300 are disposed on the same SoC (system on chip), so as to avoid interference of the Radio Frequency module with harmonics of the digital clock as little as possible when the Radio Frequency module receives communication data sent by the calling ue 200, a Frequency conversion module (Radio Frequency Integrated Circuit) is added on the called ue 300, and when the Frequency conversion module works, the SoC of the called ue 300 is in a Frequency conversion mode.
In the frequency conversion mode, the frequency conversion module sends an instruction for starting the frequency conversion mode to a Baseband Phase Locked Loop (BBPLL), and sends an instruction for starting the frequency conversion mode to a Digital Front End (DFE), where the instruction carries a frequency conversion parameter.
And the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain the target clock frequency. The initial clock frequency is provided by the baseband phase-locked loop by the clock source XTAL in the called user terminal 300, and may be 26 MHz.
And the baseband phase-locked loop performs frequency division processing on the target clock frequency according to preset frequency division parameters and sends the frequency division clock frequency after the frequency division processing to the digital front end.
The digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters, and sends the processed clock frequency to a Port Physical Layer (PHY).
The radio frequency module of the called terminal 300 receives the communication data transmitted from the calling subscriber terminal 200 and transmits the received data to the digital front end.
The digital front end sends the received data to the baseband physical layer, and the baseband physical layer samples the received data based on the clock frequency processed by the gated clock, so that the called subscriber 400 can clearly hear the chat content initiated by the main subscriber 100 through the calling subscriber terminal 200.
It should be noted that the above application scenarios are only used for exemplary illustration, and are not to be understood as a limitation of the application scenarios of the method for preventing harmonic interference according to the embodiment of the present disclosure, and the method for preventing harmonic interference according to the embodiment of the present disclosure may also be applied to an automatic driving scenario, an unmanned aerial vehicle scenario, a radar scenario, and the like.
In addition, it should be noted that the calling party, the called party, the calling terminal and the called terminal in the above example are relative concepts, that is, when the calling party and the calling terminal in the above example receive a call request initiated by another user, they are the called party and the called terminal; similarly, the called user and the called terminal in the above example are the calling user and the calling terminal when initiating the call request for calling other users.
The following describes the technical solutions of the present disclosure and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present disclosure will be described below with reference to the accompanying drawings.
In one aspect, the embodiment of the present disclosure provides a method for preventing harmonic interference, which is suitable for the application scenario.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for preventing harmonic interference according to an embodiment of the disclosure.
As shown in fig. 2, the method includes:
s101: and the frequency conversion module sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end respectively, and the instruction carries frequency conversion parameters.
The main body for executing the method for preventing harmonic interference according to the embodiment of the present disclosure may be a device for preventing harmonic interference, and the device may be specifically a user terminal (including a calling user terminal and a called user terminal) as described in the above example.
In some embodiments, the main body performing the method for preventing harmonic interference of the embodiments of the present disclosure may also be an interphone, a computer, an iPad, a vehicle terminal, a radar system, and a server, etc.
Wherein, the step may specifically include: the frequency conversion module sends a frequency conversion mode starting instruction carrying frequency conversion parameters to the baseband phase-locked loop, and the frequency conversion module sends the frequency conversion mode starting instruction carrying the frequency conversion parameters to the digital front end.
Wherein, the frequency conversion parameter can be set based on the requirement.
S102: and the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end.
The initial clock frequency is provided by the clock source for the baseband phase-locked loop. In the prior art, in order to prevent harmonic interference, a method is generally adopted to adjust the frequency of a clock source, that is, to change the clock frequency provided by a clock source for a baseband phase-locked loop.
In some embodiments, the target clock frequency is (m/n) × the initial clock frequency, wherein m > n > 1. Namely, the frequency (namely the target clock frequency) of the baseband phase-locked loop in the frequency conversion mode is increased to m/n compared with the frequency (namely the initial clock frequency) of the baseband phase-locked loop in the common mode.
For example, in the case of LTE (Long Term Evolution), the clock frequency of the baseband phase-locked loop is changed from 122.88MHz to 122.88 x (m/n) MHz.
The frequency of the frequency division clock of the digital front end is also increased by (m-n)/n.
In order to make the solution of the embodiment of the present disclosure more clearly understood, the method is described in detail by taking the method as an example of being applied to an intercom, and the well-known prior art is not described again.
The interphone at least comprises a clock source, a baseband phase-locked loop and a digital front end, wherein the clock source provides clock frequency for the baseband phase-locked loop (for the known structures in the prior art and the connection relations among the structures, etc., the description is omitted here).
In the prior art, to avoid interference of a harmonic wave of a clock to a radio frequency module, a clock frequency of a clock source is adjusted, and the adjusted clock frequency is provided for a baseband phase-locked loop, and the baseband phase-locked loop divides a frequency of the received adjusted clock frequency and sends the divided frequency to a digital front end.
In the embodiment of the present disclosure, the clock frequency of the clock source is not modified, the clock frequency (that is, the initial clock frequency in the above example) is directly provided by the clock source to the baseband phase-locked loop, an instruction of starting the frequency conversion mode with the frequency conversion parameter is sent to the baseband phase-locked loop through the added frequency conversion module, the baseband phase-locked loop modifies the clock frequency (that is, the initial clock frequency in the above example) provided by the clock source according to the frequency conversion parameter, divides the modified clock frequency (that is, the target clock frequency in the above example), and sends the divided frequency (that is, the divided clock frequency in the above example) to the digital front end.
It should be noted that, in order to ensure that the sampling clock frequency of the baseband is not changed, i.e. the synchronization of the baseband timing is not affected, the embodiments of the present disclosure are optimized based on the above examples, and refer to the following examples specifically.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for preventing harmonic interference according to another embodiment of the present disclosure.
As shown in fig. 3, the method includes:
s201: and the frequency conversion module sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end respectively, and the instruction carries frequency conversion parameters.
S202: and the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end.
For the description of S201 and S202, reference may be made to the above example, which is not described herein again.
S203: and the digital front end performs sampling rate conversion on the frequency division clock frequency according to the frequency conversion parameters.
In the embodiment of the disclosure, the digital front end receives the frequency division clock frequency sent by the baseband phase-locked loop, and performs sampling conversion on the frequency division clock frequency, so that for the baseband physical layer, the clock frequency of data sampling in the frequency conversion mode is the same as the clock frequency of data sampling in the normal mode (i.e., in the non-frequency conversion mode), thereby achieving the technical effects that the sampling clock frequency of the baseband is not changed, and the timing synchronization of the baseband is not affected.
In some embodiments, S203 may comprise: and performing gated clock processing on the frequency division clock frequency according to the frequency conversion parameters so as to send the clock frequency after the gated clock processing to the baseband physical layer.
That is to say, the digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters, that is, performs clock mask processing, and sends the clock frequency subjected to the clock mask processing to the baseband physical layer, so that the baseband physical layer performs data sampling based on the clock frequency subjected to the clock mask processing, thereby achieving the technical effects that the sampling clock frequency of the baseband is not changed, and the timing synchronization of the baseband is not affected.
The principles of embodiments of the present disclosure are now exemplarily illustrated with reference to fig. 4.
The frequency conversion parameters n and m are 16 and 17, the Clock frequency (DFE _ CLK) of the digital front end is 61.44MHz, the Normal mode is Normal mode, and the frequency conversion mode is Clock-shift mode.
As shown in FIG. 4, the frequency of the baseband PLL in Normal mode (bblpp fcore in FIG. 4) is 614.4 MHz. And the frequency bbpll fcore of the baseband phase-locked loop in the frequency conversion mode Clock-shift mode is 652.8 MHz.
Wherein rx _ data _ real/imag (1.92MHz) refers to the frequency of data sampling, rx _ data _ valid (1.92MHz) refers to the sampling frequency of valid data, and phy _ clk _61M44(61.44MHz) and phy _ clk _30M72(30.72MHz) are the data sampling frequencies of the baseband physical layer, respectively.
In normal mode, the data transfer from digital front end to baseband phy or from baseband phy to digital front end is performed with a valid set of I/Q data driven by phy _ clk _61M44(61.44 MHz). To guarantee the clock frequency, valid has a significant width twice the front-end digital clock frequency.
In the frequency conversion mode, the front-end digital clock frequency is increased to 65.28M, and the front-end digital performs clock mask processing (see the dashed line and labeled part in the figure), to generate phy _ clk _61M44 and phy _ clk _30M72, where the valid high effective width may be increased to 3 front-end digital clock frequency cycles.
According to another aspect of the embodiments of the present disclosure, an apparatus for preventing harmonic interference is further provided in support of the implementation of the method for preventing harmonic interference.
Referring to fig. 5, fig. 5 is a schematic diagram of an apparatus for preventing harmonic interference according to an embodiment of the disclosure.
As shown in fig. 5, the apparatus includes:
the frequency conversion module 10 is configured to send an instruction for starting a frequency conversion mode to the baseband phase-locked loop 20 and the digital front end 30, where the instruction carries frequency conversion parameters;
the baseband phase-locked loop 20 is configured to adjust an initial clock frequency according to the frequency conversion parameter to obtain a target clock frequency, perform frequency division processing on the target clock frequency, and send the frequency-divided clock frequency after the frequency division processing to the digital front end 30.
In some embodiments, the digital front end 30 is configured to perform a sample rate conversion on the divided clock frequency according to the conversion parameter.
In some embodiments, the digital front end 30 is specifically configured to perform clock gating processing on the frequency-divided clock frequency according to the frequency conversion parameter, and send the clock frequency after the clock gating processing to the baseband physical layer.
In some embodiments, the target clock frequency is (m/n) the initial clock frequency, wherein m > n > 1.
According to another aspect of the embodiments of the present disclosure, a data processing method is also provided in the embodiments of the present disclosure.
Referring to fig. 6, fig. 6 is a schematic flow chart of a data processing method according to an embodiment of the disclosure.
As shown in fig. 6, the method includes:
s301: and the frequency conversion module respectively sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters.
S302: and the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target frequency, performs frequency division processing on the target frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end.
S303: and the digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters and sends the clock frequency after the gated clock processing to the baseband physical layer.
S304: and the digital front end responds to the received data to be processed sent by the radio frequency module and transmits the data to be processed to the baseband physical layer.
S305: and the baseband physical layer samples the data to be processed based on the clock frequency processed by the gating clock.
Similarly, the main body for executing the method for preventing harmonic interference of the embodiment of the present disclosure may be a device for preventing harmonic interference, and the device may be specifically a user terminal (including a calling user terminal and a called user terminal) as described in the above example.
In some embodiments, the main body performing the method for preventing harmonic interference of the embodiments of the present disclosure may also be an interphone, a computer, an iPad, a vehicle terminal, a radar system, and a server, etc.
For a clearer understanding of the scheme of the embodiment of the present disclosure, the method is described in detail by taking the method as an example of being applied to iPad, and the known prior art is not described again.
The iPad at least includes a clock source, a baseband phase-locked loop and a digital front end, and the clock source provides a clock frequency for the baseband phase-locked loop (for the known structures in the prior art and the connection relations among the structures, etc., which are not described herein again).
The iPad corresponding to the user A is a first iPad, the iPad corresponding to the user B is a second iPad, the user A logs in chat software (such as WeChat) on the first iPad, the user B logs in WeChat on the second iPad, the user A chats with the user B through the logged-in WeChat on the first iPad, and the chat statement is C.
And a clock source on the second iPad provides an initial clock frequency for the baseband phase-locked loop, and the frequency conversion module sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, wherein the instruction carries frequency conversion parameters.
And adjusting the initial clock frequency by the baseband phase-locked loop on the second iPad according to the frequency conversion parameters to obtain a target clock frequency, dividing the target clock frequency to obtain a frequency division clock frequency, and sending the frequency division clock frequency to the digital front end.
And the digital front end on the second iPad performs clock mask processing on the distributed clock frequency and sends the clock frequency subjected to the clock mask processing to the baseband physical layer.
And the radio frequency module on the second iPad receives the data to be processed corresponding to the statement C and sends the data to be processed to the digital front end.
And the digital front end on the second iPad sends the data to be processed to the baseband physical layer.
The baseband physical layer on the second iPad samples data to be processed based on the clock frequency after clock mask processing, thereby obtaining the chat content without harmonic interference (namely statement C)
In the same way, it is worth explaining that the above examples are only used for exemplary illustration, and are not to be construed as limiting the execution subject and application scenario of the data processing method of the embodiment of the present disclosure.
According to another aspect of the embodiments of the present disclosure, there is also provided a data processing apparatus for supporting implementation of the above data processing method,
referring to fig. 7, fig. 7 is a schematic diagram of a data processing apparatus according to an embodiment of the disclosure.
As shown in fig. 7, the apparatus includes:
the frequency conversion module 10 is configured to send an instruction for starting a frequency conversion mode to the baseband phase-locked loop 20 and the digital front end 30, where the instruction carries frequency conversion parameters;
the baseband phase-locked loop 20 is configured to adjust an initial clock frequency according to the frequency conversion parameter to obtain a target frequency, perform frequency division processing on the target frequency, and send the frequency-divided clock frequency after the frequency division processing to the digital front end 30;
the digital front end 30 is configured to perform gated clock processing according to the frequency-divided clock frequency, and send the clock frequency after gated clock processing to the baseband physical layer 40;
the digital front end 30 is further configured to, in response to receiving data to be processed sent by a radio frequency module, transmit the data to be processed to the baseband physical layer 40;
the baseband physical layer 40 is configured to sample the data to be processed based on the clock frequency processed by the gated clock.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present disclosure.
In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present disclosure may be substantially or partially contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should also be understood that, in the embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.
While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (6)
1. A method of preventing harmonic interference, the method comprising:
the frequency conversion module respectively sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performs frequency division processing on the target clock frequency, and sends the frequency-divided clock frequency after the frequency division processing to the digital front end;
and the digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters so as to send the clock frequency after the gated clock processing to a baseband physical layer.
2. The method of claim 1, wherein the target clock frequency is (m/n) the initial clock frequency, wherein m > n > 1.
3. An apparatus for preventing harmonic interference, the apparatus comprising:
the frequency conversion module is used for respectively sending an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop is used for adjusting the initial clock frequency according to the frequency conversion parameters to obtain a target clock frequency, performing frequency division processing on the target clock frequency and sending the frequency-divided clock frequency after the frequency division processing to the digital front end;
and the digital front end is used for performing gated clock processing on the frequency division clock frequency according to the frequency conversion parameters and transmitting the clock frequency after the gated clock processing to the baseband physical layer.
4. The apparatus of claim 3, wherein the target clock frequency is (m/n) the initial clock frequency, and wherein m > n > 1.
5. A method of data processing, the method comprising:
the frequency conversion module respectively sends an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop adjusts the initial clock frequency according to the frequency conversion parameters to obtain a target frequency, performs frequency division processing on the target frequency, and sends the frequency division clock frequency after the frequency division processing to the digital front end;
the digital front end performs gated clock processing on the frequency division clock frequency according to the frequency conversion parameters and sends the clock frequency after gated clock processing to a baseband physical layer;
the digital front end responds to received data to be processed sent by a radio frequency module and transmits the data to be processed to the baseband physical layer;
and the baseband physical layer samples the data to be processed based on the clock frequency processed by the gating clock.
6. A data processing apparatus, characterized in that the apparatus comprises:
the frequency conversion module is used for respectively sending an instruction for starting a frequency conversion mode to the baseband phase-locked loop and the digital front end, and the instruction carries frequency conversion parameters;
the baseband phase-locked loop is used for adjusting the initial clock frequency according to the frequency conversion parameters to obtain a target frequency, performing frequency division processing on the target frequency and sending the frequency division clock frequency after the frequency division processing to the digital front end;
the digital front end is used for performing gated clock processing according to the frequency division clock frequency and sending the clock frequency after the gated clock processing to the baseband physical layer;
the digital front end is further used for responding to the received data to be processed sent by the radio frequency module and transmitting the data to be processed to the baseband physical layer;
and the baseband physical layer is used for sampling the data to be processed based on the clock frequency processed by the gated clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911221648.0A CN110958030B (en) | 2019-12-03 | 2019-12-03 | Method and device for preventing harmonic interference, and data processing method and device |
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| CN201911221648.0A CN110958030B (en) | 2019-12-03 | 2019-12-03 | Method and device for preventing harmonic interference, and data processing method and device |
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| CN110958030A CN110958030A (en) | 2020-04-03 |
| CN110958030B true CN110958030B (en) | 2021-11-30 |
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| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
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| CN102243313A (en) * | 2011-04-25 | 2011-11-16 | 上海迦美信芯通讯技术有限公司 | Dual-channel radio frequency receiver and frequency planning method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
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