CN110956929A

CN110956929A - Pixel driving circuit, driving method thereof, array substrate and display device

Info

Publication number: CN110956929A
Application number: CN202010001856.6A
Authority: CN
Inventors: 朱升; 张正元; 袁粲; 随鹏
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2020-01-02
Filing date: 2020-01-02
Publication date: 2020-04-03

Abstract

The embodiment of the application provides a pixel driving circuit, a driving method thereof, an array substrate and a display device. The pixel driving circuit includes: the pixel comprises a plurality of pixel rows, a pixel column and a pixel array, wherein the pixel rows comprise a plurality of sub-pixel groups, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are respectively a first sub-pixel and a second sub-pixel; the multi-stage grid line group comprises a first grid line and a second grid line, and two sub-pixels of the same sub-pixel group are respectively and electrically connected with the first grid line and the second grid line; the two sub-pixels of the same pixel group share the same sensing line; and a plurality of data lines electrically connected to the respective sub-pixels. The embodiment of the application can greatly shorten the time of one-time full-screen compensation sensing, and is beneficial to realizing high-frequency display; meanwhile, the time for realizing one-time full-screen compensation sensing is greatly shortened, and each sub-pixel can be compensated in time, so that the service life of components in the pixel driving circuit is prolonged; it is also beneficial to improve the accuracy of the compensated sensing.

Description

Pixel driving circuit, driving method thereof, array substrate and display device

Technical Field

The application relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof, an array substrate and a display device.

Background

For a high-resolution display device, under high-frequency driving, the time of the blanking period is short, and in the blanking period of one frame of the display screen, compensation sensing can be performed on only one sub-pixel in each pixel in one pixel row, so that a long time is required for completing compensation sensing on the full screen.

The compensation sensing of the full screen requires a long time, which affects the quality of the display image on the one hand and also affects the service life of the components in the pixel driving circuit on the other hand.

Disclosure of Invention

The present application provides a pixel driving circuit, a driving method thereof, an array substrate and a display device, aiming at the disadvantages of the prior art, so as to solve the technical problem that the compensation sensing of the full screen requires a long time in the prior art.

In a first aspect, an embodiment of the present application provides a pixel driving circuit, including:

the pixel array comprises a plurality of pixel rows and a plurality of pixel units, wherein each pixel row comprises a plurality of sub-pixel groups, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are respectively a first sub-pixel and a second sub-pixel;

the multi-stage grid line group comprises a first grid line and a second grid line, and two sub-pixels of the same sub-pixel group are respectively and electrically connected with the first grid line and the second grid line;

a plurality of sensing lines, wherein two sub-pixels of the same pixel group share the same sensing line;

a plurality of data lines electrically connected to the respective sub-pixels.

Optionally, two of the sub-pixels of the same pixel group share one of the data lines.

Optionally, the pixel driving circuit further includes: and a plurality of first power lines, wherein a plurality of sub-pixel groups of the same pixel row share one first power line.

Optionally, in the same pixel row, each sub-pixel group and one sub-pixel in the adjacent sub-pixel group form one pixel; or in the same pixel row, two adjacent sub-pixel groups form one pixel.

Optionally, the sub-pixel comprises a switching transistor and a sensing transistor; the switch transistor in the first sub-pixel is electrically connected with a first gate line in a last level gate line group, and the gate of the sensing transistor in the first sub-pixel is electrically connected with a first gate line in a present level gate line group; the switch transistor in the second sub-pixel is electrically connected with the second gate line in the last level gate line group, and the gate of the sensing transistor in the second sub-pixel is electrically connected with the second gate line in the present level gate line group.

Optionally, the sub-pixel further comprises a driving transistor, a storage capacitor and a light emitting unit; a first pole of the switch transistor is electrically connected with the corresponding data line, and a second pole of the switch transistor is electrically connected with the grid electrode of the driving transistor; a first pole of the driving transistor is electrically connected with the corresponding first power line, a second pole of the driving transistor is electrically connected with the first pole of the light-emitting unit, and the second pole of the light-emitting unit is electrically connected with the second power line; a first pole of the sensing transistor is electrically connected with the corresponding sensing line, and a second pole of the sensing transistor is electrically connected with a second pole of the driving transistor; the first pole of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second pole of the storage capacitor is electrically connected with the second pole of the driving transistor.

In a second aspect, an embodiment of the present application provides an array substrate, which includes the pixel driving circuit described above.

In a third aspect, an embodiment of the present application provides a display device, which includes the array substrate described above.

In a fourth aspect, an embodiment of the present application provides a driving method for a pixel driving circuit, for driving the pixel driving circuit, where a time for each frame of a display frame includes a display period and a vanishing period, the driving method includes:

writing a reset signal and a corresponding data signal into each first sub-pixel of each pixel row in sequence in a display period of each frame of display picture, and writing a data signal corresponding to the reset signal into each first sub-pixel of each pixel row in sequence;

and in the shadow eliminating period of each frame of display picture, performing compensation sensing operation on each first sub-pixel or each second sub-pixel in the corresponding pixel row.

Optionally, in a display period of each frame of a display screen, sequentially writing a reset signal and a corresponding data signal to each first subpixel of each pixel row, and sequentially writing a data signal corresponding to the reset signal to each first subpixel of each pixel row, includes:

inputting an effective signal to a first gate line in two adjacent gate line groups, inputting a reset signal to each sensing line to reset each first sub-pixel in a corresponding pixel row, and inputting a corresponding data signal to each data line to write the data signal into the corresponding first sub-pixel;

inputting an active signal to a second gate line in two adjacent gate line groups, inputting a reset signal to each sensing line to reset each second sub-pixel in a corresponding pixel row, and inputting a corresponding data signal to each data line to write the data signal into the corresponding second sub-pixel.

Optionally, in a blanking period of each frame of the display screen, performing a compensation sensing operation on each first sub-pixel or each second sub-pixel in a corresponding pixel row, including:

a reset stage, resetting each first sub-pixel or each second sub-pixel in a corresponding pixel row;

in the sensing stage, each reset first sub-pixel or each reset second sub-pixel charges the corresponding sensing line;

and in the sampling stage, the potential of each sensing line is sampled to be used as compensation data of each first sub-pixel or each second sub-pixel of the corresponding pixel row.

The technical scheme provided by the embodiment of the application has the following beneficial technical effects:

according to the pixel driving circuit, the driving method thereof, the array substrate and the display device, compensation sensing of two sub-pixels electrically connected with the same sensing line at different time can be realized by controlling the gate signal, and compared with the prior art in which 3 or 4 sub-pixels in one pixel share the same sensing line, the time for realizing one-time full-screen compensation sensing is greatly shortened, which is beneficial to improving the quality of a display picture under high-frequency display; meanwhile, the time for realizing one-time full-screen compensation sensing is greatly shortened, and each sub-pixel can be compensated in time, so that the service life of components in the pixel driving circuit is prolonged; the first sub-pixel and the second sub-pixel in the same pixel group are controlled by different gate lines, so that the influence of one sub-pixel can be avoided when the compensation sensing operation is carried out on the other sub-pixel, and the accuracy of compensation sensing is improved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of time division of each frame of a display screen according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating a driving method of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 8 is a flowchart illustrating a step S1 of the driving method of the pixel driving circuit shown in fig. 7;

FIG. 9 is a timing diagram of the pixel driving circuit shown in FIG. 5 during a display period;

fig. 10 is a flowchart illustrating a step S2 of the driving method of the pixel driving circuit shown in fig. 7;

FIG. 11 is a timing diagram of the pixel driving circuit shown in FIG. 5 during an effect period;

fig. 12 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The inventor of the present application considers that, in a high-resolution OLED display device, a plurality of sub-pixels in one pixel generally share the same sensing line, and in high-frequency display, because the shadow eliminating period of the high-frequency OLED display device is short, in the shadow eliminating period of one frame, only one sub-pixel in each pixel in one pixel row can be subjected to compensation sensing, so that one compensation sensing on a full screen is long, and the influence on the picture quality is large.

In addition, since the sensing transistors of the sub-pixels in the same pixel are controlled by the same gate line in the prior art, when a compensation sensing operation is performed on one sub-pixel in the pixel, the sensing transistor of the sub-pixel in the pixel, which is not subjected to compensation sensing, is also in an on state, and if the sub-pixel which is not subjected to compensation sensing has a defect, some interference signals may be generated, so that the compensation sensing result is inaccurate.

The present application provides a pixel driving circuit, a driving method thereof, an array substrate and a display device, which are used to solve the above technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

The present embodiment provides a pixel driving circuit, as shown in fig. 1, the pixel driving circuit provided by the present embodiment includes a plurality of pixel rows 10, a multi-level gate line group G, a plurality of sensing lines SL, and a plurality of data lines DL.

The pixel row 10 includes a plurality of sub-pixel groups 101, and the sub-pixel group 101 includes two sub-pixels, which are a first sub-pixel SP1 and a second sub-pixel SP2, respectively.

The gate line group G includes a first gate line GL1 and a second gate line GL2, and two sub-pixels of the same sub-pixel group 101 are electrically connected to the first gate line GL1 and the second gate line GL2, respectively. Specifically, as shown in fig. 1, it may be that the first sub-pixel SP1 is electrically connected to the first gate line GL1, and the second sub-pixel SP2 is electrically connected to the second gate line GL 2.

Two sub-pixels of the same pixel group 101 share the same sensing line SL.

The data lines SL are electrically connected to the corresponding sub-pixels.

Specifically, the pixel driving circuit shown in fig. 1 is an M-1 to M +1 sub-pixel group 101 in an nth row and an N +1 row, and as shown in fig. 1, the first sub-pixel SP1 and the second sub-pixel SP2 in the mth sub-pixel group 101 in the nth row are both electrically connected to the sensing line SL < M >; the first sub-pixel SP1 in the mth group of sub-pixels 101 of the nth row is electrically connected to the first gate line GL1< N-1> in the nth-1 row and the first gate line GL1< N > in the nth row, and the second sub-pixel SP2 in the mth group of sub-pixels 101 of the nth row is electrically connected to the second gate line GL2< N-1> in the nth-1 row and the second gate line GL2< N > in the nth row.

Therefore, in the embodiment, compensation sensing of two sub-pixels electrically connected with the same sensing line SL at different times can be realized by controlling the gate signal, and compared with the prior art in which 3 or 4 sub-pixels in one pixel share the same sensing line, the time for realizing one-time full-screen compensation sensing is greatly shortened, which is beneficial to improving the quality of a display picture under high-frequency display; meanwhile, the time for realizing one-time full-screen compensation sensing is greatly shortened, and each sub-pixel can be compensated in time, so that the service life of components in the pixel driving circuit is prolonged; the first sub-pixel and the second sub-pixel in the same pixel group are controlled by different gate lines, so that the influence of one sub-pixel can be avoided when the compensation sensing operation is carried out on the other sub-pixel, and the accuracy of compensation sensing is improved.

Further, as shown in fig. 1, the present embodiment provides a pixel driving circuit in which two sub-pixels of the same sub-pixel group 101 share the same data line DL. Specifically, the first and second sub-pixels SP1 and SP2 in the nth row and mth sub-pixel group 101, for example, shown in fig. 1, are electrically connected to the mth data line DL < M >.

In the embodiment, the data signals can be written into the two sub-pixels electrically connected with the same data line DL at different times by controlling the gate signal, so that the number of the data lines DL can be reduced, and the resolution of the display device can be improved.

Optionally, as shown in fig. 2, the pixel driving circuit provided in this embodiment further includes a plurality of first power lines VDD, and a plurality of sub-pixel groups 101 in the same pixel row 10 share one first power line.

Specifically, as shown in fig. 2, 6 sub-pixels in the same pixel row 10, that is, 3 sub-pixel groups in the same pixel row 10 share the same first power line VDD, i.e., one for six. Generally, sub-pixels in the same pixel share one first power line VDD, and thus, when a sub-pixel in a display device includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, the first power line VDD may be one to six or one to twelve; when the sub-pixels in the display device include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, the first power line VDD may be one-to-four, one-to-eight, one-to-ten, or the like.

The number of sub-pixel groups 101 sharing the same first power line VDD in the same pixel row 10 is not limited in the present application, as long as the power supply performance of the first power line VDD is ensured to be good.

In this embodiment, the plurality of sub-pixel groups 101 in the same pixel row 10 share one first power line VDD, so that the number of the first power lines VDD can be reduced, and the resolution of the display device can be improved.

Optionally, in the pixel driving circuit provided in this embodiment, in the same pixel row 10, each sub-pixel group 101 and one sub-pixel in the adjacent sub-pixel group 101 form one pixel; or two adjacent sub-pixel groups 101 in the same pixel row 10 constitute one pixel.

Specifically, as shown in fig. 3, the sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, i.e., an RGB type display device. The sub-pixels in the same pixel row 10 are alternately arranged in the order of a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, wherein one red sub-pixel R, one green sub-pixel G and one blue sub-pixel B constitute one pixel. That is, in the same pixel row 10, each sub-pixel group 101 and one sub-pixel in the adjacent sub-pixel group 101 constitute one pixel.

Specifically, as shown in fig. 4, the sub-pixels include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, i.e., an RGBW type display device. The sub-pixels in the same pixel row 10 are alternately arranged in the order of a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, wherein one red sub-pixel R, one green sub-pixel G, one blue sub-pixel B, and one white sub-pixel W constitute one pixel. In the same pixel row 10, two adjacent sub-pixel groups 101 constitute one pixel.

Alternatively, as shown in fig. 5, the present embodiment provides a pixel driving circuit in which the sub-pixel includes a switching transistor Tsw and a sensing transistor Ts; the switching transistor Tsw in the first sub-pixel SP1 is electrically connected to the first gate line GL1 in the gate line group G of the previous stage, and the gate of the sensing transistor Ts in the first sub-pixel SP1 is electrically connected to the first gate line GL1 in the gate line group G of the current stage; the switching transistor Tsw in the second sub-pixel SP2 is electrically connected to the second gate line GL2 in the gate line group G of the previous stage, and the gate of the sensing transistor Ts in the second sub-pixel SP2 is electrically connected to the second gate line GL2 in the gate line group G of the present stage.

In the pixel driving circuit provided in this embodiment, the first gate line GL1 and the second gate line GL2 in the gate line group G can be shared by two adjacent pixel rows 10, so that the number of gate lines is not increased while the time-sharing compensation sensing and the time-sharing data writing for the two sub-pixels in the sub-pixel group 101 are implemented, which is beneficial to improving the resolution of the display device; in addition, when compensation sensing is performed on one sub-pixel in the same pixel group, the sensing transistor in the other sub-pixel is not turned on, so that the sub-pixel performing compensation sensing is not affected, and the accuracy of compensation sensing is improved.

Further, the present embodiment provides a pixel driving circuit based on 3T 1C. Specifically, as shown in fig. 5, the sub-pixel further includes a driving transistor Td, a storage capacitor C, and a light emitting unit EL; a first pole of the switching transistor Tsw is electrically connected to the corresponding data line DL, and a second pole of the switching transistor Tsw is electrically connected to the gate electrode of the driving transistor Td; a first pole of the driving transistor Td is electrically connected to the corresponding first power line VDD, a second pole of the driving transistor Td is electrically connected to a first pole of the light emitting unit EL, and a second pole of the light emitting unit EL is electrically connected to the second power line VSS; a first pole of the sensing transistor Ts is electrically connected to a corresponding sensing line SL, and a second pole of the sensing transistor Ts is electrically connected to a second pole of the driving transistor Td; a first pole of the storage capacitor C is electrically connected to the gate electrode of the driving transistor Td, and a second pole of the storage capacitor C is electrically connected to the second pole of the driving transistor Td.

It should be noted that, in the pixel driving circuit provided in this embodiment, the number of transistors and storage capacitors included in each sub-pixel may be adjusted.

The pixel driving circuit provided by the embodiment adopts the 3T1C pixel circuit, so that fewer components are used for driving each sub-pixel, the circuit is simpler, and the pixel driving circuit is particularly suitable for a high-resolution display device; and the pixel circuit of 3T1C can realize the threshold voltage compensation of the driving transistor, and has better display effect.

Based on the same inventive concept, the present embodiment provides a driving method of a pixel driving circuit, for driving the pixel driving circuit in the above embodiments. In the present embodiment, the time of each frame of display screen includes a display period and a vanishing period, and as shown in fig. 6, the time of the K-1 th frame of display screen, and the time of the K +1 th frame of display screen each include a display period and a vanishing period. As shown in fig. 7, the driving method of the pixel driving circuit provided in this embodiment includes:

s1: writing a reset signal and a corresponding data signal into each first sub-pixel of each pixel row in sequence in a display period of each frame of display picture, and writing the reset signal and the corresponding data signal into each first sub-pixel of each pixel row in sequence;

s2: and in the shadow eliminating period of each frame of display picture, performing compensation sensing operation on one sub-pixel in each sub-pixel group in the corresponding pixel row.

In the driving method of the pixel driving circuit provided in this embodiment, each sub-pixel is controlled to display in the display period of each frame of display image, and the compensation sensing operation is performed on each first sub-pixel or each second sub-pixel in the corresponding pixel row in the shadow elimination period of each frame of display image, so that the time for performing full-screen compensation sensing is greatly shortened, which is beneficial to improving the display effect, compared with the prior art in which each shadow elimination period can only perform the compensation sensing operation on one sub-pixel in each pixel (including 3 or 4 sub-pixels) in the corresponding pixel row; because the compensation sensing of the two sub-pixels in the same sub-pixel group is in the shadow eliminating period of the display picture of different frames, the compensation sensing of the two sub-pixels in the same sub-pixel group is not influenced mutually, and the measured compensation data is more accurate.

Alternatively, as shown in fig. 8, in the driving method provided in this embodiment, step S1 includes:

step S101: an active signal is input to the first gate line GL1 in the two adjacent gate line groups, and a reset signal is input to each sensing line SL to reset each first subpixel SP1 in the corresponding pixel row, and a corresponding data signal is input to each data line DL to write the data signal to the corresponding first subpixel SP 1.

Specifically, as shown in fig. 5 and 9, the display period includes a first stage T1, a second stage T2, and a third stage T3.

In the first phase T1, a high level is input to the first gate line GL1< N-1> and the first gate line GL1< N > in the nth-1 st and nth-stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each first sub-pixel SP1 in the nth pixel row are both turned on. The sensing transistor Ts is turned on, so that the reset signals Vref input by the sensing line SL < M-1> and the sensing line SL < M > are written into the second node s of each corresponding first sub-pixel SP1, so as to reset the potential of the second node s of each corresponding first sub-pixel SP 1; the switching transistor Tsw is turned on so that the data signal d1< N > < M-1> inputted from the data line DL < M-1> is written into the first node g of the first subpixel SP1 in the M-1 th subpixel group in the nth pixel row, so that the data signal d1< N > < M > inputted from the data line DL < M > is written into the first node g of the first subpixel SP1 in the mth subpixel group in the nth pixel row. That is, the data signal writing to each first subpixel SP1 in the nth pixel row and the potential resetting of the second node s are completed in the first stage T1.

In the second phase T2, a high level is input to the first gate line GL1< N > and the first gate line GL1< N +1> in the nth and N +1 th stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each first sub-pixel SP1 in the N +1 th pixel row are both turned on. Similarly to the first stage T1, in the second stage T2, the writing of the data signal to each of the first subpixels SP1 in the N +1 th pixel row and the resetting of the potential of the second node s are completed.

In the third stage T3, a high level is input to the first gate line GL1< N +1> and the first gate line GL1< N +2> in the (N + 1) -th and (N + 2) -th stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each first subpixel SP1 in the (N + 2) -th pixel row are both turned on. Similarly to the first stage T1, in the third stage T3, the writing of the data signal to each of the first subpixels SP1 in the N +2 th pixel row and the resetting of the potential of the second node s are completed.

It should be noted that the last-level gate line group corresponding to the nth pixel row is an N-1 th-level gate line group, the present-level gate line group corresponding to the nth pixel row is an nth-level gate line group, and N is an integer greater than or equal to 1. That is, the first-level gate signal line group is the 0 th level, that is, the last-level gate line group corresponding to the first pixel row is the 0 th-level gate line group, and the present-level gate line group corresponding to the first pixel row is the 1 st-level gate line group.

Step S102: an active signal is input to the second gate line GL2 in the two adjacent gate line groups, and a reset signal is input to each sensing line SL to reset each second subpixel SP2 in the corresponding pixel row, and a corresponding data signal is input to each data line DL to write the data signal to the corresponding second subpixel SP 2.

Specifically, as shown in fig. 5 and 9, the display period further includes a fourth stage T4, a fifth stage T5, and a sixth stage T6.

In the fourth stage T4, a high level is input to the second gate line GL2< N-1> and the second gate line GL2< N > in the nth-1 st and nth-stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each second sub-pixel SP2 in the nth pixel row are both turned on. The sensing transistor Ts is turned on, so that the reset signals Vref input by the sensing line SL < M-1> and the sensing line SL < M > are written into the second node s of each corresponding second sub-pixel SP2, so as to reset the potential of the second node s of each corresponding second sub-pixel SP 1; the switching transistor Tsw is turned on so that the data signal d2< N > < M-1> inputted from the data line DL < M-1> is written into the first node g of the second subpixel SP2 in the M-1 th subpixel group in the nth pixel row, so that the data signal d2< N > < M > inputted from the data line DL < M > is written into the first node g of the second subpixel SP2 in the mth subpixel group in the nth pixel row. That is, the writing of the data signal to each of the second subpixels SP2 in the nth pixel row and the resetting of the potential of the second node s are completed in the first stage T1.

In the fifth stage T5, a high level is input to the second gate line GL2< N > and the second gate line GL2< N +1> in the nth-stage and N + 1-stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each second subpixel SP2 in the N +1 th pixel row are both turned on. Similarly to the first stage T4, in the fifth stage T5, the writing of the data signal to each of the second subpixels SP2 in the N +1 th pixel row and the resetting of the potential of the second node s are completed.

In the sixth phase T6, a high level is input to the second gate line GL2< N +1> and the second gate line GL2< N +2> in the (N + 1) -th and (N + 2) -th stage gate line groups, so that the switching transistor Tsw and the sensing transistor Ts in each second subpixel SP2 in the (N + 2) -th pixel row are both turned on. Similarly to the fourth stage T4, in the sixth stage T6, the writing of the data signal to each of the second subpixels SP2 in the N +2 th pixel row and the resetting of the potential of the second node s are completed.

The light emitting unit EL emits light by a voltage difference between the gate (first node g) and the second electrode (second node s) of the driving transistor Td, and the light emitting current of the light emitting unit EL in each sub-pixel is:

"μ" in the above-listed formula is the mobility of carriers of the driving transistor Td, "W/L" is the width-to-length ratio of the channel of the driving transistor Td, V_dataData signal of the first node, V, written for the corresponding sub-pixel_refIs a reset signal, V, of the second node s of the driving transistor Td_thIs the threshold voltage of the driving transistor Td.

It should be noted that, in the driving method of the pixel driving circuit provided in the present application, after all the first gate lines GL1 are scanned, all the second gate lines GL2 may be scanned, or two adjacent first gate lines GL1 and two adjacent second gate lines GL2 may be scanned alternately.

The driving method in the display period for each frame of the display screen provided by the present embodiment realizes writing of the data signal to each of the first subpixel SP1 and each of the second subpixel SP2 and voltage resetting of the second node s, and the light emitting unit EL in each subpixel emits light under the driving of the driving transistor Td.

Alternatively, as shown in fig. 10, in the driving method provided in this embodiment, step S2 includes:

the reset phase ① resets each first sub-pixel SP1 or each second sub-pixel SP2 in the corresponding pixel row S201.

As shown in fig. 5 and 11, in the reset phase ① of the blanking period of the display screen of the K-th frame, the reset operation is performed on each first subpixel SP1 in the nth pixel row.

Specifically, a high level is input to the first gate line GL1< N-1> and the first gate line GL1< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each first sub-pixel SP1 in the nth pixel row; each data line DL, for example, the data line DL < M-1> and the data line DL < M >, inputs the reset signal Vref, so that the reset signal is written into the first node g of each first sub-pixel SP1 in the nth pixel row; each sensing line SL, for example, the sensing line SL < M-1> and the sensing line SL < M >, inputs the initialization signal Vini, so that the initialization signal Vini is written into the second node s of each first sub-pixel SP1 in the nth pixel row.

As shown in fig. 5 and 11, in the reset phase ① of the blanking period of the display screen of the (K + 1) th frame, the reset operation is performed on each of the second subpixels SP2 in the nth pixel row.

Specifically, a high level is input to the second gate line GL2< N-1> and the second gate line GL2< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each second subpixel SP2 in the nth pixel row; each data line DL, for example, the data line DL < M-1> and the data line DL < M >, inputs the reset signal Vref, so that the reset signal is written into the first node g of each second sub-pixel SP2 in the nth pixel row; each sensing line SL, for example, the sensing line SL < M-1> and the sensing line SL < M >, inputs the initialization signal Vini, so that the initialization signal Vini is written into the second node s of each second sub-pixel SP2 in the nth pixel row.

In the sensing stage ②, each reset first sub-pixel SP1 or second sub-pixel SP2 charges the corresponding sensing line SL at S202.

As shown in fig. 5 and 11, in the sensing phase ② of the blanking period of the display screen of the kth frame, each first subpixel SP1 in the nth pixel row charges the corresponding sensing line SL.

Specifically, a high level is still input to the first gate line GL1< N-1> and the first gate line GL1< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each first sub-pixel SP1 in the nth pixel row; reset signals Vref are input to the data lines DL (for example, data line DL < M-1> and data line DL < M >); the signal of each sensing line SL is floating, and the second node s charges each sensing line SL (for example, the sensing line SL < M-1> and the sensing line SL < M >) until the driving transistor Td is turned off.

As shown in fig. 5 and 11, in the sensing phase ② of the blanking period of the display screen of the (K + 1) th frame, each second subpixel SP2 in the nth pixel row charges the corresponding sensing line SL.

Specifically, a high level is still input to the second gate line GL2< N-1> and the second gate line GL2< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each second subpixel SP2 in the nth pixel row; reset signals Vref are input to the data lines DL (for example, data line DL < M-1> and data line DL < M >); the signal of each sensing line SL is floating, and the second node s of each second sub-pixel SP2 in the nth pixel row charges each sensing line (for example, the sensing line SL < M-1> and the sensing line SL < M >) until the driving transistor Td is turned off.

The sampling stage ③ samples the potential of each sensing line SL as the compensation data of each first sub-pixel SP1 or each second sub-pixel SP2 of the corresponding pixel row S203.

As shown in fig. 5 and 11, in the sampling phase ③ of the blanking period of the display screen of the K-th frame, the potential of each sensing line SL is sampled.

Specifically, a high level is still input to the first gate line GL1< N-1> and the first gate line GL1< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each first sub-pixel SP1 in the nth pixel row; reset signals Vref are input to the data lines DL (for example, data line DL < M-1> and data line DL < M >); the potential of the sensing line SL (e.g., the potentials of the sensing line SL < M-1> and the sensing line SL < M >) is sampled as compensation data of each first subpixel SP1 in the nth pixel row.

As shown in fig. 5 and 11, in the sampling phase ③ of the blanking period of the display screen of the K +1 th frame, the potential of each sensing line SL is sampled.

Specifically, a high level is still input to the second gate line GL2< N-1> and the second gate line GL2< N > to turn on the sensing transistor Ts and the switching transistor Tsw in each second subpixel SP2 in the nth pixel row; reset signals Vref are input to the data lines DL (for example, data line DL < M-1> and data line DL < M >); the potential of the sensing line SL (e.g., the potentials of the sensing line SL < M-1> and the sensing line SL < M >) is sampled as compensation data of each of the second subpixels SP2 in the nth pixel row.

The collected potential on each sensing line is the current potential Vs ' of the second node s in the corresponding sub-pixel, and since the driving transistor Td stops charging the sensing line when turned off, the current threshold voltage Vth ' of the driving transistor Td in the corresponding sub-pixel is the current voltage Vref of the first node g and the current potential Vs ' of the second node s, that is, Vth ' is equal to Vref-Vs '. Since the reset signal Vref is a known potential, the compensation data Vs ' is collected, so that the current threshold voltage Vth ' of the sub-pixel can be calculated to compensate the sub-pixel with the current threshold voltage Vth ' of the sub-pixel in the subsequent display process.

It should be noted that, although the timing chart shown in fig. 11 shows that two adjacent blanking periods respectively perform the sensing compensation operation on each first sub-pixel SP1 and each second sub-pixel SP2 in the same pixel row, this is merely an exemplary illustration, and the sensing compensation operation may be performed on each first sub-pixel SP1 in all pixel rows first, and then on each second sub-pixel SP2 in the pixel row.

The driving method of the pixel driving circuit in the blanking period provided by the embodiment can realize the compensation sensing operation on each first sub-pixel SP1 or each second sub-pixel SP2 in the corresponding pixel row, and because the compensation sensing operation is performed on only one sub-pixel in one sub-pixel group in one blanking period, the detection result is not influenced by another sub-pixel in the same sub-pixel group, and the detection result is more accurate.

Based on the same inventive concept, as shown in fig. 12, the array substrate provided in this embodiment includes the pixel driving circuit in the above embodiment, which has the beneficial effects of the pixel driving circuit in the above embodiment, and is not repeated herein.

Specifically, the array substrate further comprises a gate scanning circuit, a data line gating circuit and the like so as to control signal input of the pixel driving circuit.

Based on the same inventive concept, the present embodiment provides a display device, as shown in fig. 13, the display device provided in the present embodiment includes the array substrate in the above embodiments, and has the beneficial effects of the array substrate in the above embodiments, which are not repeated herein.

Specifically, the display device further comprises a power supply, a driving chip and the like, which respectively provide electric energy and driving signals for the operation of the pixel driving circuit.

Specifically, when the display device in this embodiment is a large-sized OLED display device, because the number of pixels in the large-sized OLED display device is large, the method has a significant advantage in shortening the time of the full-screen compensation sensing operation, and is also beneficial to improving the quality of the display image.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the description herein, particular features, structures, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A pixel driving circuit, comprising:

a plurality of data lines electrically connected to the respective sub-pixels.

2. The pixel driving circuit according to claim 1, wherein two of the sub-pixels of the same pixel group share one of the data lines.

3. The pixel driving circuit according to claim 1, further comprising:

and a plurality of first power lines, wherein a plurality of sub-pixel groups of the same pixel row share one first power line.

4. The pixel driving circuit according to any of claims 1-3, wherein each of the sub-pixel groups and one of the sub-pixels in an adjacent sub-pixel group in the same pixel row constitute one pixel; or

In the same pixel row, two adjacent sub-pixel groups form one pixel.

5. The pixel driving circuit according to claim 4,

the sub-pixel comprises a switching transistor and a sensing transistor;

the switch transistor in the first sub-pixel is electrically connected with a first gate line in a last level gate line group, and the gate of the sensing transistor in the first sub-pixel is electrically connected with a first gate line in a present level gate line group;

the switch transistor in the second sub-pixel is electrically connected with the second gate line in the last level gate line group, and the gate of the sensing transistor in the second sub-pixel is electrically connected with the second gate line in the present level gate line group.

6. The pixel driving circuit according to claim 5,

the sub-pixel further comprises a driving transistor, a storage capacitor and a light emitting unit;

a first pole of the switch transistor is electrically connected with the corresponding data line, and a second pole of the switch transistor is electrically connected with the grid electrode of the driving transistor;

a first pole of the driving transistor is electrically connected with the corresponding first power line, a second pole of the driving transistor is electrically connected with the first pole of the light-emitting unit, and the second pole of the light-emitting unit is electrically connected with the second power line;

a first pole of the sensing transistor is electrically connected with the corresponding sensing line, and a second pole of the sensing transistor is electrically connected with a second pole of the driving transistor;

the first pole of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second pole of the storage capacitor is electrically connected with the second pole of the driving transistor.

7. An array substrate comprising the pixel driving circuit according to any one of claims 1 to 6.

8. A display device comprising the array substrate according to claim 7.

9. A driving method of a pixel driving circuit for driving the pixel driving circuit according to any one of claims 1 to 6, wherein a time for displaying a picture per frame includes a display period and a blanking period, the driving method comprising:

10. The method of claim 9, wherein writing a reset signal and a corresponding data signal to the first sub-pixels of each pixel row in sequence, and writing a data signal corresponding to the reset signal to the first sub-pixels of each pixel row in sequence, in a display period of each frame of a display screen, comprises:

11. The driving method of the pixel driving circuit according to claim 9, wherein performing the compensation sensing operation on each of the first sub-pixels or the second sub-pixels in the corresponding pixel row in the blanking period of each frame of the display screen comprises: