CN110956051A - Test device and test method - Google Patents
Test device and test method Download PDFInfo
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- CN110956051A CN110956051A CN201811130301.0A CN201811130301A CN110956051A CN 110956051 A CN110956051 A CN 110956051A CN 201811130301 A CN201811130301 A CN 201811130301A CN 110956051 A CN110956051 A CN 110956051A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/14—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
- G06K7/1404—Methods for optical code recognition
- G06K7/1408—Methods for optical code recognition the method being specifically adapted for the type of code
- G06K7/1413—1D bar codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/14—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
- G06K7/1404—Methods for optical code recognition
- G06K7/1408—Methods for optical code recognition the method being specifically adapted for the type of code
- G06K7/1417—2D bar codes
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Abstract
The present disclosure relates to the field of testing technologies, and in particular, to a testing apparatus and a testing method. The device comprises: the integrated circuit testing device comprises a testing substrate, a testing module and a control module, wherein the testing substrate is used for placing an integrated circuit and testing the integrated circuit so as to obtain testing data of the integrated circuit; and the analysis lens is arranged opposite to the test substrate and used for scanning the identification code on the packaging body of the integrated circuit so as to enable the processor to analyze the identification code and judge the correctness of the identification code according to an analysis result and the test data. The method and the device reduce scanning time and improve scanning efficiency, thereby improving verification efficiency of the identification code and saving time cost and labor cost.
Description
Technical Field
The present disclosure relates to the field of testing technologies, and in particular, to a testing apparatus and a testing method.
Background
The production process of the integrated circuit comprises a chip production stage and a packaging stage, wherein the chip of the integrated circuit is packaged in the packaging stage, an identification code is printed on a packaging body to identify the chip, and finally the packaged chip is tested.
However, in an actual production process, there may be a phenomenon that the identification code on the package is printed erroneously due to carelessness of work. Therefore, in order to verify whether the identification code on the package is printed correctly, in the stage of testing the packaged chip, the identification code on the package is firstly scanned, various data of the chip in the chip production process, such as test data, manufactured data and the like, are obtained by analyzing the identification code, then the packaged chip is tested to obtain the test data of the packaged chip, and finally the test data of the packaged chip is compared with the test data of the chip in the chip production stage, if the comparison is successful, the identification code is correct, and if the comparison is unsuccessful, the identification code is incorrect.
At present, in the process of verifying the correctness of the identification code, the identification code on the packaging body is scanned in a manual mode, so that the problems of low identification code verification efficiency and high labor cost exist.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a testing apparatus and a testing method, so as to overcome the problems of low verification efficiency and high labor cost of an identification code caused by manually identifying the identification code at least to a certain extent.
According to an aspect of the present disclosure, there is provided a test apparatus including:
the integrated circuit testing device comprises a testing substrate, a testing module and a control module, wherein the testing substrate is used for placing an integrated circuit and testing the integrated circuit so as to obtain testing data of the integrated circuit;
and the analysis lens is arranged opposite to the test substrate and used for scanning the identification code on the packaging body of the integrated circuit so as to enable the processor to analyze the identification code and judge the correctness of the identification code according to an analysis result and the test data.
In an exemplary embodiment of the present disclosure, the test apparatus further includes:
and the mechanical arm is used for grabbing the integrated circuit and placing the integrated circuit on the test substrate.
In an exemplary embodiment of the present disclosure, the test substrate includes a test site capable of placing one of the integrated circuits; the test substrate is used for testing the integrated circuit at the test position to obtain test data of the integrated circuit at the test position.
In an exemplary embodiment of the present disclosure, the analysis lens is one and is disposed opposite to the test position.
In an exemplary embodiment of the present disclosure, the test substrate includes a plurality of test locations, each of the test locations is capable of placing one of the integrated circuits, and the test substrate is configured to simultaneously test the integrated circuits at each of the test locations to simultaneously obtain test data of the integrated circuits at each of the test locations.
In an exemplary embodiment of the disclosure, the number of the analysis lenses is the same as the number of the test positions, the analysis lenses correspond to the test positions one by one, and each analysis lens is arranged opposite to the corresponding test position.
In an exemplary embodiment of the present disclosure, the resolving lens is movable relative to the test substrate.
In an exemplary embodiment of the present disclosure, the apparatus further includes:
and the lens moving track is used for controlling the analysis lens to move in the lens moving track.
In an exemplary embodiment of the present disclosure, the analysis lens is detachably disposed in the lens moving track.
In an exemplary embodiment of the present disclosure, the identification code is generated from test data in a chip manufacturing process of the integrated circuit.
In an exemplary embodiment of the present disclosure, the identification code is a one-dimensional code or a two-dimensional code.
According to an aspect of the present disclosure, there is provided a test method applied to the test apparatus as described in any one of the above, including:
testing an integrated circuit placed in a test substrate through the test substrate to obtain test data of the integrated circuit;
and scanning the identification code on the packaging body of the integrated circuit placed on the test substrate through an analysis lens so as to enable a processor to analyze the identification code and judge the correctness of the identification code according to an analysis result and the test data.
The test device comprises a test substrate and an analytic lens, wherein the test substrate and the analytic lens are arranged oppositely, so that the analytic lens can scan identification codes placed on a packaging body of an integrated circuit on the test substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:
FIG. 1 shows a schematic structural diagram of a test apparatus in an exemplary embodiment;
FIG. 2 shows a flow diagram of a testing method in an exemplary embodiment.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
In the present exemplary embodiment, there is provided a test apparatus, as shown in fig. 1, the test apparatus may include: a test substrate 101 and an analysis lens 102, wherein:
the test substrate 101 is used for placing an integrated circuit and testing the integrated circuit to obtain test data of the integrated circuit;
and the analysis lens 102 is arranged opposite to the test substrate 101 and used for scanning the identification code on the packaging body of the integrated circuit so that the processor analyzes the identification code and judges the correctness of the identification code according to an analysis result and the test data.
The test device provided in this exemplary embodiment, by arranging the test substrate 101 and the analysis lens 102 relatively, the analysis lens 102 can scan the identification code placed on the package of the integrated circuit on the test substrate 101, compared with the prior art, a manual scanning mode is not adopted, thereby greatly reducing the scanning time, improving the scanning efficiency, improving the verification efficiency of the identification code, and saving the time cost and the labor cost.
Next, each part of the test apparatus in the present exemplary embodiment will be described in more detail with reference to fig. 1.
The test substrate 101 is used for placing an integrated circuit and testing the integrated circuit to obtain test data of the integrated circuit.
In the present exemplary embodiment, the test substrate 101 may be disposed on a main body of a test apparatus. The test substrate 101 may comprise at least one test site 103, each test site 103 being capable of holding an integrated circuit. In order to improve the testing efficiency, when the test substrate 101 includes a plurality of test locations 103, the test substrate 101 simultaneously tests the integrated circuits at the test locations 103 to obtain the test data of the integrated circuits at the test locations 103. The integrated circuit may be, for example, a dynamic random access memory integrated circuit, a static random access memory integrated circuit, and the like, which is not particularly limited in this exemplary embodiment.
And the analysis lens 102 is arranged opposite to the test substrate 101 and used for scanning the identification code on the packaging body of the integrated circuit so that the processor analyzes the identification code and judges the correctness of the identification code according to an analysis result and the test data.
In the present exemplary embodiment, a fixed position may be provided on the main body of the test apparatus, and the resolving lens 102 may be fixed at the fixed position. The analysis lens 102 may be detachably fixed at a fixed position to facilitate the detachment and maintenance of the analysis lens 102. It should be noted that the fixed position can be selected according to the condition of the relative arrangement of the analysis lens 102 and the test substrate 101. By arranging the analysis lens 102 opposite to the test substrate 101, the scanning range of the analysis lens 102 can cover the identification code on the package of the integrated circuit on the test substrate 101, thereby realizing automatic scanning of the identification code.
The analysis lens 102 is movable relative to the test substrate 101. For example, a lens moving track may be provided on the main body of the test apparatus, and the analysis lens 102 may be disposed in the lens moving track, such that the lens moving track controls the analysis lens 102 to move in the lens moving track. The analysis lens 102 may be detachably disposed in the lens moving track to facilitate detachment. For another example, a robot arm may be disposed on the testing apparatus, and the analysis lens 102 may be disposed on the robot arm, such that the analysis lens 102 may move along with the movement of the robot arm. In any way, the analysis lens 102 is controlled to move, and the analysis lens 102 is ensured to be arranged opposite to the test substrate 101, so that the analysis lens 102 can scan the identification code on the package of the integrated circuit in the test substrate 101. The above-described manner of moving the analysis lens 102 with respect to the test substrate 101 is merely exemplary, and is not intended to limit the present invention. It should be noted that although the analysis lens 102 is disposed opposite to the test substrate 101, when the integrated circuit on the test substrate 101 may not be within the scanning range of the analysis lens 102 or when a plurality of integrated circuits are placed on the test substrate 101, the analysis lens 102 may be controlled to move at this time, so as to scan the identification code on the package of the integrated circuit on the test substrate 101.
The identification code may be generated from test data during a chip manufacturing process of the integrated circuit. The identification code may also be generated from process data, equipment data, test data, and the like in the chip manufacturing process of the integrated circuit, which is not particularly limited in this exemplary embodiment.
The identification code may be a one-dimensional code or a two-dimensional code, which is not particularly limited in this exemplary embodiment. When the identification code of the integrated circuit is generated based on the test data in the chip manufacturing process, the identification code of the integrated circuit is associated with the test data in the chip manufacturing process of the integrated circuit and then stored in the analysis database. When the processor analyzes the identification code on the package of the integrated circuit scanned by the analysis lens 102, the identification code is matched with each identification code in the analysis database one by one, test data in a chip manufacturing process corresponding to the identification code successfully matched with the identification code in the analysis database is determined as test data in the chip manufacturing process of the identification code, the test data in the chip manufacturing process is compared with the test data tested by the test substrate 101, if the comparison is successful, the identification code on the package of the integrated circuit is correct, and if the comparison is unsuccessful, the identification code on the package of the integrated circuit is incorrect.
The test apparatus may further include: and a robot arm for grasping the integrated circuit and placing the integrated circuit on the test substrate 101. When the test substrate 101 comprises at least one test position 103, the robot arm may grab the integrated circuit and place the integrated circuit at each test position 103.
The number of the analysis lenses 102 is at least one, and specifically, may be set according to the number of the test positions 103 on the test substrate 101.
For example, when the test substrate 101 includes a test position 103, the test position 103 can place one of the integrated circuits, and the test substrate 101 is used to test the integrated circuit at the test position 103 to obtain test data of the integrated circuit at the test position 103, the number of the analysis lenses 102 may be one, and the analysis lenses 102 are disposed opposite to the test position 103, that is, the analysis lenses 102 are disposed right above the test position 103. Based on the above structure, while the test substrate 101 tests the integrated circuit at the test position 103, the analysis lens 102 can identify the identification code on the package of the integrated circuit. By arranging the analysis lens 102 and the test position 103 relatively, the test on the integrated circuit and the scanning on the identification code on the packaging body of the integrated circuit can be carried out simultaneously, so that the test and scanning time is greatly reduced, and the verification efficiency is improved.
For another example, when the test substrate 101 includes a plurality of test positions 103, each test position 103 can place one integrated circuit, and the test substrate 101 is configured to test the integrated circuits at each test position 103 at the same time, so as to obtain test data of the integrated circuits at each test position 103 at the same time, the number of the analysis lenses 102 may be the same as the number of the test positions 103, and the analysis lenses 102 correspond to the test positions 103 one by one, and each analysis lens 102 is disposed opposite to the corresponding test position 103. Based on the above structure, while the test substrate 103 simultaneously tests the integrated circuits at each test position 103, each analysis lens 102 can simultaneously scan the identification codes on the packages of the integrated circuits at the corresponding test position 103. By arranging the analysis lenses 102 with the same number as the test positions 103 and corresponding the analysis lenses 102 to the test positions 103 one by one, in the process of testing the integrated circuits at the test positions 103 by the test substrate 101, the analysis lenses 102 can scan the identification codes on the packaging bodies of the integrated circuits at the corresponding test positions 103, so that the test and scanning efficiency is greatly improved, and the verification efficiency of the identification codes is further improved.
For another example, when the test substrate 101 includes a plurality of test positions 103, each test position 103 can place one integrated circuit, and the test substrate 101 is used to simultaneously test the integrated circuits at each test position 103 so as to simultaneously obtain test data of the integrated circuits at each test position 103, the number of the analysis lenses 102 may be one. Based on the above structure, while the integrated circuits at the test positions 103 are simultaneously tested by the test substrate 101, the analysis lens 102 is controlled to move, so that the analysis lens 102 sequentially scans the identification codes on the packages of the integrated circuits at the test positions 103.
It should be noted that the number and the installation positions of the analysis lenses 102 are merely exemplary, and are not intended to limit the present invention.
In summary, the test substrate 101 and the analysis lens 102 are arranged oppositely, so that the analysis lens 102 can scan the identification code on the package of the integrated circuit placed on the test substrate 101, compared with the prior art, a manual scanning mode is not adopted, the scanning time is greatly reduced, the scanning efficiency is improved, the verification efficiency of the identification code is improved, and the time cost and the labor cost are saved.
In an exemplary embodiment of the present disclosure, as shown in fig. 2, there is also provided a testing method applied to the testing apparatus shown in fig. 1, the method may include the steps of:
step S210, testing an integrated circuit placed in a test substrate through the test substrate to obtain test data of the integrated circuit;
step S220, scanning the identification code on the package of the integrated circuit placed on the test substrate through the analysis lens, so that the processor analyzes the identification code and determines the correctness of the identification code according to the analysis result and the test data.
Since the specific details of the testing method have been described in the corresponding testing apparatus, the details are not described herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (12)
1. A test apparatus, comprising:
the integrated circuit testing device comprises a testing substrate, a testing module and a control module, wherein the testing substrate is used for placing an integrated circuit and testing the integrated circuit so as to obtain testing data of the integrated circuit;
and the analysis lens is arranged opposite to the test substrate and used for scanning the identification code on the packaging body of the integrated circuit so as to enable the processor to analyze the identification code and judge the correctness of the identification code according to an analysis result and the test data.
2. The testing device of claim 1, further comprising:
and the mechanical arm is used for grabbing the integrated circuit and placing the integrated circuit on the test substrate.
3. The test apparatus of claim 1, wherein the test substrate includes a test position, the test position being capable of placing one of the integrated circuits; the test substrate is used for testing the integrated circuit at the test position to obtain test data of the integrated circuit at the test position.
4. The testing device of claim 3, wherein the resolving lens is one and disposed opposite to the testing position.
5. The test apparatus as claimed in claim 1, wherein the test substrate comprises a plurality of test positions, each of the test positions being capable of holding one of the integrated circuits, the test substrate being configured to simultaneously test the integrated circuits at each of the test positions to simultaneously obtain test data of the integrated circuits at each of the test positions.
6. The testing device according to claim 5, wherein the number of the analysis lenses is the same as the number of the testing positions, the analysis lenses are in one-to-one correspondence with the testing positions, and each analysis lens is arranged opposite to the corresponding testing position.
7. The test apparatus of claim 1, wherein the resolving lens is movable relative to the test substrate.
8. The testing device of claim 7, wherein the device further comprises:
and the lens moving track is used for controlling the analysis lens to move in the lens moving track.
9. The testing device of claim 8, wherein the analysis lens is detachably disposed in the lens moving track.
10. The test apparatus as claimed in any one of claims 1 to 9, wherein the identification code is generated from test data in a chip manufacturing process of the integrated circuit.
11. The testing device of any one of claims 1 to 9, wherein the identification code is a one-dimensional code or a two-dimensional code.
12. A test method applied to the test apparatus as set forth in claim 1, comprising:
testing an integrated circuit placed in a test substrate through the test substrate to obtain test data of the integrated circuit;
and scanning the identification code on the packaging body of the integrated circuit placed on the test substrate through an analysis lens so as to enable a processor to analyze the identification code and judge the correctness of the identification code according to an analysis result and the test data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811130301.0A CN110956051A (en) | 2018-09-27 | 2018-09-27 | Test device and test method |
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| CN201811130301.0A CN110956051A (en) | 2018-09-27 | 2018-09-27 | Test device and test method |
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| CN110956051A true CN110956051A (en) | 2020-04-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111967546A (en) * | 2020-06-30 | 2020-11-20 | 广州超音速自动化科技股份有限公司 | Lithium battery test data binding method, device and storage medium |
| CN117452121A (en) * | 2023-10-30 | 2024-01-26 | 乐沪电子有限公司 | Method, device and computer storage medium for testing electronic product through code scanner |
-
2018
- 2018-09-27 CN CN201811130301.0A patent/CN110956051A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111967546A (en) * | 2020-06-30 | 2020-11-20 | 广州超音速自动化科技股份有限公司 | Lithium battery test data binding method, device and storage medium |
| CN117452121A (en) * | 2023-10-30 | 2024-01-26 | 乐沪电子有限公司 | Method, device and computer storage medium for testing electronic product through code scanner |
| CN117452121B (en) * | 2023-10-30 | 2024-05-24 | 乐沪电子有限公司 | Method, device and computer storage medium for testing electronic product through code scanner |
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