CN110956008A - Sub-threshold digital circuit time sequence optimization method and system - Google Patents
Sub-threshold digital circuit time sequence optimization method and system Download PDFInfo
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Abstract
The invention discloses a sub-threshold digital circuit time sequence optimization method and a system, wherein the method comprises the steps of firstly determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect; then, carrying out time sequence analysis on the given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units which can improve the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition to adjust so as to optimize the time sequence of the sub-threshold digital circuit through adjusting the size of the gate length. According to the invention, the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect, so that time sequence optimization is realized, the circuit performance of the sub-threshold digital circuit is improved, and the delay time of the unit is reduced; meanwhile, the consistency of the unit time delay is improved by utilizing the increase of the area, so that the robustness of the circuit is enhanced.
Description
Technical Field
The invention relates to the technical field of circuit timing optimization, in particular to a sub-threshold digital circuit timing optimization method and system.
Background
The sub-threshold digital circuit is a digital logic circuit with the working voltage lower than the threshold voltage of a transistor device, and the dynamic power consumption and the static power consumption of the circuit can be greatly reduced because the circuit works in a sub-threshold region. Just because the device works in the subthreshold region, the current and the voltage of the device have an exponential relationship, and the change of the size of the device can cause obvious current change and parasitic capacitance change, so that the electrical performance of the circuit is obviously changed. In addition, the circuit performance fluctuates greatly along with the deviation of the PVT (Process-Voltage-Temperature), in order to make the designed sub-threshold digital circuit have higher robustness, the design optimization Process of the sub-threshold digital circuit needs to consider the statistical analysis and optimization of the deviation of the PVT, which exponentially increases the complexity of the device size optimization of the sub-threshold digital circuit, so that the device optimization speed Process becomes very slow.
At present, with the increase of the scale of the sub-threshold digital circuit, the statistical analysis and optimization of the PVT deviation are combined with the traditional random optimization algorithm and the heuristic optimization algorithm, and the statistical analysis and optimization can not be directly applied to the optimization of the sub-threshold digital circuit with a larger scale, particularly the optimization of the sub-threshold digital time sequence circuit with the larger scale. In addition, in order to improve the performance of the sub-threshold digital circuit, the traditional method is to increase the ratio of the gate width to the gate length of an MOS device in the circuit, but increasing the gate width can significantly increase the area, which can cause the discretization of the cell height in the used standard cell library, and further cause the area waste; reducing the gate length of a unit working in a subthreshold region can possibly reduce the performance of the unit due to reverse short channel effect, and simultaneously can cause the performance distribution of the unit to be more flattened due to the reduction of the product of the gate width and the gate length, thereby reducing the robustness of the circuit design.
Disclosure of Invention
The invention provides a sub-threshold digital circuit time sequence optimization method and a sub-threshold digital circuit time sequence optimization system, wherein the reverse short channel effect is utilized to increase the gate length of a device of a main delay unit so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit and reduce the delay time of the unit; meanwhile, the consistency of the unit time delay is improved by utilizing the increase of the area, so that the robustness of the circuit is enhanced.
In order to achieve the purpose, the invention provides the following technical scheme:
a sub-threshold digital circuit timing optimization method comprises the following steps:
determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect;
performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet timing requirements, the signal paths comprising: a latch and its front-end combinational logic or a flip-flop and its front-end combinational logic;
determining a number of main delay units in each signal path that does not meet timing requirements that can improve performance using reverse short channel effects;
and increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition to adjust so as to optimize the time sequence of the sub-threshold digital circuit through adjusting the size of the gate length.
Further, the step of determining a logic cell circuit capable of improving performance by reverse short channel effect comprises:
acquiring a logic unit circuit in a used logic unit library or a logic unit circuit referred in a design to be optimized;
changing the gate length of an MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, and measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit under the corresponding gate length to obtain gate length-delay data;
checking the grid length-delay data to check whether a region with delay less than the delay of the original grid length exists in the region with the grid length greater than the original grid length;
if so, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit which can not improve the performance by utilizing the reverse short channel effect is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
Further, the method also comprises the following steps:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the time delay of the logic unit circuit, and a time delay-gate length relation lookup table of the logic unit circuit is established.
Further, the method also comprises the following steps:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulation of the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, the power consumption of the logic unit circuit under the delay is obtained at the same time, and a delay-power consumption relation lookup table of the logic unit circuit is established.
Further, the method also comprises the following steps:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length, namely the performance optimization coefficient of the logic unit circuit are obtained.
Further, the method also comprises the following steps:
and (3) for the design meeting the time sequence constraint, taking the grid length as an initial value, finely adjusting the grid length through an optimization algorithm, and estimating the power consumption of the logic unit circuit by using the grid length-power consumption relation lookup table on the premise of meeting a preset time sequence constraint condition to realize the optimization of the power consumption of the circuit.
Further, the step of performing timing analysis on the given integrated circuit to obtain all signal paths that do not meet the timing requirement includes:
performing time sequence analysis on the given integrated circuit by using a statistical time sequence analysis tool or based on circuit statistical simulation to obtain the delay distribution of all signal paths;
judging whether the delay distribution of each signal path meets the preset time sequence constraint condition or not;
and listing the signal paths which do not meet the preset time sequence constraint condition into the signal paths which do not meet the time sequence requirement.
Further, the step of determining a number of main delay cell circuits in each of the signal paths that do not meet timing requirements that can utilize reverse short channel effects to improve performance comprises:
if the logic unit circuit in the signal path which does not meet the time sequence requirement is a calibrated logic unit circuit which can improve the performance by using the reverse short channel effect, the logic unit circuit is listed into a main delay unit circuit which can improve the performance by using the reverse short channel effect;
if the latch or the trigger in the signal path which does not meet the timing requirement is a logic unit circuit which is calibrated and can improve the performance by using the reverse short channel effect, the latch or the trigger is listed in a main delay unit circuit which can improve the performance by using the reverse short channel effect.
A sub-threshold digital circuit timing optimization system, comprising:
a first determination unit for determining a logic cell circuit that can improve performance using a reverse short channel effect;
an analysis unit for performing timing analysis on a given integrated circuit to derive all signal paths that do not meet timing requirements, the signal paths comprising: the relay and the front end thereof are combined logically;
the second determining unit is used for determining a plurality of main delay units which can improve the performance by utilizing reverse short channel effect in each signal path which does not meet the timing requirement;
and the adjusting unit is used for adjusting the length of the gate of the device of the main delay unit to be increased by utilizing the reverse short channel effect according to a preset time sequence constraint condition so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the size of the gate length.
Further, the first determination unit includes:
the acquisition unit is used for acquiring the logic unit circuit in the used logic unit library or the logic unit circuit quoted in the design to be optimized;
the processing unit is used for changing the gate length of an MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit, acquiring the delay of the logic unit circuit under the corresponding gate length, and acquiring gate length-delay data;
the checking unit is used for checking the gate length-delay data and checking whether an area with delay less than the delay of the original gate length exists in the area with the gate length greater than the original gate length;
if so, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit which can not improve the performance by utilizing the reverse short channel effect is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
According to the technical scheme, compared with the prior art, the invention discloses a sub-threshold digital circuit time sequence optimization method and a sub-threshold digital circuit time sequence optimization system, the method comprises the steps of firstly determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect; then, carrying out time sequence analysis on the given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units which can improve the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition to adjust so as to optimize the time sequence of the sub-threshold digital circuit through adjusting the size of the gate length. According to the invention, the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect, so that time sequence optimization is realized, the circuit performance of the sub-threshold digital circuit is improved, and the delay time of the unit is reduced; meanwhile, the consistency of the unit time delay is improved by utilizing the increase of the area, so that the robustness of the circuit is enhanced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart of a method for optimizing the timing of a sub-threshold digital circuit according to an embodiment of the present invention;
fig. 2 is a flowchart of a specific implementation manner of step S101 according to an embodiment of the present invention;
fig. 3 is a flowchart of a specific implementation manner of step S102 according to an embodiment of the present invention;
fig. 4 is a structural diagram of a sub-threshold digital circuit timing optimization system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a method for optimizing a timing sequence of a sub-threshold digital circuit, where the method specifically includes the following steps:
and S101, determining a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect.
In an embodiment of the present invention, as shown in fig. 2, which is a specific implementation manner of the step S101, specifically, the step of determining a logic unit circuit capable of improving performance by using a reverse short channel effect includes:
s201, obtaining a logic unit circuit in the used logic unit library or a logic unit circuit quoted in the design to be optimized.
S202, changing the gate length of an MOS device in each logic unit circuit, simulating the logic unit circuit to obtain the input-output waveform of the logic unit circuit under the corresponding gate length, measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtaining gate length-delay data.
S203, checking the grid length-time delay data, checking whether an area with time delay smaller than the time delay of the original grid length exists in the area with the grid length larger than the original grid length, if so, executing a step S204, and if not, executing a step S205.
And S204, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
S205, the logic unit circuit is listed as the logic unit circuit which can not utilize the reverse short channel effect to improve the performance.
Further, after determining the logic cell circuit capable of improving the performance by using the reverse short channel effect, the method further includes:
for a logic unit circuit capable of improving performance by utilizing reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulation of the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and a delay-gate length relation lookup table of the logic unit circuit is established.
Further, after determining the logic cell circuit capable of improving the performance by using the reverse short channel effect, the method further includes:
for a logic unit circuit capable of improving performance by utilizing reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, an input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulation of the logic unit circuit, the time delay of the logic unit circuit is obtained by measuring the input-output waveform of the logic unit circuit, the power consumption of the logic unit circuit under the time delay is obtained, and a time delay-power consumption relation lookup table of the logic unit circuit is established.
Further, after determining the logic cell circuit capable of improving the performance by using the reverse short channel effect, the method further includes:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length, namely the performance optimization coefficient of the logic unit circuit are obtained.
Further, after determining the logic cell circuit capable of improving the performance by using the reverse short channel effect, the method further includes:
and establishing a statistical delay-gate length relation lookup table of the logic unit circuit based on the statistical simulation of the logic unit circuit.
Further, after determining the logic cell circuit capable of improving the performance by using the reverse short channel effect, the method further includes:
and (3) for the design meeting the time sequence constraint, taking the grid length as an initial value, finely adjusting the grid length through an optimization algorithm, and estimating the power consumption of the logic unit circuit by using the grid length-power consumption relation lookup table on the premise of meeting a preset time sequence constraint condition to realize the optimization of the power consumption of the circuit.
S102, carrying out time sequence analysis on the given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise: a latch and its front-end combinational logic or a flip-flop and its front-end combinational logic.
In an embodiment of the present invention, as shown in fig. 3, which is a specific implementation manner of the step S102, specifically, the step of performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirement includes:
s301, performing timing analysis on a given integrated circuit by using a statistical timing analysis tool or circuit-based statistical simulation to obtain delay distributions of all signal paths, where the signal paths include: a latch and its front-end combinational logic or a flip-flop and its front-end combinational logic.
S302, determining whether the delay profile of each signal path satisfies a predetermined timing constraint condition, if not, performing step S303, and if so, performing step S304.
And S303, listing the signal paths which do not meet the time sequence requirement into the signal paths which do not meet the time sequence requirement.
And S304, listing the signal paths corresponding to the preset time sequence constraint conditions into the signal paths meeting the time sequence requirements.
In the embodiment of the present invention, each latch and its front end combinational logic or flip-flop and its front end combinational logic need to satisfy a preset timing constraint condition, where the preset timing constraint condition specifically is:
tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max＜α.Tclock
tPrev_FF-Pdelay,min+tCML-Pdelay,min＞β.tFF-hold,max
wherein α is between (0, 1), β is between (1, ∞), tPrev_FF-Pdelay,maxOutputting the maximum value of the delay time for the preceding stage latch or the trigger; t is tCML-Pdelay,maxThe maximum value of the time for the output signal of the front-end combinational logic circuit to reach the latch or the trigger; t isclockThe clock signal period for the working of the sequential circuit is the reciprocal value of the clock signal frequency; t is tCML-Pdelay,minThe minimum value of the time for the output of the front-end combinational logic to reach the latch or the trigger; t is tPrev_FF-Pdelay,minOutputting the minimum value of delay time for the data of the preceding stage latch or the trigger; t is tFF-hold,maxA data input maximum hold time for a latch or flip-flop; t is tFF-setup,maxIs the maximum setup time for the data input of the latch or flip-flop.
S103, determining a plurality of main delay units which can improve the performance by utilizing the reverse short channel effect in each signal path which does not meet the timing requirement.
In an embodiment of the present invention, the step of determining a plurality of main delay unit circuits capable of improving performance by using a reverse short channel effect in each signal path not meeting the timing requirement includes:
if the logic unit circuit in the signal path which does not meet the time sequence requirement is the logic unit circuit which is calibrated to improve the performance by utilizing the reverse short channel effect, the logic unit circuit is listed into the main delay unit circuit which can improve the performance by utilizing the reverse short channel effect.
If the latch or the trigger in the signal path which does not meet the timing requirement is the logic unit circuit which is calibrated to improve the performance by utilizing the reverse short channel effect, the latch or the trigger is listed in the main delay unit circuit which can improve the performance by utilizing the reverse short channel effect.
Specifically, for each front-end combinational logic circuit and latch or flip-flop that do not meet the timing requirements, the result of determining the unit that can improve performance using reverse short channel effect using this step is used to check out the main delay unit in which performance can be improved using reverse short channel effect; if the logic unit in the front-end combined logic circuit which does not meet the time sequence requirement is the calibrated logic unit which can improve the performance by using the reverse short channel effect, the logic unit is listed into a main delay unit which can improve the performance by using the reverse short channel effect, otherwise, the logic unit is excluded from the unit to be optimized; the same is done for latches or flip-flop circuits.
And S104, increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition, and adjusting the time sequence of the sub-threshold digital circuit by adjusting the size of the gate length.
In the embodiment of the present invention, according to the requirement that each latch or flip-flop and the front-end combinational logic circuit must comply with the predetermined timing constraint condition, the predetermined timing constraint condition is:
tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max＜α.Tclock
tPrev_FF-Pdelay,min+tCML-Pdelay,min＞β.tFF-hold,max
wherein, TclockIs the clock signal period of the working of the sequential circuit, namely the reciprocal value of the clock signal frequency; t is tPrev_FF-Pdelay,maxOutputting the maximum value of the delay time for the preceding stage latch or the trigger; t is tCM-LPd,elayThe maximum value of the time for the output signal of the front ma end x combinational logic circuit to reach the latch or the trigger; t isclockThe clock signal period for the working of the sequential circuit is the reciprocal value of the clock signal frequency; t is tCML-Pdelay,minThe minimum value of the time for the output of the front-end combinational logic to reach the latch or the trigger; t is tPrev_FF-Pdelay,minFor data input of preceding-stage latch or flip-flopOutputting the minimum value of the delay time; t is tFF-hold,maxA data input maximum hold time for a latch or flip-flop; t is tFF-setup,maxIs the maximum setup time for the data input of the latch or flip-flop.
Furthermore, tCML-Pdelay,maxAnd tCML-Pdelay,minThe maximum delay time and the minimum delay time of each level of logic gate are respectively determined, and the method specifically comprises the following steps:
tCML-Pdelay,max＝∑tCell-Pdelay,max,i
tCML-Pdelay,min＝∑tCell-Pdelay,min,i
for the latch or the flip-flop which does not satisfy the above-mentioned predetermined timing constraint condition and the front-end combinational logic thereof, the delay spaces which still need to be improved are respectively positioned as follows:
tdelay_improve_goal1＝(tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max)-α.Tclock
tdelay_improve_goal2＝β.tFF-hold,max-(tPrev_FF-Pdelay,min+tCML-Pdelay,min)
in addition, considering that only the logic cell circuit which can utilize the reverse short channel effect is adjusted to optimize the delay performance of the front-end combinational logic circuit (the latch or the trigger is not adjusted or cannot be adjusted):
-∑ΔtRCSE_Cell-Pdelay,max,i≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay,min,i≥tdelay_improve_goal2
furthermore, considering the adjustment of the cells (including latches or flip-flops) that can take advantage of the reverse short channel effect to optimize the delay performance of the front-end combinational logic circuit:
-∑ΔtRCSE_Cell-Pdelay，max，i-ΔtPrev_FF-Pdelay，max-ΔtFF-setup，max≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay，min,i-ΔtFF-hold，max+ΔtPrev_FF-Pdelay，min≥tdelay_improve_goal2
wherein:
ΔtRCSE_Cell-Pdelay，max，i＝tRCSE_Cell-Pdelay，max，i，new-tRCSE_Cell-Pdelay，max，I，org
ΔtRCSE_Cell-Pdelay，min，i＝tRCSE_Cell-Pdelay，min，i，new-tRCSE_Cell-Pdelay，min，i，org
ΔtPrev_FF-Pdelay，max＝tPrev_FF-Pdelay，max，new-tPrev_FF-Pdelay，max，org
ΔtPrev_FF-Pdelay，min＝tPrev_FF-Pdelay,min,new-tPrev_FF-Pdelay,min,org
ΔtFF-setup，max＝tFF-setup，max，new-tFF-setup，max，org
ΔtFF-hold，max＝tFF-hold，max，new-tFF-hold，max，org
in particular, tRCSE_Cell-Pdelay,max,i,newAdjusting the maximum delay time after the gate length for a logic unit i capable of improving the delay performance by utilizing the reverse short channel effect; t is tRCSE_Cell-Pdelay,max,I,orgThe maximum delay time before the gate length (namely the original gate length) is adjusted for a logic unit i which can improve the delay performance by utilizing the reverse short channel effect; t is tRCSE_Cell-Pdelay,min,i,newAdjusting the minimum delay time after the gate length for a logic unit i capable of improving the delay performance by utilizing the reverse short channel effect; t is tRCSE_Cell-Pdelay,min,i,orgThe minimum delay time before the gate length (namely the original gate length) is adjusted for a logic unit i which can improve the delay performance by utilizing the reverse short channel effect; t is tPrev_FF-Pdelay,max,newThe maximum delay time after the gate length is adjusted for a preceding stage latch or a trigger which can improve the delay performance by utilizing the reverse short channel effect; t is tPrev_FF-Pdelay,max,orgThe maximum delay time before the gate length (namely the original gate length) is adjusted by a preceding stage latch or trigger which can improve the delay performance by utilizing the reverse short channel effect; t is tPrev_FF-Pdelay,min,newPreceding stage for improving delay performance by utilizing reverse short channel effectThe minimum delay time after the latch or flip-flop adjusts the gate length; t is tPrev_FF-Pdelay,min,orgThe minimum delay time before the grid length (namely the original grid length) is adjusted by a preceding stage latch or trigger which can improve the delay performance by utilizing the reverse short channel effect; t is tFF-setup,max,newThe maximum establishment time of the input data after the gate length is adjusted for the latch or the trigger which can improve the delay performance by utilizing the reverse short channel effect; t is tFF-setup,max,orgThe maximum establishment time of input data before the gate length (namely the original gate length) is adjusted for a latch or a trigger which can improve the delay performance by utilizing the reverse short-channel effect; t is tFF-hold,max,newAdjusting the maximum retention time of input data after the gate length for a latch or a trigger which can improve the delay performance by using the reverse short channel effect; t is tFF-hold,max,orgThe maximum retention time of input data before the gate length (namely the original gate length) is adjusted by a latch or a trigger capable of improving the delay performance by using the reverse short-channel effect.
For the inequality group:
-∑ΔtRCSE_Cell-Pdelay,max,i≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay，min，i≥tdelay_improve_goal2
or
-∑ΔtRCSE_Cell-Pdelay,max,i-ΔtFF-setup,max≥tdelay_improve_goal1+ΔtPrev_FF-Pdelay,max
∑ΔtRCSE_Cell-Pdelay,min,i-ΔtFF-hold,max≥tdelay_improve_goal2-ΔtPrev_FF-Pdelay,min
And solving to obtain: Δ t for each adjustable logic cell circuitRCSE_Cell-Pdelay,max,iMinimum value of (d); Δ t for each adjustable logic cellRCSE_Cell-Pdelay,min,iMaximum value of (d); Δ t per adjustable latch or flip-flopFF-setup,maxMaximum value of (d); Δ t per adjustable latch or flip-flopFF-hold,maxMaximum value of (d);
further according to the following four formulas:
tRCSE_Cell-Pdelay,max,i,new＝tRCSE_Cell-Pdelay,max,I,org+ΔtRCSE_Cell-Pdelay,max,i
tRCSE_Cell-Pdelay,min,i,new＝tRCSE_Cell-Pdelay,min,i,org+ΔtRCSE_Cell-Pdelay,min,i
tFF-setup,max,new＝tFF-setup,max,org+ΔtFF-setup,max
tFF-hold,max,new＝tFF-hold,max,org+ΔtFF-hold,max
the delay of the cell can be obtained for a new gate length: t is tRCSE_Cell-Pdelay,max,i,new；tRCSE_Cell-Pdelay,min,i,new；tFF-setup,max,newAnd tFF-hold,max,new。
Obtaining the adjusted grid length of the corresponding adjustable logic unit according to the established delay-grid length relation lookup table of the unit, and obtaining the delay t of the unit under the new grid lengthRCS_EC-ellP,dela,y,max、itRCSE_Cell-Pdelay,min,i,new、tFF-setup,max,newAnd tFF-hold,max,newThe corresponding front-end combinational logic circuit and the latch or trigger circuit can meet the time sequence requirement, so that the optimization of the time sequence through the adjustment of the gate length size is realized.
Further, the adjusted grid length is used as an initial value, the grid length is finely adjusted through an optimization algorithm, and the unit power consumption is estimated by using the established grid length-power consumption relation lookup table on the premise of meeting the preset time sequence constraint condition, so that the power consumption of the circuit is optimized.
Furthermore, based on the sequence of the signal paths, the gate length of the front-end combination logic circuit and the latch or trigger circuit combination is increased by utilizing the reverse short channel effect to the devices of the main delay unit, so that the circuit performance is improved, the delay time of the unit is reduced, the delay consistency of the unit is improved, the time sequence optimization is realized, and the delay consistency of the paths is improved.
The embodiment of the invention discloses a sub-threshold digital circuit time sequence optimization method, which comprises the steps of firstly determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect; then, carrying out time sequence analysis on the given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units which can improve the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition to adjust so as to optimize the time sequence of the sub-threshold digital circuit through adjusting the size of the gate length. According to the invention, the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect, so that time sequence optimization is realized, the circuit performance of the sub-threshold digital circuit is improved, and the delay time of the unit is reduced; meanwhile, the consistency of the unit time delay is improved by utilizing the increase of the area, so that the robustness of the circuit is enhanced.
Referring to fig. 4, based on the method for optimizing the timing sequence of the sub-threshold digital circuit disclosed in the foregoing embodiment, the present embodiment correspondingly discloses a system for optimizing the timing sequence of the sub-threshold digital circuit, which specifically includes: a first determining unit 401, an analyzing unit 402, a second determining unit 403, and an adjusting unit 404, wherein:
a first determination unit 401 for determining a logic cell circuit that can improve performance by using a reverse short channel effect;
an analyzing unit 402, configured to perform timing analysis on a given integrated circuit to obtain all signal paths that do not satisfy the timing requirement, where the signal paths include: the relay and the front end thereof are combined logically;
a second determining unit 403, configured to determine a plurality of main delay units in each signal path that does not meet the timing requirement, where the performance of the signal path can be improved by using reverse short channel effect;
the adjusting unit 404 is configured to adjust, by using an inverse short channel effect, a gate length of a device of the main delay unit to be increased according to a preset timing constraint condition, so as to optimize a timing sequence of the sub-threshold digital circuit by adjusting a size of the gate length.
Further, the first determining unit 401 specifically includes: an acquisition unit 4011, a processing unit 4012, and a checking unit 4013, wherein:
the obtaining unit 4011 is configured to obtain a logic unit circuit in the logic unit library or a logic unit circuit referred to in the design to be optimized;
the processing unit 4012 is configured to change a gate length of an MOS device in each logic unit circuit, obtain an input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit, and obtain a delay of the logic unit circuit under the corresponding gate length, to obtain gate length-delay data;
the checking unit 4013 is configured to check the gate length-delay data, and check whether an area with a delay smaller than the delay of the original gate length exists in an area with a gate length larger than the original gate length;
if so, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit which can not improve the performance by utilizing the reverse short channel effect is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
The embodiment of the invention discloses a sub-threshold digital circuit time sequence optimization system, which determines a logic unit circuit capable of improving performance by using a reverse short channel effect through a first determination unit; performing time sequence analysis on the given integrated circuit through an analysis unit to obtain all signal paths which do not meet the time sequence requirement; then, a second determining unit is used for determining a plurality of main delay units which can improve the performance by using a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, the adjusting unit adjusts the gate length of the device of the main delay unit by using the reverse short channel effect according to the preset time sequence constraint condition so as to optimize the time sequence of the sub-threshold digital circuit by adjusting the size of the gate length. According to the invention, the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect, so that time sequence optimization is realized, the circuit performance of the sub-threshold digital circuit is improved, and the delay time of the unit is reduced; meanwhile, the consistency of the unit time delay is improved by utilizing the increase of the area, so that the robustness of the circuit is enhanced.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A sub-threshold digital circuit timing optimization method, comprising:
determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect;
performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet timing requirements, the signal paths comprising: a latch and its front-end combinational logic or a flip-flop and its front-end combinational logic;
determining a number of main delay units in each signal path that does not meet timing requirements that can improve performance using reverse short channel effects;
and increasing the gate length of the device of the main delay unit by utilizing the reverse short channel effect according to a preset time sequence constraint condition to adjust so as to optimize the time sequence of the sub-threshold digital circuit through adjusting the size of the gate length.
2. The method of claim 1, wherein the step of determining a logic cell circuit that can improve performance using reverse short channel effects comprises:
acquiring a logic unit circuit in a used logic unit library or a logic unit circuit referred in a design to be optimized;
changing the gate length of an MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, and measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit under the corresponding gate length to obtain gate length-delay data;
checking the grid length-delay data to check whether a region with delay less than the delay of the original grid length exists in the region with the grid length greater than the original grid length;
if so, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit which can not improve the performance by utilizing the reverse short channel effect is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
3. The method of claim 2, further comprising:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the time delay of the logic unit circuit, and a time delay-gate length relation lookup table of the logic unit circuit is established.
4. The method of claim 2, further comprising:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the gate length of an MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained through simulation of the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, the power consumption of the logic unit circuit under the delay is obtained at the same time, and a delay-power consumption relation lookup table of the logic unit circuit is established.
5. The method of claim 2, further comprising:
for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length, namely the performance optimization coefficient of the logic unit circuit are obtained.
6. The method of claim 2, further comprising:
and (3) for the design meeting the time sequence constraint, taking the grid length as an initial value, finely adjusting the grid length through an optimization algorithm, and estimating the power consumption of the logic unit circuit by using the grid length-power consumption relation lookup table on the premise of meeting a preset time sequence constraint condition to realize the optimization of the power consumption of the circuit.
7. The method of claim 1, wherein the step of performing timing analysis on the given integrated circuit to derive all signal paths that do not meet timing requirements comprises:
performing time sequence analysis on the given integrated circuit by using a statistical time sequence analysis tool or based on circuit statistical simulation to obtain the delay distribution of all signal paths;
judging whether the delay distribution of each signal path meets the preset time sequence constraint condition or not;
and listing the signal paths which do not meet the preset time sequence constraint condition into the signal paths which do not meet the time sequence requirement.
8. The method of claim 1, wherein said step of determining a number of primary delay cell circuits in each of said signal paths not meeting timing requirements that can utilize reverse short channel effects to improve performance comprises:
if the logic unit circuit in the signal path which does not meet the time sequence requirement is a calibrated logic unit circuit which can improve the performance by using the reverse short channel effect, the logic unit circuit is listed into a main delay unit circuit which can improve the performance by using the reverse short channel effect;
if the latch or the trigger in the signal path which does not meet the timing requirement is a logic unit circuit which is calibrated and can improve the performance by using the reverse short channel effect, the latch or the trigger is listed in a main delay unit circuit which can improve the performance by using the reverse short channel effect.
9. A sub-threshold digital circuit timing optimization system, comprising:
a first determination unit for determining a logic cell circuit that can improve performance using a reverse short channel effect;
an analysis unit for performing timing analysis on a given integrated circuit to derive all signal paths that do not meet timing requirements, the signal paths comprising: the relay and the front end thereof are combined logically;
the second determining unit is used for determining a plurality of main delay units which can improve the performance by utilizing reverse short channel effect in each signal path which does not meet the timing requirement;
and the adjusting unit is used for adjusting the length of the gate of the device of the main delay unit to be increased by utilizing the reverse short channel effect according to a preset time sequence constraint condition so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the size of the gate length.
10. The system according to claim 9, wherein the first determination unit comprises:
the acquisition unit is used for acquiring the logic unit circuit in the used logic unit library or the logic unit circuit quoted in the design to be optimized;
the processing unit is used for changing the gate length of an MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit, acquiring the delay of the logic unit circuit under the corresponding gate length, and acquiring gate length-delay data;
the checking unit is used for checking the gate length-delay data and checking whether an area with delay less than the delay of the original gate length exists in the area with the gate length greater than the original gate length;
if so, the logic unit circuit is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit which can not improve the performance by utilizing the reverse short channel effect is listed as a logic unit circuit which can improve the performance by utilizing the reverse short channel effect.
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