CN114925636A - Characterization method of time sequence characteristics of combinational logic unit and storage medium - Google Patents
Characterization method of time sequence characteristics of combinational logic unit and storage medium Download PDFInfo
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Abstract
The invention discloses a method for representing time sequence characteristics of a full voltage domain combinational logic unit and a storage medium. The characterization method comprises the following steps: setting working environment and parameters of the combinational logic unit; selecting output load min, changing input conversion time, carrying out a small amount of Monte Carlo simulation, and establishing a relation model of delay standard deviation and input conversion time; selecting input conversion time of a step condition in a sub-threshold region or a super-threshold region, changing output load, and carrying out a small amount of Monte Carlo simulation to establish a corresponding relation model of delay standard deviation and output load; selecting input conversion time with the value as slow input in a subthreshold region or a super-threshold region, changing output load, and performing a small amount of Monte Carlo simulation to establish a relational model corresponding to the standard deviation of delay and the output load; and integrating all the obtained relation models to obtain a representation model of the full voltage domain time sequence characteristics. The invention has less simulation times and can quickly obtain the corresponding characterization parameters of the time sequence characteristics.
Description
Technical Field
The invention relates to the technical field of electronic design automation, in particular to a characterization method of time sequence characteristics of a combinational logic unit suitable for a full voltage domain.
Background
In the process of circuit operation, the delay generated by each unit is not constant and has a certain fluctuation, and the size of the fluctuation is usually measured by taking the standard deviation sigma as a timing statistic parameter. The method for searching phenotype time sequence analysis is always the core of an Electronic Design Automation (EDA) tool, and as process nodes are reduced, in order to calculate statistical delay more accurately, a series of methods are proposed in sequence: OCV (on-chip ripple), AOCV (advanced on-chip ripple), POCV (on-parameter-chip ripple), and LVF (library ripple format).
The OCV represents the influence of delay fluctuation on the unit and the path by multiplying a fixed coefficient on the basis of a unit delay time sequence library, and the coefficient is obtained by inverter chain simulation. The AOCV changes the fixed coefficients into coefficients that vary with the length of the series, which, while further reducing the error, increases the simulation overhead in acquiring the coefficients. POCV characterizes the cell at a fixed input transmission time and load, and gives a delay fluctuation sensitivity to characterize local fluctuations. This method is further improved in accuracy, but still causes a large error because the same unit has only one characteristic environment. The LVF establishes a lookup table format containing mean and variance based on the defects of the POCV and by combining the characteristics of the lookup table and taking input conversion time and output load as indexes. Compared with POCV, although LVF characterization time is increased along with the increase of the number of values of the lookup table, the precision is further improved due to the more detailed table.
The above methods are all based on a library, i.e. discrete PVTs and a look-up table consisting of input transmission times and output loads. Their advantages are that the extraction of the characterization parameters can be performed in advance, and the accuracy is higher, but the disadvantage is also obvious, it takes a lot of time to obtain the characterization parameters in the process of building the library, and under the condition of ensuring the accuracy, taking LVF library as an example, each unit needs to perform 7 × 7 monte carlo analyses under a specific PVT, so the simulation overhead required to be spent for different types of units with different driving strengths will be huge.
Therefore, it is an urgent technical problem in the art to provide a method for characterizing the timing characteristics of a circuit with low simulation overhead.
Disclosure of Invention
In order to solve the technical problem that the simulation cost for acquiring the circuit time sequence characteristics is high in the prior art, the invention provides a characterization method and a storage medium for the time sequence characteristics of a combinational logic unit.
The invention provides a method for representing the time sequence characteristics of a combinational logic unit, which comprises the following steps:
setting the working environment and working parameters of the combinational logic unit to be characterized;
selecting an output load under the working environment min Said output load min Establishing a relation model of a delay standard deviation and input conversion time for presetting a minimum load and changing the input conversion time, and obtaining the value of the input conversion time at a fast-slow input boundary by the relation model of the delay standard deviation and the input conversion time;
judging whether the combinational logic unit works in a subthreshold region or a super-threshold region;
under the working environment, selecting input conversion time with the value being a step condition in a sub-threshold region or a super-threshold region, changing output load, and establishing a relation model of the delay standard deviation and the output load under the condition of fast input in the sub-threshold region or the super-threshold region by carrying out Monte Carlo simulation for preset times;
under the working environment, selecting input conversion time taking the value as slow input in a sub-threshold region or a super-threshold region, changing output load, and establishing a relation model of delay standard deviation and output load under the slow input of the sub-threshold region or the super-threshold region by carrying out Monte Carlo simulation for preset times; the value of the input conversion time with the value of slow input is larger than the value of the input conversion time at the boundary of the fast input and the slow input;
and integrating all the obtained relation models of the subthreshold region or the super-threshold region to obtain a representation model of the time sequence characteristics of the combinational logic unit.
Further, the relation model of the delay standard deviation and the input conversion time and the value of the input conversion time at the fast and slow input boundary are obtained by the following steps:
selecting an output load min And carrying out Monte Carlo simulation for preset times to obtain a standard deviation sigma of time delay 0 ；
Randomly selecting two groups of input conversion time slew with values as slow input 1 、slew 2 Selecting an output load min Respectively carrying out Monte Carlo simulation of preset times to obtain two groups of input conversion time slews 1 、slew 2 Corresponding two delay standard deviations sigma 1 、σ 2 ；
With two sets of input conversion times slew 1 、slew 2 As an argument, with two standard deviations of delay σ 1 、σ 2 Is a dependent variable, and is subjected to two delay standard deviations sigma 1 、σ 2 Drawing a straight line L1 to obtain an expression of a straight line L1, and delaying the standard deviation sigma 0 Is substituted into the straight line L 1 Obtaining the value of the input conversion time at the fast and slow input boundary in the expression of (1);
output with input conversion time slew and output load min As a standard deviation of the delay of the index σ 0 (ii) a Output to input conversion time slew 1 And an output load min As a standard deviation of the delay of the index σ 1 (ii) a Output to input conversion time slew 2 And an output load min As a standard deviation of the delay of the index σ 2 And establishing a relation model of the delay standard deviation of the slow input and the input conversion time and the value of the input conversion time at the boundary of the fast input and the slow input through the output three groups of data.
Further, the establishing of the relationship model of the fast input lower delay standard deviation and the output load in the subthreshold region or the super-threshold region includes:
selecting the input conversion time slew and changing the output load a Said output load being loaded a Has a value range of [0.5 × maximum output load, maximum output load]Performing Monte Carlo simulation corresponding to preset times to obtain corresponding standard deviation sigma of time delay a ；
To output load min And an output load a As independent variable, with standard deviation of time delay σ 0 、σ a Is a dependent variable, and is subjected to two delay standard deviations sigma 0 、σ a Drawing a straight line L2 to obtain an expression of a straight line L2 and a slope k of the straight line L2 0 ；
Output with input conversion time slew and output load min As a standard deviation of the delay of the index σ 0 (ii) a Output with input conversion time slew and output load a As a standard deviation of the delay of the index σ a ；
And establishing a relation model of the fast input lower delay standard deviation and the output load in a subthreshold region or a super-threshold region through the two groups of output data.
Further, the establishing of the relationship model of the delay standard deviation and the output load under the slow input in the subthreshold region comprises:
randomly selecting an input switching time slew taking a value as a slow input b Obtaining an input conversion time slew based on an expression of the straight line L1 b And an output load min Corresponding standard deviation of delay
Standard deviation of said time delay
Substituting the expression into the straight line L2 to obtain the output load at the boundary of the large and small output loads
A value of (d);
and establishing a relation model of the delay standard deviation and the output load under the slow input of the sub-threshold region.
Further, the establishing of the relation model of the delay standard deviation and the output load under the slow input in the super-threshold region includes:
randomly selecting an input switching time slew taking a value as a slow input c ；
Obtaining an input conversion time slew based on an expression of the straight line L1 c And an output load min Corresponding standard deviation of delay
Selecting an input conversion time slew c Output load c Said output load c Has a value range of [0.5 × maximum output load, maximum output load]Performing Monte Carlo simulation corresponding to the preset times to obtain the standard deviation sigma of the delay c ；
To output load c Is an independent variable, with a standard deviation of time delay σ c With a slope k 0 Making a straight line L3;
will delay the standard deviation
Substituted into a straight line L3 to obtain the output load as an independent variable
The value of (1), the output load
As input switching time slew c A minimum load boundary of;
selecting input conversion time as slew c Output load d Said output load being loaded d Has a value range of [ output load ] min Output load
]Performing Monte Carlo simulation corresponding to the preset times to obtain the standard deviation sigma of the delay d ；
To output load min 、load d Is an independent variable, with a standard deviation of time delay sigma d Calculating the output load as independent variable at the intersection of the line L3 and the line L4 as a straight line L4
The value of (1), the output load
As input switching time slew c The maximum load boundary of (a);
calculating an input conversion time slew c Intermediate load boundary of
Through a straight line L 4 The expression of (a) yields the output load
Standard deviation of time delay of (2)
By a straight line L 3 The expression of (a) yields the output load
Standard deviation of time delay
A value of (d);
at input conversion time slew c Under the condition of (2) to output a load
As independent variable, with standard deviation of delay
As a dependent variable, with a standard deviation of the time delay
Make a straight line L 5 To obtain a straight line L 5 The expression of (1);
output to input conversion time slew c And an output load min As a standard deviation of the time delay of the index
Output to input conversion time slew c And an output load d As a standard deviation of the delay of the index σ d (ii) a Output to input conversion time slew c And an output load c As a standard deviation of the delay of the index σ c ；
Establishing input conversion time slew of super-threshold region through output data c A corresponding relation model of the standard deviation of the time delay and the output load;
selecting input conversion time slew at any slow input e Will input a conversion time slew e Into the straight line L 1 Obtaining an input conversion time slew e And an output load min Corresponding standard deviation of delay
At the output load as the output load min In case of calculating the input conversion time slew e And input conversion time slew c Is a difference value delta of the delay standard deviation of (1), is taken as a straight line L 3 L therein 3 `＝L 3 + Delta/2; making a straight line L 4 L therein 4 `＝L 4 +Δ；
Selecting an input switching time slew e Will delay the standard deviation
Is substituted into the expression of the straight line L3' to obtain the output load
As the value of the input switching time slew e A minimum load boundary of;
and calculates the output load at the intersection of the straight line L3' and the straight line L4
As the value of the input switching time slew e The maximum load boundary of (a);
selecting an input switching time slew e Intermediate load boundary
Through a straight line L 4 The expression obtains the output load
Standard deviation of time delay
By a straight line L 3 Expression of' obtains output load
Standard deviation of time delay
A value of (d);
selecting an input switching time slew e To output a load
As independent variable, with standard deviation of delay
As a dependent variable, with a standard deviation of the time delay
Making a straight line L 5 V, get a straight line L 5 The expression of the text;
and establishing a relation model of the super-threshold region, the delay standard deviation of the slow input condition and the output load.
Further, the operating parameter includes at least one of a type, a size, a temperature, a process corner, and an operating voltage of the combinational logic cell.
Further, the preset minimum output load is 0.1 fF.
Further, the preset times in the subthreshold region are more than or equal to 4.
Further, the preset times in the super-threshold region are greater than or equal to 6.
The computer-readable storage medium is used for storing a computer program, and when the computer program runs, the computer program performs the method for characterizing the time sequence characteristics of the full-voltage-domain combinational logic unit according to the above technical solution.
The invention obtains the relation model of the input conversion time, the output load and the delay standard deviation of the combined logic unit by adopting a small amount of Monte Carlo simulation under different conditions, thereby obtaining the relation model of the input conversion time, the output load and the delay standard deviation of the full-voltage-domain combined logic unit. Compared with the prior art, the invention has the following advantages:
1. the method has good applicability for acquiring timing sequence statistical parameters of different types of combinational logic units, and can still be applied under the conditions of different driving strengths, different voltages, different temperatures and different process angles;
2. according to the method, a relation model of the standard deviation sigma of the time delay, the input conversion time slew and the output load under the voltage node can be obtained only by 4 Monte Carlo simulations, so that the simulation overhead is effectively reduced, and the average error is less than 10%;
3. according to the invention, a relation model of the standard deviation sigma of the time delay under the voltage node, the input conversion time slew and the output load can be obtained only by 6 Monte Carlo simulations, so that the simulation overhead is effectively reduced, and the average error is less than 10%.
Drawings
The invention is described in detail below with reference to examples and figures, in which:
FIG. 1 is an overall flow chart of the present invention.
FIG. 2 is a flow chart of the present invention for modeling the relationship between the standard deviation of delay and the input conversion time.
FIG. 3 is a flow chart of the present invention for modeling the relationship between the standard deviation of delay and the output load under the fast input condition in the sub-threshold region.
FIG. 4 is a flow chart of the present invention for modeling the relationship between the standard deviation of delay and the output load under the condition of slow input in the subthreshold region.
FIG. 5 is a flow chart of the present invention for modeling the relationship between the standard deviation of delay and the output load for the fast input in the super-threshold region.
FIG. 6 is a flow chart of the present invention for modeling the relationship between the standard deviation of delay and the output load under the condition of slow input in the super-threshold region.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Thus, a feature indicated in this specification will serve to explain one of the features of one embodiment of the invention, and does not imply that every embodiment of the invention must have the stated feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.
The invention provides a method for representing the time sequence characteristics of a combinational logic unit, which mainly comprises the following steps.
And setting the working environment and working parameters of the combinational logic unit to be characterized. In one embodiment, the operating parameter includes at least one of a type, a size, a temperature, a process corner, and an operating voltage of the combinational logic cell.
Selecting output load under set working environment min Changing input conversion time, carrying out Monte Carlo simulation for preset times to establish a relation model of the delay standard deviation and the input conversion time, and obtaining the value of the input conversion time at the fast-slow input boundary by the relation model of the delay standard deviation and the input conversion time; output load of the invention min Is a preset minimum load.
Judging whether the combinational logic unit works in a subthreshold region or a super-threshold region;
if the sub-threshold-value-region-based fast input delay standard deviation modeling method works in the sub-threshold-value region, selecting input conversion time with a value of a step condition in the sub-threshold-value region under a set working environment, changing output load, and building a relation model of the fast input delay standard deviation and the output load in the sub-threshold-value region by carrying out Monte Carlo simulation for preset times; if the system works in the super-threshold area, selecting the input conversion time with the value being the step condition in the super-threshold area under the set working environment, changing the output load, and establishing a relation model of the delay standard deviation and the output load under the quick input of the super-threshold area by carrying out Monte Carlo simulation for a preset number of times.
Under the set working environment, selecting input conversion time with the value as slow input in a subthreshold region or a super-threshold region, changing output load, and establishing a relation model of the slow input lower delay standard deviation and the output load in the subthreshold region or the super-threshold region by carrying out Monte Carlo simulation for preset times; wherein the value of the input conversion time of the slow input is larger than the value of the input conversion time at the boundary of the fast input and the slow input;
and integrating all the obtained relation models of the subthreshold region or the super-threshold region to obtain a characterization model of the combinational logic unit time sequence characteristics, wherein the characterization model can be suitable for circuits of a full voltage domain.
The overall process of the present invention is further illustrated with reference to fig. 1.
Changing input conversion time slew, establishing a relation model of a delay standard deviation sigma and the input conversion time slew by carrying out a small amount of Monte Carlo simulation on a unit, and obtaining the input conversion time at a fast-slow input boundary by the relation model
104, the combinational logic unit works in a sub-threshold area, under the condition, the input conversion time is selected to be a step condition, namely, the slew is equal to 0ps, the output load is changed, and a relational model of the standard deviation sigma along with the output load under the condition of fast input is established by carrying out a small amount of Monte Carlo simulation on the unit;
and 108, integrating the voltage nodes required by the subthreshold region and the super-threshold region to obtain a rapid characterization model of the full-voltage domain time sequence statistical characteristics of the combinational logic unit under the selected environment, so as to rapidly obtain time sequence statistical parameters of the delay fluctuation with the input conversion time slew and the output load as indexes.
In one embodiment, the output load is selected under a set operating environment min And changing the input conversion time, and carrying out Monte Carlo simulation for preset times to establish a relation model of the standard deviation of the time delay and the input conversion timeObtaining the value of the input conversion time at the fast and slow input boundary by a relation model of the delay standard deviation and the input conversion time; output load of the invention min The step of setting the minimum load includes the following steps.
First selecting output load min And carrying out Monte Carlo simulation for preset times to obtain a standard deviation sigma of time delay 0 ；
Randomly selecting two groups of input conversion time slew with values as slow input 1 、slew 2 Selecting an output load min Respectively carrying out Monte Carlo simulation of preset times to obtain two groups of input conversion time slew 1 、slew 2 Corresponding two standard deviations of delay σ 1 、σ 2 ；
With two sets of input conversion times slew 1 、slew 2 As independent variable, with two delay standard deviations σ 1 、σ 2 Is a dependent variable, and is subjected to two delay standard deviations sigma 1 、σ 2 Drawing a straight line L1 to obtain an expression of a straight line L1, and delaying the standard deviation sigma 0 Is substituted into the straight line L 1 Obtaining the value of input conversion time at the fast and slow input boundary;
output with input conversion time slew and output load min Standard deviation of delay σ as index 0 (ii) a Output to input conversion time slew 1 And an output load min Standard deviation of delay σ as index 1 (ii) a Output to input conversion time slew 2 And an output load min As a standard deviation of the delay of the index σ 2 And establishing a relation model of the delay standard deviation of slow input and the input conversion time and the value of the input conversion time at the boundary of the fast input and the slow input through the output three groups of data.
The detailed flow of the relationship model between the delay standard deviation of the slow input and the input conversion time according to the present invention is described below with reference to fig. 2.
Step 201: under the selected working environment, the input conversion time is selected to be a step condition, namely, the slew is 0ps, and the input conversion time is outputLoad min Hspice simulations were performed at 0.1fF, where the Monte Carlo number is K, and the standard deviation of the delay σ was obtained for this case 0 In this step, the simulation overhead i is K;
The process of establishing the relation model of the delay standard deviation and the output load under the condition of fast input in the subthreshold region or the super-threshold region is the same, and the establishment of the relation model of the delay standard deviation and the output load under the condition of fast input in the subthreshold region or the super-threshold region specifically comprises the following steps.
Selecting input conversion time slew and changing output load a Output load a Has a value range of [0.5 × maximum output load, maximum output load]Carrying out Monte Carlo simulation corresponding to preset times to obtain corresponding delay standard deviation sigma a ；
To output load min And an output load a As independent variable, with standard deviation of time delay σ 0 、σ a As a dependent variable, two standard deviations of delay σ are passed 0 、σ a Drawing a straight line L2 to obtain an expression of a straight line L2 and a slope k of the straight line L2 0 ；
Output with input conversion time slew and output load min As a standard deviation of the delay of the index σ 0 (ii) a Output with input conversion time slew and output load a As a standard deviation of the delay of the index σ a ；
And establishing a relation model of the fast input lower delay standard deviation and the output load in a subthreshold region or a super-threshold region through the two groups of output data.
The following describes the relationship model between the standard deviation of the delay and the output load under the condition of full voltage domain fast input according to the present invention in further detail with reference to fig. 3 and 5.
As shown in fig. 3, the relationship model of the standard deviation of the delay and the output load under the condition of fast input in the sub-threshold region specifically includes the following steps.
301, under the selected working environment, selecting the input conversion time as a step condition, i.e. slew is 0ps, and selecting a group of larger output load loads a Wherein the load is output a The value of (A) can be selected from any value in the range of 0.5 × maximum output load-maximum output load to be used as hspice simulation, wherein the Monte Carlo times is K, and the corresponding time delay standard deviation sigma is obtained a In this step, the simulation overhead i is K;
As shown in fig. 5, the relationship model of the standard deviation of the delay and the output load under the condition of fast input in the super-threshold region specifically includes the following steps.
The method specifically comprises the following steps of establishing a relation model of the delay standard deviation and the output load under the condition of slow input in a subthreshold region.
Randomly selecting an input switching time slew taking a value as a slow input b Obtaining an input conversion time slew based on an expression of the straight line L1 b And an output load min Corresponding standard deviation of delay
Will delay the standard deviation
Substituting into the expression of the straight line L2 to obtain the output load at the boundary of the large and small output loads
A value of (d);
and establishing a relation model of the standard deviation of the delay under the slow input of the subthreshold region and the output load.
The detailed process of establishing the relationship model between the standard deviation of the delay and the output load under the slow input of the sub-threshold region according to the present invention is described below with reference to fig. 4.
The establishment of the relation model of the standard deviation of the time delay and the output load under the condition of establishing the slow input in the super-threshold region specifically comprises the following steps.
Randomly selecting an input switching time slew taking a value as a slow input c ；
Obtaining an input conversion time slew based on an expression of a straight line L1 c And an output load min Corresponding standard deviation of delay
Selecting an input conversion time slew c Output load c Output load c Has a value range of [0.5 × maximum output load, maximum output load]Performing Monte Carlo simulation corresponding to the preset times to obtain the standard deviation sigma of the delay c ；
To output load c Is an independent variable, with a standard deviation of time delay sigma c With a slope k 0 Making a straight line L3;
will delay the standard deviation
Substituted into a straight line L3 to obtain the output load as an independent variable
Value of (2), output load
As input switching time slew c A minimum load boundary of;
selecting an input conversion time as slew c Output load d Output load d Has a value range of [ output load ] min Output load
]Performing Monte Carlo simulation corresponding to the preset times to obtain the standard deviation sigma of the delay d ；
To output load min 、load d Is an independent variable, with a standard deviation of time delay σ d Calculating the output load as independent variable at the intersection of the line L3 and the line L4 as a straight line L4
Value of (2), output load
As input switching time slew c The maximum load boundary of (a);
calculating an input conversion time slew c Intermediate load boundary of
Through a straight line L 4 The expression of (a) yields the output load
Standard deviation of time delay of (2)
By a straight line L 3 The expression of (a) yields the output load
Standard deviation of time delay
A value of (d);
at the input switching time slew c Under the condition of (2) to output the load
As independent variable, with standard deviation of delay
As a dependent variable, with a standard deviation of the time delay
Making a straight line L 5 To obtain a straight line L 5 The expression of (2);
output to input conversion time slew c And an output load min As a standard deviation of the time delay of the index
Output to input conversion time slew c And an output load d As a standard deviation of the delay of the index σ d (ii) a Output to input conversion time slew c And an output load c As a standard deviation of the delay of the index σ c ；
Establishing input conversion time slew of super-threshold region through output data c A corresponding relation model of the standard deviation of the time delay and the output load;
selecting input conversion time slew at any slow input e Will input a conversion time slew e Substituted into a straight line L 1 Obtaining an input conversion time slew e And an output load min Corresponding standard deviation of delay
At the output load as the output load min In case, the input conversion time slew is calculated e And input conversion time slew c Is taken as a straight line L 3 L therein 3 `＝L 3 + Delta/2; making a straight line L 4 L therein 4 `＝L 4 +Δ；
Select input switching time slew e Will delay the standard deviation
Is substituted into the expression of the straight line L3' to obtain the output load
As the value of the input switching time slew e A minimum load boundary of;
and calculates the output load at the intersection of the straight line L3' and the straight line L4
As the value of the input switching time slew e The maximum load boundary of (a);
selecting an input switching time slew e Intermediate load boundary
Through a straight line L 4 "expression to obtain output load
Standard deviation of time delay
By a straight line L 3 Expression of' obtains the output load
Standard deviation of time delay
A value of (d);
selecting an input switching time slew e To output a load
As independent variable, with standard deviation of delay
As a dependent variable, with a standard deviation of time delay
Making a straight line L 5 V, get a straight line L 5 The expression of;
and establishing a relation model of the super-threshold region, the delay standard deviation of the slow input condition and the output load.
The following describes in detail specific steps of establishing a relation model of the super-threshold region, the delay standard deviation of the slow input condition and the output load with reference to fig. 6.
603, outputting the load under the selected working environment c As an argument, the standard deviation σ of the excess delay c The slope obtained in step 502 is taken as k 0 Straight line L of 3 To obtain a straight line L 3 The expression of (1);
611, under the selected working environment, inputting the conversion time slew under any slow input condition e (i.e., input transition time)
) Next, from the straight line L obtained in step 204 1 Substituting expressions into selected slew e The value of (1) can be obtained quickly that the input conversion time is slew e The output load is load min Standard deviation of lower delay
613, inputting the conversion time slew under the selected working environment e In the case of (2), the standard deviation will be delayed
Is substituted into the expression of the straight line L3' to obtain the independent variable
As the value of the input switching time slew e A corresponding minimum load boundary; and calculates the independent variable at the intersection of the straight line L3' and the straight line L4
As an input, the conversion time is slew e A corresponding maximum load boundary;
614, inputting the conversion time slew under the selected working environment e In the case of (2), making an intermediate load boundary
Wherein
Through a straight line L 4 The expression can be quickly obtained
Standard deviation of time delay
By a straight line L 3 The expression can be obtained quickly
Standard deviation of time delay
A value of (d);
The invention also protects a computer-readable storage medium for storing a computer program which, when running, performs the method for characterizing the time sequence characteristics of a full voltage domain combinational logic cell of the above-described solution.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A method for characterizing timing characteristics of a combinational logic cell, comprising:
setting a working environment and working parameters of a combinational logic unit to be characterized;
selecting an output load under the operating environment min Said output load min Setting a minimum load for presetting, changing input conversion time, carrying out Monte Carlo simulation for preset times, establishing a relation model of a delay standard deviation and the input conversion time, and obtaining a value of the input conversion time at a fast-slow input boundary by the relation model of the delay standard deviation and the input conversion time;
judging whether the combinational logic unit works in a subthreshold region or a super-threshold region;
under the working environment, selecting input conversion time with the value being a step condition in a sub-threshold region or a super-threshold region, changing output load, and establishing a relation model of the delay standard deviation and the output load under the condition of fast input in the sub-threshold region or the super-threshold region by carrying out Monte Carlo simulation for preset times;
under the working environment, selecting input conversion time with the value as slow input in a sub-threshold region or a super-threshold region, changing output load, and establishing a relation model of delay standard deviation and output load under the slow input of the sub-threshold region or the super-threshold region by carrying out Monte Carlo simulation for preset times; the value of the input conversion time with the value of slow input is larger than the value of the input conversion time at the boundary of the fast input and the slow input;
and integrating all the obtained relation models of the subthreshold region or the super-threshold region to obtain a representation model of the time sequence characteristics of the combinational logic unit.
2. Method for characterizing a timing characteristic of a combinational logic cell as defined in claim 1The method is characterized in that a relation model of the delay standard deviation and the input conversion time and the value of the input conversion time at the fast and slow input boundary are obtained through the following steps: selecting an output load min And carrying out Monte Carlo simulation of preset times to obtain the standard deviation sigma of the time delay 0 ；
Randomly selecting two groups of input conversion time slew with values as slow input 1 、slew 2 Selecting an output load min Respectively carrying out Monte Carlo simulation of preset times to obtain two groups of input conversion time slew 1 、slew 2 Corresponding two delay standard deviations sigma 1 、σ 2 ；
With two sets of input conversion times slew 1 、slew 2 As an argument, with two standard deviations of delay σ 1 、σ 2 Is a dependent variable, and is subjected to two delay standard deviations sigma 1 、σ 2 Drawing a straight line L1 to obtain an expression of a straight line L1, and delaying the standard deviation sigma 0 Is substituted into the straight line L 1 Obtaining the value of input conversion time at the fast and slow input boundary;
output with input conversion time slew and output load min As a standard deviation of the delay of the index σ 0 (ii) a Output to input conversion time slew 1 And an output load min Standard deviation of delay σ as index 1 (ii) a Output to input conversion time slew 2 And an output load min Standard deviation of delay σ as index 2 And establishing a relation model of the delay standard deviation of the slow input and the input conversion time and the value of the input conversion time at the boundary of the fast input and the slow input through the output three groups of data.
3. The method of characterizing timing characteristics of combinational logic cells according to claim 2, wherein said modeling fast input delay standard deviation versus output load in sub-threshold or super-threshold regions comprises:
selecting the input conversion time slew and changing the output load a Said input isLoad out a Is in the range of [0.5 × maximum output load, maximum output load]Carrying out Monte Carlo simulation corresponding to preset times to obtain corresponding delay standard deviation sigma a ；
To output a load min And an output load a As an independent variable, with a standard deviation of time delay σ 0 、σ a As a dependent variable, two standard deviations of delay σ are passed 0 、σ a Drawing a straight line L2 to obtain an expression of a straight line L2 and a slope k of the straight line L2 0 ；
Output with input conversion time slew and output load min As a standard deviation of the delay of the index σ 0 (ii) a Output with input conversion time slew and output load a Standard deviation of delay σ as index a ；
And establishing a relation model of the fast input lower delay standard deviation and the output load of the subthreshold region or the super-threshold region through the two groups of output data.
4. The method of characterizing timing characteristics of combinational logic cells according to claim 2, wherein said modeling delay standard deviation versus output load at slow input in sub-threshold region comprises:
randomly selecting an input switching time slew taking a value as a slow input b Obtaining an input conversion time slew based on an expression of the straight line L1 b And an output load min Corresponding standard deviation of delay
The standard deviation of the time delay
Substituting the expression into the straight line L2 to obtain the output load at the boundary of the large and small output loads
A value of (d);
and establishing a relation model of the delay standard deviation and the output load under the slow input of the sub-threshold region.
5. The method of characterizing timing characteristics of combinational logic cells according to claim 3, wherein said modeling delay standard deviation versus output load at slow inputs in the super-threshold region comprises:
randomly selecting an input switching time slew taking a value as a slow input c ；
Obtaining an input conversion time slew based on an expression of the straight line L1 c And an output load min Corresponding standard deviation of delay
Selecting an input conversion time slew c Output load c Said output load being loaded c Is in the range of [0.5 × maximum output load, maximum output load]Performing Monte Carlo simulation corresponding to preset times to obtain standard deviation sigma of delay c ；
To output load c Is an independent variable, with a standard deviation of time delay sigma c With a slope k 0 Making a straight line L3;
will delay the standard deviation
Substituted into a straight line L3 to obtain the output load as an independent variable
The value of (1), the output load
As input switching time slew c A minimum load boundary of;
selecting input conversion time as slew c Output load d Said output load being loaded d Has a value range of [ output load ] min Output load
]Performing Monte Carlo simulation corresponding to the preset times to obtain the standard deviation sigma of the delay d ；
To output a load min 、load d Is an independent variable, with a standard deviation of time delay σ d Calculating the output load as independent variable at the intersection of the line L3 and the line L4 as a straight line L4
Value of, the output load
As input switching time slew c The maximum load boundary of (a);
calculating an input conversion time slew c Intermediate load boundary of
Through a straight line L 4 The expression of (a) yields the output load
Standard deviation of time delay
By a straight line L 3 The expression of (a) yields the output load
Standard deviation of time delay
A value of (d);
at the input switching time slew c Under the condition of (2) to output a load
As independent variable, with standard deviation of delay
As a dependent variable, with a standard deviation of time delay
Making a straight line L 5 To obtain a straight line L 5 The expression of (1);
output to input conversion time slew c And an output load min Standard deviation of delay as index
Output to input conversion time slew c And an output load d As a standard deviation of the delay of the index σ d (ii) a Output to input conversion time slew c And an output load c As a standard deviation of the delay of the index σ c ；
Establishing input conversion time slew of super-threshold region through output data c A corresponding delay standard deviation and output load relation model;
selecting input conversion time slew at any slow input e Will input the conversion time slew e Into the straight line L 1 Obtaining an input conversion time slew e And an output load min Corresponding standard deviation of delay
At the output load as output load min In case of calculating the input conversion time slew e And input conversion time slew c Is a difference value delta of the delay standard deviation of (1), is taken as a straight line L 3 L therein 3 `＝L 3 + Delta/2; making a straight line L 4 L therein 4 `＝L 4 +Δ；
Selecting an input switching time slew e Will delay the standard deviation
Is substituted into the expression of the straight line L3' to obtain the output load
As the value of the input switching time slew e A minimum load boundary of;
and calculates the output load at the intersection of the line L3' and the line L4
As the value of the input switching time slew e The maximum load boundary of (a);
selecting an input switching time slew e Intermediate load boundary
Through a straight line L 4 "expression to obtain output load
Standard deviation of time delay
By a straight line L 3 Expression of' obtains output load
Standard deviation of time delay
A value of (d);
selecting an input switching time slew e To output a load
As an independent variable, toStandard deviation of time
As a dependent variable, with a standard deviation of the time delay
Making a straight line L 5 Obtaining a straight line L 5 The expression of the text;
and establishing a relation model of the super-threshold region, the delay standard deviation of the slow input condition and the output load.
6. A method of characterizing timing characteristics of combinational logic cells according to any of claims 1-5, characterized in that said operational parameters comprise at least one of the type, size, temperature, process corner and operational voltage of combinational logic cells.
7. A method for characterizing the timing characteristics of a combinational logic cell according to any of claims 1 through 5, wherein the predetermined minimum output load is 0.1 fF.
8. The method of characterizing timing characteristics of combinational logic cells according to claim 1, wherein the number of monte carlo simulations performed in the sub-threshold region is at least 4 x the predetermined number.
9. The method of characterizing temporal characteristics of a combinational logic cell according to claim 1, wherein the number of monte carlo simulations performed in the above-threshold region is at least 6 x the predetermined number.
10. A computer-readable storage medium for storing a computer program, wherein the computer program when executed performs a method of characterizing a timing characteristic of a combinational logic cell as defined in any one of claims 1 to 7.
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| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN117150994A (en) * | 2023-10-30 | 2023-12-01 | 北京云枢创新软件技术有限公司 | Analysis method of signal assignment delay, electronic equipment and storage medium |
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| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN117150994A (en) * | 2023-10-30 | 2023-12-01 | 北京云枢创新软件技术有限公司 | Analysis method of signal assignment delay, electronic equipment and storage medium |
| CN117150994B (en) * | 2023-10-30 | 2024-01-23 | 北京云枢创新软件技术有限公司 | Analysis method of signal assignment delay, electronic equipment and storage medium |
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