CN110943072A - Inductance structure - Google Patents
Inductance structure Download PDFInfo
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- CN110943072A CN110943072A CN201811107158.3A CN201811107158A CN110943072A CN 110943072 A CN110943072 A CN 110943072A CN 201811107158 A CN201811107158 A CN 201811107158A CN 110943072 A CN110943072 A CN 110943072A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
Abstract
The invention provides an inductance structure, comprising: a substrate; a first dielectric layer formed on the substrate; a first metal layer formed in the first dielectric layer; a second dielectric layer formed on the first dielectric layer; a second metal layer formed in the second dielectric layer; at least one intermediate dielectric layer formed between the first dielectric layer and the second dielectric layer; at least one intermediate metal layer formed in the at least one intermediate dielectric layer; and a plurality of through holes connecting the first metal layer and the at least one intermediate metal layer, and connecting the second metal layer and the at least one intermediate metal layer, wherein the first metal layer, the through holes, the at least one intermediate metal layer, the through holes, the second metal layer, the through holes, and the at least one intermediate metal layer form an extension path, and the extension path extends in a spiral manner with the first metal layer as an extension starting point. The inductance structure provided by the invention has large line width and low occupied area.
Description
Technical Field
The present invention relates to an inductor structure, and more particularly, to a vertical inductor structure with a large line width and a small footprint.
Background
For the current planar inductor, when the required inductance value is higher, the number of induction turns of the device is larger, the occupied area on the chip is larger, and in order to avoid the additional effect between the inductor (inductor) and other devices, the lower part of the inductor is designed to be a clearance area, i.e. no device or metal layer is placed, and the clearance area is required within a certain distance around the inductor. However, the above limitations have resulted in a chip that is relatively inefficient in terms of area usage.
The current planar inductor uses a single metal layer, and the lower metal layer is used as a connecting wire with other components, which is limited by the process factor, and the design thereof should meet the requirement of minimum spacing (min spacing), and it is desired to arrange a metal wire with a larger line width and increase the number of turns of the inductor in order to increase the inductance. However, the process and design requirements are still difficult to overcome in terms of chip area usage.
Therefore, it is desirable to develop an inductor structure with a large line width and a low footprint.
Disclosure of Invention
The invention provides an inductor structure, which aims to solve the problems of small line width and large occupied area of the existing inductor structure.
According to an embodiment of the present invention, an inductor structure is provided. This inductance structure includes: a substrate; a first dielectric layer formed on the substrate; a first metal layer formed in the first dielectric layer; a second dielectric layer formed on the first dielectric layer; a second metal layer formed in the second dielectric layer, wherein the first metal layer and the second metal layer are continuous metal layers; at least one intermediate dielectric layer formed between the first dielectric layer and the second dielectric layer; at least one intermediate metal layer formed in the at least one intermediate dielectric layer, wherein the at least one intermediate metal layer is a patterned metal layer; and a plurality of via holes (via) connecting the first metal layer and the at least one intermediate metal layer, and connecting the second metal layer and the at least one intermediate metal layer, wherein the first metal layer, the via holes, the at least one intermediate metal layer, the via holes, the second metal layer, the via holes, and the at least one intermediate metal layer form an extension path, and the extension path extends in a counterclockwise spiral manner with the first metal layer as an extension starting point.
According to some embodiments, the lengths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 1um and 100 um.
According to some embodiments, the thicknesses of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 0.01um and 4 um.
According to some embodiments, the widths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 0.01um and 100 um.
According to some embodiments, the pitch of the patterned metal layer of the at least one intermediate metal layer is between 0.01um and 10 um.
According to some embodiments, the at least one middle dielectric layer is a single middle dielectric layer, and the at least one middle metal layer is a single middle metal layer.
According to some embodiments, the at least one middle dielectric layer is a dual-layer middle dielectric layer, and the at least one middle metal layer is a dual-layer middle metal layer. According to some embodiments, the semiconductor device further includes a plurality of vias connecting the intermediate metal layers of different layers.
According to some embodiments, the at least one middle dielectric layer is a three-layer middle dielectric layer, and the at least one middle metal layer is a three-layer middle metal layer. According to some embodiments, the semiconductor device further includes a plurality of vias connecting the intermediate metal layers of different layers.
According to an embodiment of the present invention, an inductor structure is provided. This inductance structure includes: a substrate; a first dielectric layer formed on the substrate; a first metal layer formed in the first dielectric layer; a second dielectric layer formed on the first dielectric layer; a second metal layer formed in the second dielectric layer, wherein the first metal layer and the second metal layer are continuous metal layers; at least one intermediate dielectric layer formed between the first dielectric layer and the second dielectric layer; at least one intermediate metal layer formed in the at least one intermediate dielectric layer, wherein the at least one intermediate metal layer is a patterned metal layer; and a plurality of through holes connecting the first metal layer and the at least one intermediate metal layer, and connecting the second metal layer and the at least one intermediate metal layer, wherein the first metal layer, the through holes, the at least one intermediate metal layer, the through holes, the second metal layer, the through holes, and the at least one intermediate metal layer form an extension path, and the extension path extends in a clockwise spiral manner with the first metal layer as an extension starting point.
The invention utilizes the mode that the metal layer and the through hole are mutually connected in series in the vertical direction to manufacture the inductance element. When the number of induction turns of the inductance element is to be increased, only the number of layers of the metal layer in the vertical direction needs to be increased, namely, the number of turns of the inductance element is increased without increasing the occupied area on a plane. In addition, the present invention does have a large process window when designing and manufacturing various line widths of metal wires, i.e. considering that the metal line width is arbitrarily increased, there is no need to worry about the burden of the device on the use area, so that the inductance device with any appropriate line width can be easily manufactured. Moreover, due to the reduction of the area used on the plane, the inductance element of the invention greatly reduces the influence on the adjacent element area, especially the limitation of the adjacent element on the area use, namely, the invention provides more convenient choices for the arrangement of other elements.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
FIG. 1A is a cross-sectional view of the inductor structure of FIG. 1 taken along line A-A';
fig. 2 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
FIG. 2A is a cross-sectional view of the inductor structure along line A-A' of FIG. 2;
fig. 3 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
FIG. 3A is a cross-sectional view of the inductor structure taken along line A-A' of FIG. 3;
fig. 4 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
FIG. 4A is a cross-sectional view of the inductor structure of FIG. 4 taken along line A-A';
fig. 5 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
FIG. 5A is a cross-sectional view of the inductor structure along line A-A' of FIG. 5;
fig. 6 is a schematic cross-sectional view of an inductor structure according to an embodiment of the invention;
fig. 6A is a cross-sectional view of the inductor structure along line a-a' of fig. 6.
The symbols of the attached drawings:
10. 100, 1000 inductor structures;
12. 120, 1200 substrates;
14. 140, 1400 a first dielectric layer;
14 ', 140 ', 1400 ' bottom of the first dielectric layer;
16. 160, 1600 a first metal layer;
18. 180, 1800 second dielectric layer;
18 ', 180 ', 1800 ' bottom of the second dielectric layer;
20. 200, 2000 second metal layer;
22 an intermediate dielectric layer;
22' bottom of the middle dielectric layer;
24 an intermediate metal layer;
26. 28, 260, 280, 300, 2600, 2800, 3000, 3100 vias;
32. 320, 3200 extend the path;
34. 340, 3400 starting point of the first metal layer;
220. 2200 a first intermediate dielectric layer;
220 ', 2200' bottom of the first interlayer dielectric layer;
230. 2300 a second intermediate dielectric layer;
230 ', 2300' bottom of the second intermediate dielectric layer;
240. 2400 a first intermediate metal layer;
250. 2500 a second intermediate metal layer;
2350 a third intermediate dielectric layer;
2350' bottom of third intermediate dielectric layer;
2550 a third intermediate metal layer;
l lengths of the first metal layer, the second metal layer and the middle metal layer;
s, the distance between the middle metal layers;
t the thicknesses of the first metal layer, the second metal layer and the middle metal layer;
w the widths of the first metal layer, the second metal layer, and the middle metal layer.
Detailed Description
Referring to fig. 1, an inductor structure 10 is provided according to one of the embodiments of the present invention. Fig. 1 is a cross-sectional view of an inductor structure 10.
As shown in fig. 1, in the present embodiment, the inductor structure 10 includes a substrate 12, a first dielectric layer 14, a first metal layer 16, a second dielectric layer 18, a second metal layer 20, an intermediate dielectric layer 22, an intermediate metal layer 24, and a plurality of vias (26, 28). A first dielectric layer 14 is formed on the substrate 12. A first metal layer 16 is formed in the first dielectric layer 14 at the bottom 14' of the first dielectric layer 14. A second dielectric layer 18 is formed on the first dielectric layer 14. A second metal layer 20 is formed in the second dielectric layer 18 at the bottom 18' of the second dielectric layer 18. The first metal layer 16 and the second metal layer 20 are continuous metal layers. An intermediate dielectric layer 22 is formed between the first dielectric layer 14 and the second dielectric layer 18. An intermediate metal layer 24 is formed in the intermediate dielectric layer 22 at the bottom 22' of the intermediate dielectric layer 22. The intermediate metal layer 24 is a patterned metal layer.
In addition, vias (26, 28) connect the first metal layer 16 with the intermediate metal layer 24 and the second metal layer 20 with the intermediate metal layer 24, e.g., via 26 connects the first metal layer 16 with the intermediate metal layer 24 and via 28 connects the second metal layer 20 with the intermediate metal layer 24. It is noted that first metal layer 16, via 26, intermediate metal layer 24, via 28, second metal layer 20, via 28, and intermediate metal layer 24 form extended path 32. The extension path 32 extends in a counterclockwise spiral manner with a start point 34 of the first metal layer 16 as an extension start point, as shown in the cross-sectional view of fig. 1.
In some embodiments, substrate 12 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 14, the second dielectric layer 18, and the intermediate dielectric layer 22 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 16, second metal layer 20, and intermediate metal layer 24 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (26, 28) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, the length L of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 is between about 1um and about 100 um.
In some embodiments, the thickness T of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 is between about 0.01um and about 4 um.
In some embodiments, the widths W of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 are approximately between 0.01um and 100um, as shown in fig. 1A. FIG. 1A is a schematic cross-sectional view taken along line A-A' of FIG. 1.
In some embodiments, the spacing S between the patterned metal layers of the intermediate metal layer 24 is between about 0.01um and about 10 um.
Referring to fig. 2, an inductor structure 100 is provided according to one of the embodiments of the present invention. Fig. 2 is a cross-sectional view of the inductor structure 100.
As shown in fig. 2, in the present embodiment, the inductor structure 100 includes a substrate 120, a first dielectric layer 140, a first metal layer 160, a second dielectric layer 180, a second metal layer 200, a first intermediate dielectric layer 220, a second intermediate dielectric layer 230, a first intermediate metal layer 240, a second intermediate metal layer 250, and a plurality of vias (260, 280, 300). The first dielectric layer 140 is formed on the substrate 120. The first metal layer 160 is formed in the first dielectric layer 140 and located at the bottom 140' of the first dielectric layer 140. The second dielectric layer 180 is formed on the first dielectric layer 140. The second metal layer 200 is formed in the second dielectric layer 180 at the bottom 180' of the second dielectric layer 180. The first metal layer 160 and the second metal layer 200 are continuous metal layers. A first intermediate dielectric layer 220 is formed on the first dielectric layer 140. The first inter-metal layer 240 is formed in the first inter-dielectric layer 220 at the bottom 220' of the first inter-dielectric layer 220. The second interlayer dielectric layer 230 is formed on the first interlayer dielectric layer 220. The second intermediate metal layer 250 is formed in the second intermediate dielectric layer 230 at the bottom 230' of the second intermediate dielectric layer 230. The first intermediate metal layer 240 and the second intermediate metal layer 250 are patterned metal layers.
Vias (260, 280, 300) connect the first metal layer 160 with the first intermediate metal layer 240, the first intermediate metal layer 240 with the second intermediate metal layer 250, and the second metal layer 200 with the second intermediate metal layer 250, e.g., via 260 connects the first metal layer 160 with the first intermediate metal layer 240, via 280 connects the first intermediate metal layer 240 with the second intermediate metal layer 250, and via 300 connects the second metal layer 200 with the second intermediate metal layer 250. It is noted that the first metal layer 160, the via 260, the first intermediate metal layer 240, the via 280, the second intermediate metal layer 250, the via 300, the second metal layer 200, the via 300, the second intermediate metal layer 250, the via 280, the first intermediate metal layer 240, the via 280, and the second intermediate metal layer 250 form the extension path 320. The extension path 320 extends in a counterclockwise spiral manner with the starting point 340 of the first metal layer 160 as an extension starting point, as shown in the cross-sectional view of fig. 2.
In some embodiments, substrate 120 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 140, the second dielectric layer 180, the first intermediate dielectric layer 220, and the second intermediate dielectric layer 230 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 160, second metal layer 200, first intermediate metal layer 240, and second intermediate metal layer 250 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (260, 280, 300) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, the lengths L of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 are approximately between 1um and 100 um.
In some embodiments, the thickness T of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 is approximately between 0.01um and 4 um.
In some embodiments, the widths W of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 are approximately between 0.01um and 100um, as shown in fig. 2A. FIG. 2A is a schematic cross-sectional view taken along line A-A' of FIG. 2.
In some embodiments, the spacing S between the patterned metal layers of the first intermediate metal layer 240 and the second intermediate metal layer 250 is approximately 0.01um to 10 um.
Referring to fig. 3, an inductor structure 1000 is provided according to one of the embodiments of the present invention. Fig. 3 is a cross-sectional view of an inductor structure 1000.
As shown in fig. 3, in the present embodiment, the inductor structure 1000 includes a substrate 1200, a first dielectric layer 1400, a first metal layer 1600, a second dielectric layer 1800, a second metal layer 2000, a first intermediate dielectric layer 2200, a second intermediate dielectric layer 2300, a third intermediate dielectric layer 2350, a first intermediate metal layer 2400, a second intermediate metal layer 2500, a third intermediate metal layer 2550, and a plurality of vias (2600, 2800, 3000, 3100). A first dielectric layer 1400 is formed on the substrate 1200. The first metal layer 1600 is formed in the first dielectric layer 1400 at the bottom 1400' of the first dielectric layer 1400. A second dielectric layer 1800 is formed over the first dielectric layer 1400. The second metal layer 2000 is formed in the second dielectric layer 1800 at the bottom 1800' of the second dielectric layer 1800. The first metal layer 1600 and the second metal layer 2000 are continuous metal layers. A first intermediate dielectric layer 2200 is formed on the first dielectric layer 1400. The first intermediate metal layer 2400 is formed in the first intermediate dielectric layer 2200 at the bottom 2200' of the first intermediate dielectric layer 2200. The second intermediate dielectric layer 2300 is formed on the first intermediate dielectric layer 2200. The second intermediate metal layer 2500 is formed in the second intermediate dielectric layer 2300 at the bottom 2300' of the second intermediate dielectric layer 2300. The third intermediate dielectric layer 2350 is formed on the second intermediate dielectric layer 2300. A third intermediate metal layer 2550 is formed in the third intermediate dielectric layer 2350, at the bottom 2350' of the third intermediate dielectric layer 2350. First intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 are patterned metal layers.
Vias (2600, 2800, 3000, 3100) connect first metal layer 1600 to first intermediate metal layer 2400, first intermediate metal layer 2400 to second intermediate metal layer 2500, second intermediate metal layer 2500 to third intermediate metal layer 2550, and second metal layer 2000 to third intermediate metal layer 2550, e.g., via 2600 connects first metal layer 1600 to first intermediate metal layer 2400, via 2800 connects first intermediate metal layer 2400 to second intermediate metal layer 2500, via 3000 connects second intermediate metal layer 2500 to third intermediate metal layer 2550, and via 3100 connects second metal layer 2000 to third intermediate metal layer 2550. It is noted that the first metal layer 1600, the via 2600, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3100, the second metal layer 2000, the via 3100, the third intermediate metal layer 2550, the via 3000, the second intermediate metal layer 2500, the via 2800, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3000, and the second intermediate metal layer 2500 form the extension 3200. The extension path 3200 extends in a counterclockwise spiral manner with a start point 3400 of the first metal layer 1600 as an extension start point, as shown in the cross-sectional view of fig. 3.
In some embodiments, substrate 1200 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 1400, the second dielectric layer 1800, the first intermediate dielectric layer 2200, the second intermediate dielectric layer 2300, and the third intermediate dielectric layer 2350 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (2600, 2800, 3000, 3100) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have a length L of approximately 1um to 100 um.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have a thickness T of approximately 0.01um to 4 um.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have widths W of approximately 0.01um to 100um, as shown in FIG. 3A. FIG. 3A is a schematic cross-sectional view taken along line A-A' of FIG. 3.
In some embodiments, the spacing S of the patterned metal layers of first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 is approximately between 0.01um and 10 um.
Referring to fig. 4, an inductor structure 10 is provided according to one of the embodiments of the present invention. Fig. 4 is a cross-sectional view of the inductor structure 10.
As shown in fig. 4, in the present embodiment, the inductor structure 10 includes a substrate 12, a first dielectric layer 14, a first metal layer 16, a second dielectric layer 18, a second metal layer 20, an intermediate dielectric layer 22, an intermediate metal layer 24, and a plurality of vias (26, 28). A first dielectric layer 14 is formed on the substrate 12. A first metal layer 16 is formed in the first dielectric layer 14 at the bottom 14' of the first dielectric layer 14. A second dielectric layer 18 is formed on the first dielectric layer 14. A second metal layer 20 is formed in the second dielectric layer 18 at the bottom 18' of the second dielectric layer 18. The first metal layer 16 and the second metal layer 20 are continuous metal layers. An intermediate dielectric layer 22 is formed between the first dielectric layer 14 and the second dielectric layer 18. An intermediate metal layer 24 is formed in the intermediate dielectric layer 22 at the bottom 22' of the intermediate dielectric layer 22. The intermediate metal layer 24 is a patterned metal layer.
In addition, vias (26, 28) connect the first metal layer 16 with the intermediate metal layer 24 and the second metal layer 20 with the intermediate metal layer 24, e.g., via 26 connects the first metal layer 16 with the intermediate metal layer 24 and via 28 connects the second metal layer 20 with the intermediate metal layer 24. It is noted that first metal layer 16, via 26, intermediate metal layer 24, via 28, second metal layer 20, via 28, and intermediate metal layer 24 form extended path 32. The extension path 32 extends in a clockwise spiral manner with the start point 34 of the first metal layer 16 as an extension start point, as shown in the cross-sectional view of fig. 4.
In some embodiments, substrate 12 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 14, the second dielectric layer 18, and the intermediate dielectric layer 22 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 16, second metal layer 20, and intermediate metal layer 24 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (26, 28) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, the length L of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 is between about 1um and about 100 um.
In some embodiments, the thickness T of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 is between about 0.01um and about 4 um.
In some embodiments, the widths W of the first metal layer 16, the second metal layer 20, and the intermediate metal layer 24 are approximately between 0.01um and 100um, as shown in fig. 4A. FIG. 4A is a schematic cross-sectional view taken along line A-A' of FIG. 4.
In some embodiments, the spacing S between the patterned metal layers of the intermediate metal layer 24 is between about 0.01um and about 10 um.
Referring to fig. 5, an inductor (inductor) structure 100 is provided according to one of the embodiments of the present invention. Fig. 5 is a cross-sectional view of the inductor structure 100.
As shown in fig. 5, in the present embodiment, the inductor structure 100 includes a substrate 120, a first dielectric layer 140, a first metal layer 160, a second dielectric layer 180, a second metal layer 200, a first intermediate dielectric layer 220, a second intermediate dielectric layer 230, a first intermediate metal layer 240, a second intermediate metal layer 250, and a plurality of vias (260, 280, 300). The first dielectric layer 140 is formed on the substrate 120. The first metal layer 160 is formed in the first dielectric layer 140 and located at the bottom 140' of the first dielectric layer 140. The second dielectric layer 180 is formed on the first dielectric layer 140. The second metal layer 200 is formed in the second dielectric layer 180 at the bottom 180' of the second dielectric layer 180. The first metal layer 160 and the second metal layer 200 are continuous metal layers. A first intermediate dielectric layer 220 is formed on the first dielectric layer 140. The first inter-metal layer 240 is formed in the first inter-dielectric layer 220 at the bottom 220' of the first inter-dielectric layer 220. The second interlayer dielectric layer 230 is formed on the first interlayer dielectric layer 220. The second intermediate metal layer 250 is formed in the second intermediate dielectric layer 230 at the bottom 230' of the second intermediate dielectric layer 230. The first intermediate metal layer 240 and the second intermediate metal layer 250 are patterned metal layers.
Vias (260, 280, 300) connect the first metal layer 160 with the first intermediate metal layer 240, the first intermediate metal layer 240 with the second intermediate metal layer 250, and the second metal layer 200 with the second intermediate metal layer 250, e.g., via 260 connects the first metal layer 160 with the first intermediate metal layer 240, via 280 connects the first intermediate metal layer 240 with the second intermediate metal layer 250, and via 300 connects the second metal layer 200 with the second intermediate metal layer 250. It is noted that the first metal layer 160, the via 260, the first intermediate metal layer 240, the via 280, the second intermediate metal layer 250, the via 300, the second metal layer 200, the via 300, the second intermediate metal layer 250, the via 280, the first intermediate metal layer 240, the via 280, and the second intermediate metal layer 250 form the extension path 320. The extension path 320 extends in a clockwise spiral manner with the start point 340 of the first metal layer 160 as an extension start point, as shown in the cross-sectional view of fig. 5.
In some embodiments, substrate 120 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 140, the second dielectric layer 180, the first intermediate dielectric layer 220, and the second intermediate dielectric layer 230 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 160, second metal layer 200, first intermediate metal layer 240, and second intermediate metal layer 250 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (260, 280, 300) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, the lengths L of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 are approximately between 1um and 100 um.
In some embodiments, the thickness T of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 is approximately between 0.01um and 4 um.
In some embodiments, the widths W of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240, and the second intermediate metal layer 250 are approximately between 0.01um and 100um, as shown in fig. 5A. FIG. 5A is a schematic cross-sectional view taken along line A-A' of FIG. 5.
In some embodiments, the spacing S between the patterned metal layers of the first intermediate metal layer 240 and the second intermediate metal layer 250 is approximately 0.01um to 10 um.
Referring to fig. 6, an inductor structure 1000 is provided according to one of the embodiments of the present invention. Fig. 6 is a cross-sectional view of an inductor structure 1000.
As shown in fig. 6, in the present embodiment, the inductor structure 1000 includes a substrate 1200, a first dielectric layer 1400, a first metal layer 1600, a second dielectric layer 1800, a second metal layer 2000, a first intermediate dielectric layer 2200, a second intermediate dielectric layer 2300, a third intermediate dielectric layer 2350, a first intermediate metal layer 2400, a second intermediate metal layer 2500, a third intermediate metal layer 2550, and a plurality of vias (2600, 2800, 3000, 3100). A first dielectric layer 1400 is formed on the substrate 1200. The first metal layer 1600 is formed in the first dielectric layer 1400 at the bottom 1400' of the first dielectric layer 1400. A second dielectric layer 1800 is formed over the first dielectric layer 1400. The second metal layer 2000 is formed in the second dielectric layer 1800 at the bottom 1800' of the second dielectric layer 1800. The first metal layer 1600 and the second metal layer 2000 are continuous metal layers. A first intermediate dielectric layer 2200 is formed on the first dielectric layer 1400. The first intermediate metal layer 2400 is formed in the first intermediate dielectric layer 2200 at the bottom 2200' of the first intermediate dielectric layer 2200. The second intermediate dielectric layer 2300 is formed on the first intermediate dielectric layer 2200. The second intermediate metal layer 2500 is formed in the second intermediate dielectric layer 2300 at the bottom 2300' of the second intermediate dielectric layer 2300. The third intermediate dielectric layer 2350 is formed on the second intermediate dielectric layer 2300. A third intermediate metal layer 2550 is formed in the third intermediate dielectric layer 2350, at the bottom 2350' of the third intermediate dielectric layer 2350. First intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 are patterned metal layers.
Vias (2600, 2800, 3000, 3100) connect first metal layer 1600 to first intermediate metal layer 2400, first intermediate metal layer 2400 to second intermediate metal layer 2500, second intermediate metal layer 2500 to third intermediate metal layer 2550, and second metal layer 2000 to third intermediate metal layer 2550, e.g., via 2600 connects first metal layer 1600 to first intermediate metal layer 2400, via 2800 connects first intermediate metal layer 2400 to second intermediate metal layer 2500, via 3000 connects second intermediate metal layer 2500 to third intermediate metal layer 2550, and via 3100 connects second metal layer 2000 to third intermediate metal layer 2550. It is noted that the first metal layer 1600, the via 2600, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3100, the second metal layer 2000, the via 3100, the third intermediate metal layer 2550, the via 3000, the second intermediate metal layer 2500, the via 2800, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3000, and the second intermediate metal layer 2500 form the extension 3200. The extension path 3200 extends in a clockwise spiral manner with a start point 3400 of the first metal layer 1600 as an extension start point, as shown in the cross-sectional view of fig. 6.
In some embodiments, substrate 1200 may comprise a silicon substrate or other suitable substrate material.
In some embodiments, the first dielectric layer 1400, the second dielectric layer 1800, the first intermediate dielectric layer 2200, the second intermediate dielectric layer 2300, and the third intermediate dielectric layer 2350 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other suitable low-k dielectric material.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 may comprise, for example, copper, aluminum, or other suitable metallic conductive material.
In some embodiments, the vias (2600, 2800, 3000, 3100) may be filled with, for example, copper, tungsten, or other suitable metallic conductive material.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have a length L of approximately 1um to 100 um.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have a thickness T of approximately 0.01um to 4 um.
In some embodiments, first metal layer 1600, second metal layer 2000, first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 have widths W of approximately 0.01um to 100um, as shown in FIG. 6A. FIG. 6A is a cross-sectional view taken along line A-A' of FIG. 6.
In some embodiments, the spacing S of the patterned metal layers of first intermediate metal layer 2400, second intermediate metal layer 2500, and third intermediate metal layer 2550 is approximately between 0.01um and 10 um.
The invention utilizes the mode that the metal layer and the through hole are mutually connected in series in the vertical direction to manufacture the inductance element. When the number of induction turns of the inductance element is to be increased, only the number of layers of the metal layer in the vertical direction needs to be increased, namely, the number of turns of the inductance element is increased without increasing the occupied area on a plane. In addition, when designing and manufacturing various line widths of metal wires, the invention really has a large process space, i.e. under the condition of considering the random increase of the metal line width, the load of the element on the use area is not required to be worried about, and therefore, the inductance element with any proper line width can be easily manufactured. Moreover, due to the reduction of the area used on the plane, the inductance element of the invention greatly reduces the influence on the adjacent element area, especially the limitation of the adjacent element on the area use, namely, the invention provides more convenient choices for the arrangement of other elements.
Although the present invention has been described with reference to a number of illustrative embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. An inductive structure, comprising:
a substrate;
a first dielectric layer formed on the substrate;
a first metal layer formed in the first dielectric layer;
a second dielectric layer formed on the first dielectric layer;
a second metal layer formed in the second dielectric layer, wherein the first metal layer and the second metal layer are continuous metal layers;
at least one intermediate dielectric layer formed between the first dielectric layer and the second dielectric layer;
at least one intermediate metal layer formed in the at least one intermediate dielectric layer, wherein the at least one intermediate metal layer is a patterned metal layer; and
a plurality of through holes connecting the first metal layer and the at least one intermediate metal layer, and connecting the second metal layer and the at least one intermediate metal layer, wherein the first metal layer, the through holes, the at least one intermediate metal layer, the through holes, the second metal layer, the through holes, and the at least one intermediate metal layer form an extension path, and the extension path takes the first metal layer as an extension starting point and extends in a counterclockwise spiral manner.
2. The inductor structure of claim 1, wherein the lengths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 1um and 100 um.
3. The inductor structure of claim 1, wherein the first metal layer, the second metal layer, and the at least one intermediate metal layer have a thickness of 0.01um to 4 um.
4. The inductor structure of claim 1, wherein the widths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 0.01um and 100 um.
5. The inductor structure of claim 1, wherein the pitch of the patterned metal layer of the at least one intermediate metal layer is between 0.01um and 10 um.
6. The inductor structure of claim 1, wherein the at least one intermediate dielectric layer is a single intermediate dielectric layer and the at least one intermediate metal layer is a single intermediate metal layer.
7. The inductor structure of claim 1, wherein the at least one intermediate dielectric layer is a double-layer intermediate dielectric layer, and the at least one intermediate metal layer is a double-layer intermediate metal layer.
8. The inductor structure of claim 7, further comprising a plurality of vias connecting the intermediate metal layers of different layers.
9. The inductor structure of claim 1, wherein the at least one middle dielectric layer is a tri-layer middle dielectric layer, and the at least one middle metal layer is a tri-layer middle metal layer.
10. The inductor structure of claim 9, further comprising a plurality of vias connecting the intermediate metal layers of different layers.
11. An inductive structure, comprising:
a substrate;
a first dielectric layer formed on the substrate;
a first metal layer formed in the first dielectric layer;
a second dielectric layer formed on the first dielectric layer;
a second metal layer formed in the second dielectric layer, wherein the first metal layer and the second metal layer are continuous metal layers;
at least one intermediate dielectric layer formed between the first dielectric layer and the second dielectric layer;
at least one intermediate metal layer formed in the at least one intermediate dielectric layer, wherein the at least one intermediate metal layer is a patterned metal layer; and
a plurality of through holes connecting the first metal layer and the at least one intermediate metal layer, and connecting the second metal layer and the at least one intermediate metal layer, wherein the first metal layer, the through holes, the at least one intermediate metal layer, the through holes, the second metal layer, the through holes, and the at least one intermediate metal layer form an extension path, and the extension path extends in a clockwise spiral manner with the first metal layer as an extension starting point.
12. The inductor structure of claim 11, wherein the lengths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 1um and 100 um.
13. The inductor structure of claim 11, wherein the first metal layer, the second metal layer, and the at least one intermediate metal layer have a thickness of 0.01um to 4 um.
14. The inductor structure of claim 11, wherein the widths of the first metal layer, the second metal layer, and the at least one intermediate metal layer are between 0.01um and 100 um.
15. The inductor structure of claim 11, wherein the pitch of the patterned metal layer of the at least one intermediate metal layer is between 0.01um and 10 um.
16. The inductor structure of claim 11, wherein the at least one intermediate dielectric layer is a single intermediate dielectric layer and the at least one intermediate metal layer is a single intermediate metal layer.
17. The inductor structure of claim 11, wherein the at least one intermediate dielectric layer is a double intermediate dielectric layer and the at least one intermediate metal layer is a double intermediate metal layer.
18. The inductor structure of claim 17, further comprising a plurality of vias connecting the intermediate metal layers of different layers.
19. The inductor structure of claim 11, wherein the at least one middle dielectric layer is a tri-layer middle dielectric layer, and the at least one middle metal layer is a tri-layer middle metal layer.
20. The inductor structure of claim 19, further comprising a plurality of vias connecting the intermediate metal layers of different layers.
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| CN201811107158.3A CN110943072A (en) | 2018-09-21 | 2018-09-21 | Inductance structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070155152A1 (en) * | 2005-12-29 | 2007-07-05 | Kang Myung Ii | Method of manufacturing a copper inductor |
| US20080297299A1 (en) * | 2007-05-31 | 2008-12-04 | Electronics And Telecommunications Research Institute | Vertically formed inductor and electronic device having the same |
| CN201966211U (en) * | 2011-01-23 | 2011-09-07 | 杭州电子科技大学 | Integrated spiral inductance on vertical structural sheet |
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2018
- 2018-09-21 CN CN201811107158.3A patent/CN110943072A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070155152A1 (en) * | 2005-12-29 | 2007-07-05 | Kang Myung Ii | Method of manufacturing a copper inductor |
| US20080297299A1 (en) * | 2007-05-31 | 2008-12-04 | Electronics And Telecommunications Research Institute | Vertically formed inductor and electronic device having the same |
| CN201966211U (en) * | 2011-01-23 | 2011-09-07 | 杭州电子科技大学 | Integrated spiral inductance on vertical structural sheet |
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