CN110943055A - Fan-out type double-sided wiring packaging method and structure - Google Patents
Fan-out type double-sided wiring packaging method and structure Download PDFInfo
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- CN110943055A CN110943055A CN201911266437.9A CN201911266437A CN110943055A CN 110943055 A CN110943055 A CN 110943055A CN 201911266437 A CN201911266437 A CN 201911266437A CN 110943055 A CN110943055 A CN 110943055A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 238000000576 coating method Methods 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims abstract description 31
- 239000011248 coating agent Substances 0.000 claims abstract description 30
- 229910000679 solder Inorganic materials 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 23
- 229910016347 CuSn Inorganic materials 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010949 copper Substances 0.000 description 10
- 230000010354 integration Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a fan-out type double-sided wiring packaging method and structure, and belongs to the technical field of semiconductor packaging. Firstly, providing a carrier, and mounting a TSV adapter plate and a chip on the carrier through a thermal stripping film; the TSV adapter plate is internally provided with interconnection metal, and the exterior of the TSV adapter plate is provided with a metal bump; coating the TSV adapter plate and the chip, and removing the thermal stripping film and the carrier to form a wafer carrier; then forming a passivation layer and a wiring layer on the front surface of the wafer carrier, and growing a metal bump on the wiring layer; coating the front surface of the wafer carrier, thinning the metal bump of which the back surface is exposed out of the TSV adapter plate, and forming a passivation layer and a rewiring layer on the surface; and finally, thinning the front surface of the wafer carrier until the metal bump on the wiring layer is exposed, and growing a solder ball bump on the exposed metal bump.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging method and a structure of fan-out type double-sided wiring.
Background
With the development of electronic products in the directions of miniaturization, high performance, high reliability and the like, the system integration level is also increasingly improved. Under the circumstances, the way to improve the performance by further reducing the feature size of the integrated circuit and the line width of the interconnection line is limited by the physical characteristics of the material and the equipment process, and the conventional moore's law has been difficult to develop. Three-dimensional integration based on Fan-out (Fan-out) wafer level packaging technology is currently being developed as a main advanced packaging technology with high integration flexibility as an effective way to achieve high integration, miniaturization and low-cost application of electronic system components.
At present, two common fan-out type three-dimensional integration modes are TMV fan-out type packaging and TSV fan-out type packaging, and vertical interconnection inside a packaging body is achieved through TMV or TSV.
(1) TMV fan-out package
At present, the mainstream TMV fan-out type packaging in the industry adopts the RDL first fan-out type process of the platform-like accumulated electricity Info technology, internal vertical interconnected copper columns and rewiring are generated through an electroplating method, a chip is welded to a rewiring layer through flip-chip welding, then the chip is subjected to plastic molding together, and the metal copper columns are exposed through a lapping process, as shown in figure 1, but the scheme has the following problems: the structure is required to satisfy that the height of the vertical interconnection copper pillar 101 is greater than the sum of the thickness of the chip 102 and the thickness of the chip surface bump 103. The height of the interconnected copper column is limited by the fact that the bump process cannot be processed to be high (the bump height is less than or equal to 120 mu m), and for large chip products, the thickness of the chip cannot be thinned to be thin, so that fan-out integration cannot be carried out on part of products, particularly large chip products, by using the scheme; the method is limited by the depth-to-width ratio constraint of the photoetching process, the size of the interconnected copper column is relatively large, and the application requirements cannot be met in the design of high-density double-sided wiring products.
(2) TSV fan-out package
The TSV fan-out type packaging is achieved by performing plastic packaging integration on the TSV adapter plate 201 and the chip 202, and exposing the vertical interconnection copper pillars 203 of the TSV adapter plate through a lapping process to achieve double-sided wiring interconnection, as shown in FIG. 2. The TSV fan-out type package has a smaller width of a vertical interconnection copper column (the minimum is 10 mu m), and the thickness of a thicker TSV adapter plate (the thickness can be processed to be more than 200 mu m); compared with TMV fan-out type packaging, the packaging structure has better compatibility and flexibility, can meet the application requirements of different types of products, but the current scheme has the following problems: during the double-sided wiring process, a temporary bonding process is required to bond the fan-out package to the temporary carrier. The fan-out type packaging body has warping, and when the warping is too large, the processes such as coating or bonding of temporary bonding cannot be performed easily; in the structure, the TSV adapter plate area is only coated on four sides, so that the phenomena of layering or cracking and the like of the joint surface of the adapter plate and the plastic package material are easily caused in reliability tests such as temperature cycle and the like; after the vertical interconnection copper column is exposed by thinning the packaging body, the packaging body is insufficient in structural strength because the packaging body is large in plane size and relatively thin in thickness. Due to the fact that the CTE mismatch problem exists among the TSV adapter plate, the silicon chip and the plastic package material, a single package body is prone to warping in the subsequent high-temperature technological process, stress inside the package body is concentrated, and functional failure is prone to occurring in the subsequent technological process.
Disclosure of Invention
The invention aims to provide a fan-out type double-sided wiring packaging method and structure, and aims to solve the problems that double-sided wiring integration cannot be carried out by the conventional packaging method, and the prepared product is poor in reliability.
In order to solve the technical problem, the invention provides a fan-out type double-sided wiring packaging method, which comprises the following steps:
providing a carrier, and mounting the TSV adapter plate and the chip on the carrier through a thermal stripping film; the TSV adapter plate is internally provided with interconnection metal, and the exterior of the TSV adapter plate is provided with a metal bump;
coating the TSV adapter plate and the chip, and removing the thermal stripping film and the carrier to form a wafer carrier;
forming a passivation layer and a wiring layer on the front surface of the wafer carrier, and growing a metal bump on the wiring layer;
coating the front surface of the wafer carrier, thinning the metal bump of which the back surface is exposed out of the TSV adapter plate, and forming a passivation layer and a rewiring layer on the surface;
and thinning the front surface of the wafer carrier until the metal bumps on the wiring layer are exposed, and growing solder ball bumps on the exposed metal bumps.
Optionally, the TSV adapter plate and the chip are coated by a coating material;
and coating the front surface of the wafer carrier by using a coating material, namely coating the passivation layer and the wiring layer on the front surface of the wafer carrier by using the coating material.
Optionally, the sum of the thicknesses of the TSV interposer and the metal bumps outside the TSV interposer is greater than the thickness of the chip.
Optionally, a distance between the TSV interposer and the chip is greater than 50 μm.
Optionally, the thickness of the TSV adapter plate is 100-300 μm, and the thickness of the metal bump outside the TSV adapter plate is 10-80 μm.
Optionally, the metal bump outside the TSV interposer is made of Cu, CuSn, CuNiSn, or cunisngag.
Optionally, a passivation layer is formed on one surface of the TSV pinboard on which the metal bump is arranged.
Optionally, the number of the TSV pinboards is not less than 1, and the number of the chips is not less than 1.
The invention also provides a fan-out type double-sided wiring packaging structure, which comprises:
the wafer carrier formed by the TSV adapter plate and the chip is coated by a coating material, a passivation layer and a wiring layer are formed on the front surface of the wafer carrier, and metal bumps grow on the wiring layer; the metal bump and the passivation layer are coated by a coating material; solder bump is grown on the metal bump;
and a passivation layer and a rewiring layer are formed on the back surface of the wafer carrier.
Optionally, the TSV pinboard is internally provided with interconnection metal, and the back of the exterior of the TSV pinboard is provided with a metal bump.
The invention provides a fan-out type double-sided wiring packaging method and a fan-out type double-sided wiring packaging structure, which comprises the steps of firstly providing a carrier, and mounting a TSV adapter plate and a chip on the carrier through a thermal stripping film; the TSV adapter plate is internally provided with interconnection metal, and the exterior of the TSV adapter plate is provided with a metal bump; coating the TSV adapter plate and the chip, and removing the thermal stripping film and the carrier to form a wafer carrier; then forming a passivation layer and a wiring layer on the front surface of the wafer carrier, and growing a metal bump on the wiring layer; coating the front surface of the wafer carrier, thinning the metal bump of which the back surface is exposed out of the TSV adapter plate, and forming a passivation layer and a rewiring layer on the surface; and finally, thinning the front surface of the wafer carrier until the metal bump on the wiring layer is exposed, and growing a solder ball bump on the exposed metal bump.
The invention has the following beneficial effects:
(1) through the integration of the TSV and the TMV fan-out type process, the double-sided wiring application requirements of various types of products such as products with multiple thicknesses, multiple sizes and high-density double-sided wiring are met;
(2) by adopting the TSV adapter plate with the metal bumps with a certain height on the surface, a five-surface-coated packaging structure formed after the TSV adapter plate is subjected to plastic packaging can be realized, and the strength and reliability of a packaging body in the TSV adapter plate area are improved;
(3) the metal salient points are led out from the front surface of the TSV adapter plate and exposed after plastic package, and the structural strength and reliability of the packaging body are improved to a greater extent under the condition that the application requirement of double-sided wiring is met. Meanwhile, the warping of the packaging body can be effectively controlled by adjusting the thickness of the metal bump on the front surface and the thickness of the plastic package;
(4) and a temporary bonding process is not needed, so that the constraint caused by the fact that the temporary bonding process cannot be carried out due to overlarge warping after the single-side rewiring of the fan-out type packaging body is completed is avoided.
Drawings
FIG. 1 is a schematic diagram of a prior art TMV fan-out package;
FIG. 2 is a schematic diagram of a prior art TSV fan-out package;
FIG. 3 is a flow chart of a packaging method for fan-out double-sided wiring provided by the present invention;
FIG. 4 is a schematic cross-sectional view of a TSV interposer with interconnect metal and metal bumps;
FIG. 5 is a schematic diagram of a TSV interposer and a chip mounted on a carrier;
FIG. 6 is a schematic view of a new wafer carrier formed after encapsulation of the TSV interposer and chips and removal of the carrier;
FIG. 7 is a schematic illustration of the formation of a passivation layer and a wiring layer on the front side of a new wafer carrier and the growth of a metal bump over the wiring layer;
fig. 8 is a schematic view of a passivation layer and metal bumps on the front side of a clad wafer carrier;
FIG. 9 is a schematic view of thinning the back side of the wafer carrier to expose the metal bumps and form a passivation layer and a redistribution layer;
FIG. 10 is a schematic view of a thinned wafer carrier with metal bumps exposed on the front side;
fig. 11 is a schematic diagram of a fan-out type double-sided wiring structure finally formed.
Detailed Description
The following describes a packaging method and structure of fan-out type double-sided wiring according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a fan-out type double-sided wiring packaging method, the flow of which is shown in figure 3, and the method comprises the following steps:
step S31, providing a carrier, and mounting the TSV adapter plate and the chip on the carrier through a thermal stripping film; the TSV adapter plate is internally provided with interconnection metal, and the exterior of the TSV adapter plate is provided with a metal bump;
step S32, coating the TSV adapter plate and the chip, and removing the thermal peeling film and the carrier to form a wafer carrier;
step S33, forming a passivation layer and a wiring layer on the front surface of the wafer carrier, and growing a metal bump on the wiring layer;
step S34, coating the front surface of the wafer carrier, thinning the metal bump of which the back surface is exposed out of the TSV adapter plate, and forming a passivation layer and a rewiring layer on the surface;
and step S35, thinning the front surface of the wafer carrier until the metal bumps on the wiring layer are exposed, and growing solder ball bumps on the exposed metal bumps.
A TSV interposer 301 is manufactured through a TSV processing process, a vertical interconnection metal 303 is arranged inside the TSV interposer 301, a metal bump 304 with a certain height is arranged outside the TSV interposer 301, a cross-sectional view of the TSV interposer is shown in fig. 4, a passivation layer (not shown) can be arranged at the bottom of the metal bump 304, and the passivation layer is connected with the TSV interposer 301, so that secondary insulation protection can be achieved, and stress in the metal bump 304 region can be relieved; the external metal bump 304 of the TSV interposer is made of Cu, CuSn, CuNiSn, or cunisngag. Providing a carrier 402, and sub-packaging the TSV adapter plates 301 and the chips 302 on the carrier 402 through a thermal peeling film 401, wherein the number of the TSV adapter plates 301 is not less than 1, and the number of the chips 302 is not less than 1, as shown in FIG. 5; the thickness of the TSV adapter plate 301 is 100-300 microns, the thickness of the metal bump 304 outside the TSV adapter plate is 10-80 microns, the sum of the thicknesses of the TSV adapter plate 301 and the metal bump 304 outside the TSV adapter plate is larger than the thickness of the chip 302, the relative position of the TSV adapter plate 301 and the chip 302 is controlled through alignment, and the distance d between the TSV adapter plate 301 and the adjacent chip 302 is larger than 50 microns; the TSV interposer 301 may be formed by welding and stacking a plurality of identical interposers;
then, by using a coating process such as film pressing or injection molding, the TSV interposer 301 and the chip 302 are coated with a coating material 305, and the thermal peeling film 401 and the carrier 402 are removed by a pyrolysis process to form a new wafer carrier, where the back surfaces and the side surfaces of the TSV interposer 301 and the chip 302 are completely coated with the coating material 305, as shown in fig. 6;
referring to fig. 7, a passivation layer 306 and a wiring layer 307 are formed on the front surface of the formed new wafer carrier by a wafer-level wiring process, and a metal bump 308 is grown on the wiring layer 307 by a wafer-level bump process;
the new wafer carrier front side is coated with a coating material 309, and the coating material 309 coats the passivation layer 306 and the wiring layer 307 on the wafer carrier front side, as shown in fig. 8; wherein the coating material 309 and the rest coating material 305 are molding compounds;
thinning the cladding material 305 on the back surface of the wafer carrier by lapping and other processes until the metal bump 304 of the TSV interposer 301 is exposed, and continuing to form a passivation layer 310 and a rewiring layer 311 on the surface by a wafer-level wiring process, as shown in fig. 9;
as shown in fig. 10, thinning the cladding material 309 on the front surface of the wafer carrier by lapping or the like until the metal bump 308 on the wiring layer 307 is exposed; the solder bump 312 is grown on the exposed metal bump 308 by a wafer-level ball-mounting process, so as to generate the package shown in fig. 11.
Example two
The invention provides a fan-out type double-sided wiring packaging structure, which is structurally shown in fig. 11 and comprises a wafer carrier formed by wrapping a TSV adapter plate 301 and a chip 302 through a wrapping material 305, wherein a passivation layer 306 and a wiring layer 307 are formed on the front surface of the wafer carrier, and a metal bump 308 grows on the wiring layer 307; the metal bump 308 and the passivation layer 306 are covered by an encapsulant 309; solder bump 312 is grown on the metal bump 308; a passivation layer 310 and a re-wiring layer 311 are formed on the back side of the wafer carrier.
The TSV adapter plate 301 is internally provided with interconnection metal 303, and the back surface of the TSV adapter plate is provided with metal bumps 304.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A packaging method of fan-out type double-sided wiring is characterized by comprising the following steps:
providing a carrier, and mounting the TSV adapter plate and the chip on the carrier through a thermal stripping film; the TSV adapter plate is internally provided with interconnection metal, and the exterior of the TSV adapter plate is provided with a metal bump;
coating the TSV adapter plate and the chip, and removing the thermal stripping film and the carrier to form a wafer carrier;
forming a passivation layer and a wiring layer on the front surface of the wafer carrier, and growing a metal bump on the wiring layer;
coating the front surface of the wafer carrier, thinning the metal bump of which the back surface is exposed out of the TSV adapter plate, and forming a passivation layer and a rewiring layer on the surface;
and thinning the front surface of the wafer carrier until the metal bumps on the wiring layer are exposed, and growing solder ball bumps on the exposed metal bumps.
2. The packaging method of fan-out double-sided wiring according to claim 1, wherein the TSV interposer and the chip are encapsulated by a cladding material;
and coating the front surface of the wafer carrier by using a coating material, namely coating the passivation layer and the wiring layer on the front surface of the wafer carrier by using the coating material.
3. The packaging method of fan-out double-sided wiring as claimed in claim 1, wherein the sum of the thicknesses of the TSV interposer and its external metal bumps is greater than the thickness of the chip.
4. The packaging method of fan-out double-sided wiring of claim 1, wherein a pitch of the TSV interposer and the chip is greater than 50 μ ι η.
5. The packaging method of fan-out double-sided wiring according to claim 1, wherein the thickness of the TSV adapter plate is 100-300 μm, and the thickness of the metal bump outside the TSV adapter plate is 10-80 μm.
6. The packaging method for the fan-out type double-sided wiring of claim 1, wherein the material of the metal bump outside the TSV interposer is Cu, CuSn, CuNiSn or CuNiSnAg.
7. The packaging method of the fan-out type double-sided wiring as claimed in claim 1, wherein a passivation layer is formed on one side of the TSV interposer where the metal bumps are disposed.
8. The packaging method of fan-out double-sided wiring as claimed in claim 1, wherein the number of the TSV interposer is not less than 1, and the number of the chips is not less than 1.
9. A package structure of fan-out type double-sided wiring is characterized by comprising:
the wafer carrier formed by the TSV adapter plate (301) and the chip (302) is coated by a coating material (305), a passivation layer (306) and a wiring layer (307) are formed on the front surface of the wafer carrier, and a metal bump (308) grows on the wiring layer (307); the metal bump (308) and the passivation layer (306) are coated by a coating material (309); solder ball bumps (312) grow on the metal bumps (308);
a passivation layer (310) and a rewiring layer (311) are formed on the back of the wafer carrier.
10. The packaging structure of fan-out type double-sided wiring of claim 9, wherein the TSV interposer (301) is internally provided with an interconnection metal (303) and externally provided with a metal bump (304) on the back surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911266437.9A CN110943055A (en) | 2019-12-11 | 2019-12-11 | Fan-out type double-sided wiring packaging method and structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911266437.9A CN110943055A (en) | 2019-12-11 | 2019-12-11 | Fan-out type double-sided wiring packaging method and structure |
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| CN110943055A true CN110943055A (en) | 2020-03-31 |
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| CN201911266437.9A Pending CN110943055A (en) | 2019-12-11 | 2019-12-11 | Fan-out type double-sided wiring packaging method and structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576517A (en) * | 2013-10-29 | 2015-04-29 | 新科金朋有限公司 | Semiconductor device and method of balancing surfaces of an embedded pcb unit with a dummy copper pattern |
| CN109509727A (en) * | 2017-09-15 | 2019-03-22 | Pep创新私人有限公司 | A kind of semiconductor chip packaging method and encapsulating structure |
| CN110416175A (en) * | 2018-04-30 | 2019-11-05 | 爱思开海力士有限公司 | Semiconductor packages including the bridge-type chip being spaced apart with semiconductor wafer |
| CN210743932U (en) * | 2019-12-11 | 2020-06-12 | 中国电子科技集团公司第五十八研究所 | Packaging structure of fan-out type double-sided wiring |
-
2019
- 2019-12-11 CN CN201911266437.9A patent/CN110943055A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576517A (en) * | 2013-10-29 | 2015-04-29 | 新科金朋有限公司 | Semiconductor device and method of balancing surfaces of an embedded pcb unit with a dummy copper pattern |
| CN109509727A (en) * | 2017-09-15 | 2019-03-22 | Pep创新私人有限公司 | A kind of semiconductor chip packaging method and encapsulating structure |
| CN110416175A (en) * | 2018-04-30 | 2019-11-05 | 爱思开海力士有限公司 | Semiconductor packages including the bridge-type chip being spaced apart with semiconductor wafer |
| CN210743932U (en) * | 2019-12-11 | 2020-06-12 | 中国电子科技集团公司第五十八研究所 | Packaging structure of fan-out type double-sided wiring |
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