CN110933383B - Overcurrent protection method and device for antenna control chip and satellite television receiver - Google Patents
Overcurrent protection method and device for antenna control chip and satellite television receiver Download PDFInfo
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Abstract
The invention discloses an overcurrent protection method and device of an antenna control chip and a satellite television receiver, wherein the protection method comprises the steps of sending an enabling signal to the antenna control chip once at preset intervals when a starting trigger signal is detected, and recording the total times of sending the enabling signal; and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip. The method can avoid the problem that the antenna control chip cannot be recovered due to self-locking at the moment of starting.
Description
Technical Field
The disclosure relates to the field of televisions, and in particular relates to an overcurrent protection method and device for an antenna control chip and a satellite television receiver.
Background
Televisions are mainly classified into cable televisions, wireless televisions, and satellite televisions. The satellite television receives electromagnetic wave signals transmitted by a satellite through a satellite receiving antenna (namely a cauldron). Currently, satellite receiving antennas above disc1.2 are used in large areas in europe, and such antennas mostly have motors. The antenna control chip is used for providing power supply and control signals for a tuner of the satellite receiving antenna, and the output end of the antenna control chip is electrically connected with the motor. At the moment of starting a television, a coil of a motor is charged instantly to extract current, so that an antenna control chip generates larger impact current instantly (the impact value of the current reaches 1.224A), the impact current reaches a critical current value of self-protection of the antenna control chip, and when the duration of the impact current reaches the time length (for example, 6ms) required by the antenna control chip to enter self-locking, the antenna control chip starts self-locking to enter a self-protection state and cannot recover, so that the antenna control chip cannot work normally, the television cannot receive signals, and a television screen has no image display or displays a prompt that the signals cannot be searched.
Disclosure of Invention
In order to solve the problem that the control chip cannot be recovered due to self protection caused by large impact current generated by the antenna control chip at the moment of starting up in the related art, the disclosure provides an overcurrent protection method and device of the antenna control chip and a satellite television receiver.
The present disclosure provides an overcurrent protection method for an antenna control chip, including:
when a trigger signal of starting up is detected, an enabling signal is sent to an antenna control chip once at preset time intervals, and the total times of sending the enabling signal is recorded;
and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip.
In one embodiment, the step of sending an enable signal to the antenna control chip every predetermined time interval and recording the total number of times the enable signal is sent when the trigger signal for starting up is detected includes:
when a starting-up trigger signal is detected, the temperature of the antenna control chip is obtained through a temperature detection device;
judging whether the temperature of the antenna control chip exceeds a preset temperature or not;
if yes, sending an enabling signal to the antenna control chip once at preset time intervals, and recording the total times of sending the enabling signal.
In one embodiment, the step of sending an enable signal to the antenna control chip every predetermined time interval and recording the total number of times the enable signal is sent when the trigger signal for starting up is detected includes:
when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip;
judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if yes, an enabling signal is sent to the antenna control chip once every preset time, and the total times of sending the enabling signal is recorded.
In one embodiment, the enable signal is a high level signal or a low level signal, a duration of the enable signal sent each time is longer than a preset time length, and the preset time length is a time required for the antenna control chip to enter the self-locking state.
In one embodiment, the preset times are 4-6 times, the interval preset time is 6-7 ms, and the preset times and the interval preset time are stored in a configuration file in advance.
The present disclosure further provides an overcurrent protection device of an antenna control chip, including:
an enable signal issuing module configured to: when a trigger signal of starting up is detected, an enabling signal is sent to an antenna control chip once at preset time intervals, and the total times of sending the enabling signal is recorded;
a level signal continuous output module configured to: and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip.
In one embodiment, the enable signal issuing module includes:
a temperature detection unit configured to: when a starting-up trigger signal is detected, the temperature of the antenna control chip is obtained through a temperature detection device;
a temperature determination unit configured to: judging whether the temperature of the antenna control chip exceeds a preset temperature or not;
an enable signal issuing unit configured to: if the temperature of the antenna control chip exceeds the preset temperature, an enabling signal is sent to the antenna control chip once at preset time intervals, and the total times of sending the enabling signal are recorded.
The present disclosure further provides an overcurrent protection method for an antenna control chip, including:
when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip, and judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if the level output by the antenna control chip is low level, sending an enabling signal to the antenna control chip;
after the enabling signal is sent out, waiting for a period of time, obtaining the detection result of the level detection device on the output level of the antenna control chip again, and judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if yes, repeating the first two steps;
if not, the level signal for maintaining the normal work of the antenna control chip is continuously output.
The present disclosure additionally provides a satellite television receiver, comprising:
the antenna control chip is used for providing a control signal and a power supply for the satellite antenna;
a master chip, the master chip comprising:
a memory for storing a computer program;
a processor for executing the computer program stored by the memory to implement the method according to any of the above.
In one embodiment, the satellite television receiver further comprises level detection means for detecting an output level of the antenna control chip, the level detection means being electrically connected to an output terminal of the antenna control chip and the processor, respectively, to transmit a detection result of the antenna control chip to the processor.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
when a trigger signal of starting is detected, an enabling signal of preset times is sent to the antenna control chip, so that the antenna control chip is repeatedly reset during the starting, the motor is intermittently charged through enabling the antenna control chip for multiple times, the electric quantity stored by the motor is gradually increased along with the increase of the charging times of the motor, the current required to be extracted by the motor is gradually reduced, the impact current output by the antenna control chip is also gradually reduced, when the amplitude of the impact current is smaller than the current critical value of self-locking, the antenna control chip does not start the self-locking any more, and the normal work of the antenna control chip after the starting is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic flow chart illustrating an overcurrent protection method of an antenna control chip according to an embodiment of the present disclosure;
FIG. 2 shows a schematic circuit diagram of the main chip and the antenna control chip;
FIG. 3 is a waveform diagram of an enable signal, a surge current signal and a signal output by an output terminal of the antenna control chip, which are output by the main chip and shown by the oscilloscope;
FIG. 4 illustrates a flowchart of step S120 in one embodiment of the method corresponding to FIG. 1;
fig. 5 shows a schematic flow diagram of step S120 in a further embodiment of the method embodiment corresponding to fig. 1;
fig. 6 shows a block diagram of an overcurrent protection device of an antenna control chip according to one embodiment of the present disclosure;
FIG. 7 illustrates a block diagram that enables a signal issuing module in one embodiment;
FIG. 8 shows a block diagram of an enable signal issuing module in another embodiment;
fig. 9 is a schematic flowchart illustrating an overcurrent protection method of an antenna control chip according to another embodiment of the present disclosure;
fig. 10 shows a block diagram of an overcurrent protection apparatus of an antenna control chip according to another embodiment of the present disclosure.
Detailed Description
For further explanation of the principles and construction of the present disclosure, reference will now be made in detail to the preferred embodiments of the present disclosure, which are illustrated in the accompanying drawings.
As described above, when the satellite television receiver is turned on, the motor is charged instantaneously to draw a current, so that the antenna control chip generates a large impact current instantaneously (the impact value of the current reaches 1.224A), and when the impact current reaches a critical current value of the antenna control chip for self-protection, the antenna control chip starts self-locking to enter a self-protection state, so that the antenna control chip cannot recover to normal operation. In order to solve the problem, the disclosure provides an overcurrent protection method for an antenna control chip. The main body of execution of the method is the main chip (which includes a processor and a memory) in the satellite television receiver.
Specifically, as shown in fig. 1, the method includes the following steps:
and step 110, when the trigger signal of starting up is detected, sending an enabling signal to the antenna control chip once at preset time intervals, and recording the total times of sending the enabling signal.
When the satellite television receiver is powered on but the start button is not pressed, the processor of the main chip starts to perform part of the work, for example, detecting a trigger signal for power-on. After the power-on trigger signal is detected, step 120 is executed.
The trigger signal may be a signal with a level change, for example, a signal with a high level changing to a low level, or a signal with a low level changing to a high level.
When the main chip detects a trigger signal for power-on, for example, a level change signal, the main chip intermittently sends a plurality of enable signals to the enable port of the antenna control chip. The enable signal may be a pulse signal or a high level signal. When the enable signal is a high level signal, intermittently issuing a plurality of enable signals means: the main chip outputs high level to the antenna control chip, is disconnected after a preset time, and re-sends the enable signal after being disconnected for a period of time.
In one embodiment, the duration of each enable signal is slightly longer than the preset time length, and the preset time length is the time required for the antenna control chip to enter the self-locking state. For example, the preset time length is 6 ms. The antenna control chip starts to work after receiving the enabling signal, the motor also starts to draw current, impact current is generated in the antenna control chip, if the impact current reaches the critical current value of the antenna control chip for self protection, and the duration time of the impact current reaches the time length required by the antenna control chip to enter self locking, the antenna control chip enters self locking, the motor can not draw current any more, and the motor stops working after working for a period of time. The main chip enables the antenna control chip again, the antenna control chip starts to work again, the motor starts to draw current again, at the moment, because the motor already draws partial current at the previous time, the current required to be drawn by the motor is reduced, the impact current generated by the corresponding antenna control chip is also reduced to some extent, but if the impact current can also meet the self-locking condition of the antenna control chip, the antenna control chip can still be self-locked, and the motor stops after working for a period of time. The master chip is enabled again and the above steps are repeated. After repeating for several times, the electric quantity continuously collected in the motor is close to saturation, and when the motor is electrified again, the impact current of the antenna control chip brought by the current drawn by the motor cannot meet the self-locking condition, so that the antenna control chip can continuously supply power for the motor.
Because the antenna control chip is restarted each time, the chip can generate heat, the temperature of the antenna control chip is increased, and the antenna control chip is influenced to a certain extent. Therefore, it is desirable to reduce the number of times the antenna control chip is restarted, i.e., the motor draws as much current per time as possible.
Optionally, the duration of the enable signal sent each time is designed to be slightly longer than the time required by the antenna control chip to enter the self-locking state, so that the antenna control chip can charge the motor to the maximum extent before self-locking, the number of enabling times can be reduced, and the problem of heating caused by excessive motor charging times can be avoided.
Therefore, the antenna control chip is reset for many times when being started, and the phenomenon that the antenna control chip cannot be recovered due to self locking when being started can be avoided.
Specifically, as shown in fig. 2, the output interface GPIO-PM7 of the main chip 11 is electrically connected to the enable port EN of the antenna control chip 12. In addition, the output interface GPIO-PM8 of the main chip 11 is electrically connected to the SEL port of the antenna control core, and the output interface GPIO-PM9 of the main chip 11 is electrically connected to the TONE port of the antenna control core. The output end LNB-POWER of the antenna control chip 12 is connected to a tuner 13 (wherein the tuner includes a motor) of the satellite antenna.
The master chip 11 intermittently issues the enable signal. Referring to fig. 3, a waveform S1 is a waveform output by the output interface GPIO-PM7 of the main chip 11, a waveform S2 is a surge current waveform output by the antenna control chip at the moment of power-on, and a waveform S3 is a voltage waveform output by the antenna control chip at the moment of power-on, as can be seen from fig. 3, at the moment of power-on, the main chip 11 outputs 4 high levels to the enable port EN of the antenna control chip 12 at predetermined intervals, that is, after the high level output by the main chip 11 to the antenna control chip 12 is maintained for a period of time, the output of the high level is stopped, after the output of the high level is stopped for a period of time, the high level is output to the enable port EN of the antenna control chip 12 again, and the cycle is repeated for 4 times, where the output waveform appears as four pulse signals (as shown in waveform S1).
When the antenna control chip 12 receives the enable signal and enters the operating state, the antenna control chip 12 outputs the impact current, as shown in a waveform S2 in fig. 3, the impact current output by the antenna control chip 12 gradually decreases and approaches 0 before the enable signal is turned off, that is, when the duration of the enable signal is longer than the time required for the antenna control chip 12 to enter the self-locking state, the antenna control chip enters the self-locking state, the impact current output by the antenna control chip 12 sharply decreases and approaches 0, at this time, the main chip 11 suspends outputting the high level to the enable port EN of the antenna control chip 12, and the waveform S1 shows the low level, and after the duration of the waveform S1 lasts for a while, the high level is output to the enable port EN of the antenna control chip 12 again. The antenna control chip 12 enters the operating state after receiving the enable signal again, and outputs the impulse current, because the motor has already drawn part of the current at the previous time, the current that the motor needs to draw decreases, and the amplitude of the impulse current generated by the corresponding antenna control chip also decreases, therefore, the waveform S2 shows that the amplitude of the impulse current that is output gradually decreases with the increase of the number of times of enabling the antenna control, and after four times of enabling, the current has already dropped below the safety line (i.e. below 500 mA) (as shown in the waveform S2, the amplitude of the output current is much smaller than the impulse current before enabling), and the antenna control chip 12 does not enter the self-locking state.
Each time the antenna control chip 12 is enabled, that is, during the period when the main chip 11 outputs a high level to the enable port EN of the antenna control chip 12, the voltage output by the antenna control chip 12 reaches the maximum output voltage (that is, 18V), and after a certain time, the output voltage is pulled down to 0 because the antenna control chip enters a self-locking state. When the master chip 11 outputs a high level to the enable port EN of the antenna control chip 12 again, the voltage output by the antenna control chip 12 reaches the maximum output voltage again, and the output waveform appears as four high level pulses (as shown by a waveform S3). After four times of enabling, the antenna control chip 12 outputs no pulse voltage, but outputs the voltage of 13V or 18V required for maintaining the polarization of the satellite antenna, and the waveform shows that the voltage of 13V or 18V is alternately output (as shown by the waveform S3).
Thus, the antenna control chip 12 is repeatedly reset during the period of the impulse current drawn by the motor, and the motor is intermittently charged by enabling the antenna control chip for many times, so that the impulse current output by the antenna control chip is gradually reduced, and the phenomenon that the current output by the antenna control chip is too large and enters self-locking is avoided.
The predetermined time interval is pre-stored in a configuration file of the main chip, and the configuration file can be programmed in a storage of the main chip when the main program is programmed, and the storage can be a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM) or other storage media. The predetermined time of the interval is determined manually and empirically. The time of the interval may be 6ms or 7 ms.
The total number of times is: and recording the total times of the currently sent enable signals after the master chip sends the enable signals each time. The total number of times is 0 in the initial state, and the total number of times is increased by one every time the main chip sends out an enable signal, for example, if the main chip sends out an enable signal for 3 times, the total number of times recorded as sending out the enable signal is 3 times.
And step 120, when the total number of the recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip.
The preset number is the maximum number of times the main chip emits the enable signal. If the total number of times of the enable signal sent by the main chip reaches the preset number, the output of the generated antenna control chip is restored to a normal state, and the main chip can continuously output a level signal for maintaining the normal work of the antenna control chip without discontinuously sending the enable signal. The level signal may be a high level signal or a low level signal.
The preset times and the preset time of the interval are stored in the configuration file of the main chip in advance, the configuration file can be burnt in the storage of the main chip when the main program is burnt, and the storage can be a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM) or other storage media. The preset number of times is manually and empirically determined. The preset number of times may be 4-6 times.
Therefore, when the main chip detects a trigger signal of starting, the main chip sends an enabling signal of a preset number of times to the antenna control chip, so that the antenna control chip can be repeatedly reset in the period of generating impact current at the moment of starting, the motor is intermittently charged through multiple times of resetting, the electric quantity stored by the motor is gradually increased along with the increase of the charging number of the motor, the current required to be extracted by the motor is gradually reduced, the impact current output by the antenna control chip is also gradually reduced, when the amplitude of the impact current is smaller than the current critical value of self-locking, the antenna control chip does not start self-locking any more, and the normal work of the antenna control chip after starting can be effectively ensured.
In another embodiment, as shown in fig. 4, the step 110 further includes:
and step 111, when the trigger signal of starting up is detected, obtaining the temperature of the antenna control chip through the temperature detection device.
The temperature detection device is used for detecting the surface temperature of the antenna control chip, and can be a sensor or a temperature detection circuit consisting of a capacitor, a resistor, a triode and a temperature detection chip. And a temperature detecting means connected to the main chip 11 through an I2C interface of the main chip 11, the temperature detecting means detecting a surface temperature of the antenna control chip and transmitting the detected temperature to the main chip 11, whereby the main chip 11 acquires the temperature of the antenna control chip through the temperature detecting means.
And 113, judging whether the temperature of the antenna control chip exceeds a preset temperature, if so, executing the step 115, otherwise, not executing any action, and ending.
The preset temperature is pre-stored in a configuration file of the main chip, and the configuration file can be programmed in a storage of the main chip when the main program is programmed, and the storage can be a Random Access Memory (RAM), a Read Only Memory (ROM), an erasable programmable read only memory (EPROM or flash memory), a Static Random Access Memory (SRAM) or other storage media. The value of the preset temperature is manually and empirically determined.
The temperature of the surface of the antenna control chip is in direct proportion to the current generated by the antenna control chip, namely, the higher the temperature of the antenna control chip is, the larger the current generated by the antenna control chip is, when the current reaches the self-protection current threshold of the antenna control chip, namely, when the temperature of the antenna control chip exceeds the preset temperature, the antenna control chip is self-locked and cannot be recovered. Under the condition, corresponding measures need to be taken for the antenna control chip to enable the antenna control chip to recover to normal operation.
On the contrary, the temperature of the antenna control chip is low, the corresponding self-generated current is also small, and the current cannot naturally reach the self-protection current threshold of the antenna control chip, namely, the temperature of the antenna control chip cannot exceed the preset temperature, and the antenna control chip cannot be self-locked. In this case, it is not necessary to take corresponding measures for the antenna control chip.
The main chip compares the temperature obtained by the temperature detection device with a preset temperature, and judges whether to execute the next step 115 according to the comparison result.
And step 115, sending an enabling signal to the antenna control chip once every preset time, and recording the total times of sending the enabling signal.
If the temperature of the antenna control chip exceeds the preset temperature, the main chip sends an enabling signal to the antenna control chip once every preset time interval, so that the antenna control chip is repeatedly reset, the motor is intermittently charged by resetting the antenna control chip for many times, the electric quantity stored by the motor is gradually increased along with the increase of the charging times of the motor, the current required to be extracted by the motor is gradually reduced, the impact current output by the antenna control chip is also gradually reduced, and when the amplitude of the impact current is smaller than the current critical value of self-locking, the antenna control chip does not start self-locking any more. The master chip records the total number of times the enable signal is issued, simultaneously with or after the enable signal is issued.
In this embodiment, the main chip obtains the temperature of the antenna control chip through the temperature detection device to determine whether to send the enable signal to the antenna control chip, and sends the enable signal when the temperature exceeds the preset temperature, and does not perform any processing when the temperature does not exceed the preset temperature.
In another embodiment, as shown in fig. 4, the step 110 further includes:
and step 112, when the trigger signal of starting up is detected, obtaining the detection result of the level detection device on the output level of the antenna control chip.
The level detection device is used for detecting the level of the output end LNB-POWER of the antenna control chip. The level detection device can be a level detection circuit consisting of a capacitor, a resistor, a triode and a temperature detection chip, and can also be integrated in a main chip. The output end and the control end of the level detection device are connected with the main chip, and the input end of the level detection device is electrically connected with the antenna control chip. Specifically, the level detection device may be connected to the main chip 11 through an I2C interface of the main chip 11, and an input end of the level detection device is connected to the output end LNB-POWER of the antenna control chip.
The detection result refers to a result of whether the level signal detected by the level detecting means is at a high level or a low level. The level detection device outputs different signals according to different detection results and feeds the signals back to the main chip 11, for example, when the level signal detected by the level detection device is a low level, the level detection device outputs a high level to the main chip 11; when the level signal detected by the level detection means is high level, the level detection means outputs a low level to the main chip 11.
When a starting-up trigger signal is detected, the main chip controls the level detection device to work, and the level state output by the output end LNB-POWER of the antenna control chip is obtained through detection of the level detection device.
And step 114, judging whether the level output by the antenna control chip is a low level according to the detection result of the level detection device, if so, executing step 116, otherwise, not performing any action, and ending.
The level detection device outputs different signals according to different detection results, and the main chip judges whether the high level or the low level is output by the antenna control chip according to the received different signals sent by the level detection device; when the signal sent by the level detection device received by the main chip is low level, the voltage output by the antenna control chip is judged to be high level.
If the level output by the antenna control chip is high level, it indicates that the voltage at the output end of the current antenna control chip is not pulled low, the antenna control chip is in a normal working state and does not enter into self-locking, and the antenna control chip can work normally.
If the level output by the antenna control chip is low level, the voltage of the output end of the current antenna control chip is pulled low, the antenna control chip is in an abnormal state, and the antenna control chip enters self-locking. In this case, the master chip is required to perform the next step 116.
And step 116, sending an enabling signal to the antenna control chip once every preset time, and recording the total times of sending the enabling signal.
If the level output by the antenna control chip is low level, the main chip sends an enabling signal to the antenna control chip once at intervals of preset time, so that the antenna control chip is reset repeatedly, the motor is charged intermittently by enabling the antenna control chip for many times, the electric quantity stored by the motor is increased gradually along with the increase of the charging times of the motor, the current required to be extracted by the motor is reduced gradually, the impact current output by the antenna control chip is also reduced gradually, when the amplitude of the impact current is smaller than the current critical value of self-locking, the antenna control chip does not start self-locking any more, and the normal work of the antenna control chip after starting is further ensured. And the master chip records the total number of times the enable signal is issued, simultaneously with or after the enable signal is issued.
In this embodiment, the main chip determines whether to send the enable signal to the antenna control chip by obtaining the state of the output level of the antenna control chip through the level detection device, sends the enable signal when the antenna control chip outputs a low level, and does not perform any processing when the antenna control chip outputs a high level. Fig. 6 shows a block diagram of an overcurrent protection device of an antenna control chip according to an embodiment of the present disclosure. The apparatus is adapted to perform the method embodiments as described above.
In one embodiment, the overcurrent protection apparatus 100 of the antenna control chip is implemented in a satellite television receiver, and performs all or part of the steps of the embodiments of the overcurrent protection method of the antenna control chip. As shown in fig. 6, the apparatus may include:
an enable signal issuing module 160 configured to: when a trigger signal of starting up is detected, an enabling signal is sent to an antenna control chip once at preset time intervals, and the total times of sending the enabling signal is recorded;
a level signal continuous output module 170 configured to: and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip.
In one embodiment, as shown in connection with fig. 7, the enable signal issuing module 160 includes:
a temperature detection unit 161 configured to: when a starting-up trigger signal is detected, the temperature of the antenna control chip is obtained through a temperature detection device;
a temperature determination unit 163 configured to: judging whether the temperature of the antenna control chip exceeds a preset temperature or not;
an enable signal issuing unit 165 configured to: if the temperature of the antenna control chip exceeds the preset temperature, an enabling signal is sent to the antenna control chip once at preset time intervals, and the total times of sending the enabling signal are recorded.
In one embodiment, as shown in connection with fig. 8, the enabling signal issuing module 160 includes:
a level detection unit 162 configured to: when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip;
a level judging unit 164 configured to: judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
a signal issuing unit 166 configured to: if the output level of the antenna control chip is low level, an enable signal is sent to the antenna control chip once every preset time, and the total times of sending the enable signal is recorded.
The implementation processes and the relevant details of the functions and actions of the modules in the above device are specifically referred to the implementation processes of the corresponding steps in the above method embodiments, and are not described herein again.
In another embodiment, the present disclosure further provides another over-current protection method for an antenna control chip, where the over-current protection method detects in advance whether the antenna control chip will start self-locking, and if so, the main chip sends an enable signal to the antenna control chip again to restart the antenna control chip, and after the enable signal is sent, waits for a period of time to detect again whether the antenna control chip will still perform self-locking, and if so, enables several times until the antenna control chip no longer enters self-locking. Specifically, as shown in fig. 9, the method includes the following steps:
The level detection device outputs different signals according to different detection results, and the main chip judges whether the output voltage of the antenna control chip is high level or low level according to the received different signals, for example, when the signal received by the main chip is high level, the output voltage of the antenna control chip is judged to be low level; when the signal received by the main chip is low level, the voltage output by the antenna control chip is judged to be high level.
The level detection device is the level detection device in step 112, and the level detection device will not be described in detail again.
In step 220, if the output level of the antenna control chip is low, an enable signal is sent to the antenna control chip again.
If the level output by the antenna control chip is low level, the antenna control chip is in a self-locking state and needs to be recovered. Wherein, sending the enable signal to the antenna control chip again means: the output of the signal to the enable end of the antenna control chip is stopped first, so that the antenna control chip is in a dormant state, and after the output of the signal to the antenna control chip is stopped for a period of time, the enable signal is output to the antenna control chip again. For example, when the antenna control chip is enabled at a high level, the output of the high level signal to the enable terminal of the antenna control chip is stopped first, so that no level signal is input to the enable terminal of the antenna control chip, and after a certain period of time, the high signal is output to the antenna control chip again, so that the antenna control chip starts operating again.
After the antenna control chip enters the self-locking state, the antenna control chip can be restarted by sending an enabling signal to the antenna control chip again, so that the antenna control chip starts to work again, and the motor extracts current again.
After the enabling signal is sent out, a waiting time is needed, the waiting time is slightly longer than the time needed by the antenna control chip to enter the self-locking state, that is, the waiting time is needed to ensure that the main chip can accurately judge whether the antenna control chip can still enter the self-locking state through the detection result of the level detection device. If so, the above steps 220 and 230 are repeated. If not, go to step 240.
And step 240, continuously outputting a level signal for normal operation of the antenna control chip.
When the level output by the antenna control chip is high level, the antenna control chip enters a normal working state and does not enter a self-locking state any more, so that the main chip can continuously output a level signal for maintaining the normal working of the antenna control chip to the enabling end of the antenna control chip; if the antenna control chip is enabled at low level, the main chip continuously outputs low level to the enable end of the antenna control chip, so that the antenna control chip maintains working state.
In this embodiment, the main chip determines whether to send the enable signal to the antenna control chip by obtaining the state of the output level of the antenna control chip through the level detection device, so as to respectively adopt corresponding processing modes for different situations of the antenna control chip at the moment of starting up, thereby achieving the purposes of saving resources and better protecting the antenna control chip.
Fig. 10 shows a block diagram of an overcurrent protection apparatus of an antenna control chip according to another embodiment of the present disclosure. The device is used for executing the method in the steps 210-240.
As shown in fig. 10, the apparatus may include:
a first detection and determination module 250 configured to: when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip, and judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
a primary enable signal transmission module 260 configured to: if the level output by the antenna control chip is low level, sending an enabling signal to the antenna control chip again;
a second detection and determination module 270 configured to: after the enabling signal is sent out, waiting for a period of time, obtaining the detection result of the level detection device on the output level of the antenna control chip again, judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device, and if so, enabling the first enabling signal sending module and the second detection and judgment module to execute corresponding steps; if not, executing the step of outputting a level signal for maintaining the normal work of the antenna control chip.
A normal operating level signal output module 280 configured to: and continuously outputting a level signal for maintaining the normal operation of the antenna control chip.
According to an example embodiment, the apparatus may be implemented as a satellite television receiver including an antenna control chip and a main chip including a memory and a processor. The satellite television receiver also comprises a box-shaped shell and a plurality of interfaces arranged on the box-shaped shell, the interfaces can be a signal input interface, a signal output interface, a power interface or other interfaces, the antenna control chip and the main chip are arranged in the box-shaped shell, and the output end of the antenna control chip is connected with one interface on the box-shaped shell. The antenna control chip is electrically connected with the processor, and the output end of the antenna control chip is electrically connected with a tuner of the satellite antenna through a signal connecting wire and used for providing a control signal and a power supply for the satellite antenna. The memory has stored therein a computer program which, when executed by the processor, causes the processor to perform any one of the method embodiments described above, or which, when executed by the processor, causes the satellite television receiver to carry out the functions carried out by the constituent modules of the apparatus embodiments described above.
According to an exemplary embodiment, the satellite television receiver further comprises a temperature detection device for detecting the temperature of the antenna control chip, the temperature detection device being in electrical signal connection with the processor to transmit the detection result to the processor.
According to an exemplary embodiment, the satellite television receiver further includes level detecting means for detecting an output level of the antenna control chip, the level detecting means being electrically connected to the output terminal of the antenna control chip and the processor, respectively, to transmit a detection result of the antenna control chip to the processor.
The processor described in the above embodiments may refer to a single processing unit, such as a central processing unit CPU, or may be a distributed processor system comprising a plurality of distributed processing units.
The memory described in the above embodiments may include one or more memories, which may be internal memories of the computing device, such as various memories of a transient or non-transient type, or external storage devices connected to the computing device through a memory interface.
The above description is only for the purpose of illustrating the preferred embodiments of the present disclosure and is not to be construed as limiting the scope of the present disclosure, but rather is intended to cover all equivalent structural changes made by applying the teachings of the present disclosure to the accompanying drawings.
Claims (9)
1. An overcurrent protection method of an antenna control chip is characterized by comprising the following steps:
when a trigger signal of starting up is detected, an enabling signal is sent to an antenna control chip once at preset time intervals, and the total times of sending the enabling signal is recorded; when the antenna control chip receives an enabling signal to enter a working state and is not self-locked, a motor connected with the antenna control chip draws current from the output end of the antenna control chip, after the time for drawing the current of the motor reaches the time length required by the antenna control chip to enter self-locking, the antenna control chip enters self-locking, the antenna control chip receives the enabling signal to restart, and the motor draws part of current every time the antenna control chip is enabled; the enabling signal is a high-level signal or a low-level signal, the duration of the enabling signal sent each time is longer than a preset time length, and the preset time length is the time required by the antenna control chip to enter a self-locking state;
and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip, wherein after the motor passes through the current extraction for the preset number, the electric quantity stored by the motor is close to saturation.
2. The overcurrent protection method for the antenna control chip according to claim 1, wherein the step of issuing an enable signal to the antenna control chip every predetermined time interval and recording the total number of times the enable signal is issued when the trigger signal for power-on is detected comprises:
when a starting-up trigger signal is detected, the temperature of the antenna control chip is obtained through a temperature detection device;
judging whether the temperature of the antenna control chip exceeds a preset temperature or not;
if yes, sending an enabling signal to the antenna control chip once at preset time intervals, and recording the total times of sending the enabling signal.
3. The overcurrent protection method of the antenna control chip according to claim 1, wherein the step of sending an enable signal to the antenna control chip once every predetermined time interval and recording the total number of times the enable signal is sent when the trigger signal for power-on is detected comprises:
when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip;
judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if yes, an enabling signal is sent to the antenna control chip once every preset time, and the total times of sending the enabling signal is recorded.
4. The over-current protection method for antenna control chip of claim 1,
the preset times are 4-6 times, the interval preset time is 6-7 ms, and the preset times and the interval preset time are pre-stored in a configuration file.
5. An overcurrent protection device of an antenna control chip is characterized by comprising:
an enable signal issuing module configured to: when a trigger signal of starting up is detected, an enabling signal is sent to an antenna control chip once at preset time intervals, and the total times of sending the enabling signal is recorded; when the antenna control chip receives an enabling signal to enter a working state and is not self-locked, a motor connected with the antenna control chip draws current from the output end of the antenna control chip, after the time for drawing the current of the motor reaches the time length required by the antenna control chip to enter self-locking, the antenna control chip enters self-locking, the antenna control chip receives the enabling signal to restart, and the motor draws part of current every time the antenna control chip is enabled; the enabling signal is a high-level signal or a low-level signal, the duration of the enabling signal sent each time is longer than a preset time length, and the preset time length is the time required by the antenna control chip to enter a self-locking state;
a level signal continuous output module configured to: and when the total number of recorded enabling signals reaches a preset number, continuously outputting a level signal for maintaining the normal work of the antenna control chip, wherein after the motor passes through the current extraction for the preset number, the electric quantity stored by the motor is close to saturation.
6. The over-current protection device of antenna control chip according to claim 5, wherein said enable signal issuing module comprises:
a temperature detection unit configured to: when a starting-up trigger signal is detected, the temperature of the antenna control chip is obtained through a temperature detection device;
a temperature determination unit configured to: judging whether the temperature of the antenna control chip exceeds a preset temperature or not;
an enable signal issuing unit configured to: if the temperature of the antenna control chip exceeds the preset temperature, an enabling signal is sent to the antenna control chip once at preset time intervals, and the total times of sending the enabling signal are recorded.
7. An overcurrent protection method of an antenna control chip is characterized by comprising the following steps:
when a starting-up trigger signal is detected, obtaining a detection result of a level detection device on the output level of the antenna control chip, and judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if the level output by the antenna control chip is low level, sending an enabling signal to the antenna control chip again; when the antenna control chip receives an enabling signal to enter a working state and is not self-locked, a motor connected with the antenna control chip draws current from the output end of the antenna control chip, after the time for drawing the current of the motor reaches the time length required by the antenna control chip to enter self-locking, the antenna control chip enters self-locking, the antenna control chip receives the enabling signal to restart, and the motor draws part of current every time the antenna control chip is enabled; the enabling signal is a high-level signal or a low-level signal, the duration of the enabling signal sent each time is longer than a preset time length, and the preset time length is the time required by the antenna control chip to enter a self-locking state;
after the enabling signal is sent out, waiting for a period of time, obtaining the detection result of the level detection device on the output level of the antenna control chip again, and judging whether the level output by the antenna control chip is a low level or not according to the detection result of the level detection device;
if yes, repeating the first two steps;
and if not, continuously outputting a level signal for maintaining the normal work of the antenna control chip, wherein after the motor draws current for the preset times, the electric quantity accumulated by the motor is close to saturation.
8. A satellite television receiver, comprising:
the antenna control chip is used for providing a control signal and a power supply for the satellite antenna;
a master chip, the master chip comprising:
a memory for storing a computer program;
a processor for executing the memory-stored computer program to implement the method of any of claims 1-4 and 7.
9. The satellite television receiver according to claim 8, further comprising a level detection device for detecting an output level of the antenna control chip, wherein the level detection device is electrically connected to the output terminal of the antenna control chip and the processor, respectively, to transmit a detection result of the antenna control chip to the processor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811095118.1A CN110933383B (en) | 2018-09-19 | 2018-09-19 | Overcurrent protection method and device for antenna control chip and satellite television receiver |
| PCT/CN2019/106158 WO2020057493A1 (en) | 2018-09-19 | 2019-09-17 | Overcurrent protection method and television receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811095118.1A CN110933383B (en) | 2018-09-19 | 2018-09-19 | Overcurrent protection method and device for antenna control chip and satellite television receiver |
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| CN110933383A CN110933383A (en) | 2020-03-27 |
| CN110933383B true CN110933383B (en) | 2022-04-29 |
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| CN110933383A (en) | 2020-03-27 |
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