CN110932532A - Ripple injection circuit for constant on-time control mode switching power supply - Google Patents

Abstract

The invention belongs to the field of power supplies, and particularly relates to a ripple injection circuit for a constant on-time control mode switching power supply. The scheme of the invention technically realizes that the ripple waves injected into the internal circuit are performed in the same phase with the switch switching, realizes the good performance of a constant on-time control mode, enlarges the application range of the capacitor in application, can use tantalum capacitors and ceramic capacitors, and simultaneously uses the internal circuit so as to save the area of a PCB (printed Circuit Board).

Description

Ripple injection circuit for constant on-time control mode switching power supply

Technical Field

The invention belongs to the field of power supplies, and particularly relates to a ripple injection circuit for a constant on-time control mode switching power supply.

Background

In the field of consumer electronics, various electronic devices need power supplies to maintain, and a switching power supply management chip is an indispensable part of an electronic system, wherein a switching power supply in a constant on-time control mode is well applied in the field of power supplies due to excellent load transient response and smooth working mode switching.

Under a constant on-time control mode architecture, a feedback voltage of an output voltage needs to be compared with a reference voltage to serve as a logic signal for starting an upper tube voltage, so that the feedback voltage of the output voltage can be kept consistent with the directivity of an inductive current generally, but a delay phenomenon occurs in an output ripple relative to a switch waveform due to the filtering effect of an output capacitor, so that the output ripple is smooth and has a delay, an error exists in a signal sent to a comparator, and the performance of a lower-level circuit is affected.

The first method is to use an appropriate ESR of an output capacitor to obtain an inductance ripple current ESR multiplied by Delta IL, the inductance ripple current ESR multiplied by Delta IL is used for leading an output voltage ripple to keep the variation of the ripple consistent with SW, the ripple is transferred and injected into a voltage division feedback resistance end of VOUT, namely an FB end, FB is compared with reference voltage, and when VFB is smaller than the reference voltage, a switching tube is quickly opened; the second method is to add a peripheral circuit, and inject the generated ripple current into the FB terminal by a resistor and a capacitor across two ends of an inductor of the system, so that the variation of the ripple generated by the FB terminal is consistent with the SW, thereby realizing the ripple injection effect.

However, in practical applications, the output capacitor may be a tantalum capacitor with a large ESR resistance, or a ceramic capacitor with a small ESR resistance, so that the ripple generated by the capacitor cannot meet the requirement of the circuit; meanwhile, with the reduction of the area of the PCB board in application and the simplification of the peripheral devices as much as possible, the method of generating the ripple injection current through the peripheral circuit is not practical.

Disclosure of Invention

In order to solve the above problems, the present invention provides a ripple injection circuit for a constant on-time controlled mode switching power supply, which includes a ripple injection circuit for a constant on-time controlled mode switching power supply, and is characterized by including a ripple voltage generation circuit and a ripple injection current generation circuit connected to an output terminal of the ripple voltage generation circuit.

As a further explanation of the above scheme, the ripple voltage generation circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor;

one end of the fifth resistor is connected with one end of a fourth resistor and the positive end of the first capacitor respectively, the negative end of the first capacitor is grounded, and the other end of the fourth resistor is connected with one end of a third resistor and one end of a second resistor respectively; the other end of the third resistor is grounded, and the other end of the second resistor is connected with the positive end of the second capacitor; and the negative end of the second capacitor is grounded.

As a further explanation of the above scheme, the ripple injection current generation circuit includes a first P-type triode, a second P-type triode, a first N-type triode, a second N-type triode, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, and a first resistor;

the base electrode of the first P-type triode is connected with a connection point of one end of a second resistor and the positive end of a second capacitor in the ripple voltage generating circuit, the collector electrode of the first P-type triode is connected with the ground, and the emitter electrode of the first P-type triode is simultaneously connected with the drain electrode of the first P-type MOS tube and the base electrode of the first N-type triode;

the base electrode of the second P-type triode is connected with the connection point of one end of a third resistor, one end of a fourth resistor and one end of a second resistor in the ripple voltage generating circuit, the collector electrode of the second P-type triode is connected with the ground, and the emitter electrode of the second P-type triode is simultaneously connected with the drain electrode of the second P-type MOS tube and the base electrode of the second N-type triode;

the base electrode of the first N-type triode is connected with the emitting electrode of the first P-type triode and the drain electrode of the first P-type MOS tube at the same time, the collector electrode of the first N-type triode is connected with the grid electrode of the third P-type MOS tube, the grid electrode of the fourth P-type MOS tube and the drain electrode of the fourth P-type MOS tube, and the emitting electrode of the first N-type triode is connected with the drain electrode of the third N-type MOS tube and one end of the first resistor;

the base electrode of the second N-type triode is simultaneously connected with the emitting electrode of the second P-type triode and the drain electrode of the second P-type MOS tube, the collector electrode of the second N-type triode is simultaneously connected with the grid electrode of the sixth P-type MOS tube, the grid electrode of the fifth P-type MOS tube and the drain electrode of the fifth P-type MOS tube, and the emitting electrode of the first N-type triode is simultaneously connected with the drain electrode of the fourth N-type MOS tube and the other end of the first resistor;

the drain electrode of the first P-type MOS tube is simultaneously connected with the emitter electrode of the first P-type triode and the base electrode of the first N-type NPN tube;

the drain electrode of the second P-type MOS tube is simultaneously connected with the emitter electrode of the second P-type triode and the base electrode of the second N-type triode;

the grid electrode of the third P-type MOS tube is simultaneously connected with the grid electrode of the fourth P-type MOS tube, the drain electrode of the fourth P-type MOS tube and the collector electrode of the first N-type triode; the drain electrode of the third P-type MOS tube is simultaneously connected with the drain electrode and the grid electrode of the first N-type MOS tube;

the grid electrode of the fourth P-type MOS tube is simultaneously connected with the grid electrode of the third P-type MOS tube, the drain electrode of the fourth P-type MOS tube and the collector electrode of the first N-type triode, and the drain electrode of the fourth P-type MOS tube is simultaneously connected with the grid electrode of the fourth P-type MOS tube, the grid electrode of the third P-type MOS tube and the collector electrode of the first N-type triode;

the grid electrode of the fifth P-type MOS tube is simultaneously connected with the grid electrode of the sixth P-type MOS tube, the drain electrode of the fifth P-type MOS tube and the collector electrode of the second N-type triode, and the drain electrode of the fifth P-type MOS tube is simultaneously connected with the grid electrode of the fifth P-type MOS tube, the grid electrode of the sixth P-type MOS tube and the collector electrode of the second N-type triode;

the grid electrode of the sixth P-type MOS tube is simultaneously connected with the grid electrode of the fifth P-type MOS tube, the drain electrode of the fifth P-type MOS tube and the collector electrode of the second N-type triode, and the drain electrode of the sixth P-type MOS tube is connected with the drain electrode of the second N-type MOS tube;

the grid electrode of the first N-type MOS tube is simultaneously connected with the drain electrode of the first N-type MOS tube, the drain electrode of the third P-type MOS tube and the grid electrode of the second N-type MOS tube, and the source electrode and the substrate of the first N-type MOS tube are both connected with the ground;

the grid electrode of the second N-type MOS tube is simultaneously connected with the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the drain electrode of the third P-type MOS tube, the drain electrode of the second N-type MOS tube is connected with the drain electrode of the sixth P-type MOS tube, and the source electrode and the substrate of the second N-type MOS tube are both connected with the ground;

the drain electrode of the third N-type MOS tube is simultaneously connected with the emitting electrode of the first N-type triode and one end of the first resistor, and the source electrode and the substrate of the third N-type MOS tube are both connected with the ground;

and the drain electrode of the fourth N-type MOS tube is simultaneously connected with the emitter electrode of the second N-type triode and the other end of the first resistor, and the source electrode and the substrate of the fourth N-type MOS tube are both connected with the ground.

The invention has the beneficial effects that: the scheme of the invention technically realizes that output ripples and switch switching are carried out in the same phase, realizes the good performance of a constant on-time control mode, enlarges the application range of the capacitor in application, can use a tantalum capacitor and a ceramic capacitor, and simultaneously uses an internal circuit so as to save the area of a PCB (printed circuit board).

Drawings

FIG. 1: ripple voltage generating circuit

FIG. 2: ripple injection current generating circuit

Detailed Description

The invention will be further explained with reference to the drawings and the embodiments.

Example 1:

the ripple injection circuit for the constant on-time control mode switching power supply includes a ripple voltage generating circuit consistent with the switching waveform SW and a ripple injection current generating circuit connected to the output end of the ripple voltage generating circuit.

With reference to fig. 1, the ripple voltage generating circuit includes a second resistor R2, a third resistor R515, a fourth resistor R517, a fifth resistor R521, a first capacitor CT, and a second capacitor C2; in the implementation process, the SW signal is divided by the third resistor R515, the fourth resistor R517, the fifth resistor R521 and the first capacitor CT. V1 is equivalent ripple signal, which is equivalent to a triangular wave signal, and the expression is as follows.

V2 is V1 low pass filtered, corresponding to a × output voltage Vout, where a <1 is a coefficient of the output voltage Vout. And the voltages of V2 and V1 are sent to a ripple injection current generation circuit to obtain the required ripple injection current.

The connection relationship is as follows: one end of the fifth resistor R521 is connected to one end of the fourth resistor R517 and the positive end of the first capacitor CT, the negative end of the first capacitor CT is grounded, and the other end of the fourth resistor R517 is connected to one end of the third resistor R515 and one end of the second resistor R2; the other end of the third resistor R515 is grounded, and the other end of the second resistor R2 is connected with the positive end of the second capacitor C2; the negative terminal of the second capacitor C2 is grounded; a connection point between one end of the fourth resistor R517 and one end of the third resistor R515 and one end of the second resistor R2 in the ripple voltage generation circuit is an output point V1, and a connection point between one end of the second resistor R2 and the positive terminal of the second capacitor C2 is an output point V2.

With reference to fig. 2, the ripple injection current generation circuit is similar to a transconductance operational amplifier, the input of which is equivalent proportional voltage V1 of VOUT and equivalent ripple voltage signal V2 of VOUT, and the ripple injection current generation circuit is used for converting the equivalent ripple voltage of VOUT obtained from the SW terminal into a current signal, the first stage of the amplifier is an emitter follower, the second stage is a symmetrical OTA, the input differential emitter has negative feedback of a resistor, and the transconductance of the amplifier is mainly determined by the resistor; the voltages V2 and V1 are sent to a current generating circuit to obtain: Δ iriple ═ V1-V2)/R1, a triangular wave ripple current consistent with the inductor current is obtained, that is, consistent with the inductor ripple current ESR × Δ IL, and this current is injected into the FB pin, so that ripple injection is realized; meanwhile, the size of the FB slope can be controlled by controlling the sizes of V1, V2 and a first resistor R1, and the jitter caused by noise when the FB passes through VREF is reduced, and the FB slope comprises a first P-type triode PNP1, a second P-type triode PNP2, a first N-type triode NPN1, a second N-type triode NPN2, a first P-type MOS tube MP1, a second P-type MOS tube MP2, a third P-type MOS tube MP3, a fourth P-type MOS tube MP4, a fifth P-type MOS tube MP5, a sixth P-type MOS tube MP6, a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a fourth N-type MOS tube MN4 and a first resistor R1.

The connection relationship is as follows: the base electrode of the first P-type triode PNP1 is connected with a connection point V1 between one end of a second resistor R2 and the positive end of a second capacitor C2 in the ripple voltage generating circuit, the collector electrode of the first P-type triode PNP1DE is connected with the ground, and the emitter electrode of the first P-type triode PNP DE is simultaneously connected with the drain electrode of the first P-type MOS tube MP1 and the base electrode of the first N-type triode NPN 1;

the base electrode of the second P-type triode PNP2 is connected with a connection point V2 of one end of a third resistor R515, one end of a fourth resistor R517 and one end of a second resistor R2 in the ripple voltage generating circuit, the collector electrode of the second P-type triode PNP2 is connected with the ground, and the emitter electrode of the second P-type triode PNP2 is simultaneously connected with the drain electrode of the second P-type MOS transistor MP2 and the base electrode of the second N-type triode NPN 2;

the base electrode of the first N-type triode NPN1 is connected with the emitting electrode of the first P-type triode PNP1 and the drain electrode of the first P-type MOS tube MP1 at the same time, the collector electrode of the first N-type triode NPN1 is connected with the grid electrode of the third P-type MOS tube MP3, the grid electrode of the fourth P-type MOS tube MP4 and the drain electrode of the fourth P-type MOS tube MP4, and the emitting electrode of the first N-type triode NPN1 is connected with the drain electrode of the third N-type MOS tube MN3 and one end of a first resistor R1;

a base electrode of the second N-type triode NPN2 is connected with an emitter electrode of the second P-type triode PNP2 and a drain electrode of the second P-type MOS transistor MP2 at the same time, a collector electrode of the second N-type triode NPN2 is connected with a gate electrode of the sixth P-type MOS transistor MP6, a gate electrode of the fifth P-type MOS transistor MP5 and a drain electrode of the fifth P-type MOS transistor MP5 at the same time, and an emitter electrode of the first N-type triode NPN1 is connected with a drain electrode of the fourth N-type MOS transistor MN4 and the other end of the first resistor R1 at the same time;

the grid electrode of the first P-type MOS tube MP1 is connected with bias voltage BIASP, the source electrode is connected with a power supply VDD, the substrate is connected with the power supply VDD, and the drain electrode of the first P-type MOS tube MP1 is simultaneously connected with the emitting electrode of the first P-type triode PNP1 and the base electrode of the first N-type triode NPN 1;

the grid electrode of the second P-type MOS tube MP2 is connected with bias voltage BIASP, the source electrode is connected with a power supply VDD, the substrate is connected with the power supply VDD, and the drain electrode of the second P-type MOS tube MP2 is simultaneously connected with the emitting electrode of the second P-type triode PNP2 and the base electrode of the second N-type triode NPN 2;

the grid electrode of the third P-type MOS transistor MP3 is simultaneously connected with the grid electrode of the fourth P-type MOS transistor MP4, the drain electrode of the fourth P-type MOS transistor MP4 and the collector electrode of the first N-type triode NPN 1; the source electrode is connected with a power supply VDD, the substrate is connected with the power supply VDD, and the drain electrode of the third P-type MOS tube MP3 is simultaneously connected with the drain electrode and the grid electrode of the first N-type MOS tube MN 1;

the grid electrode of the fourth P-type MOS tube MP4 is simultaneously connected with the grid electrode of the third P-type MOS tube MP3, the drain electrode of the fourth P-type MOS tube MP4 and the collector electrode of the first N-type triode NPN1, the source electrode of the fourth P-type MOS tube MP4 is connected with a power supply VDD, the substrate of the fourth P-type MOS tube MP4 is connected with the grid electrode of the fourth P-type MOS tube MP4, the grid electrode of the third P-type MOS tube MP3 and the collector electrode of the first N-type triode NPN 1;

the grid electrode of the fifth P-type MOS tube MP5 is simultaneously connected with the grid electrode of the sixth P-type MOS tube MP6, the drain electrode of the fifth P-type MOS tube MP5 and the collector electrode of the second N-type triode NPN2, the source electrode of the fifth P-type MOS tube MP5 is connected with a power supply VDD, the substrate of the fifth P-type MOS tube MP5 is connected with the grid electrode of the fifth P-type MOS tube MP5, the grid electrode of the sixth P-type MOS tube MP6 and the collector electrode of the second N-type triode NPN 2;

the grid electrode of the sixth P-type MOS transistor MP6 is simultaneously connected with the grid electrode of the fifth P-type MOS transistor MP5, the drain electrode of the fifth P-type MOS transistor MP5 and the collector electrode of the second N-type triode NPN2, the source electrode is connected with a power supply VDD, the substrate is connected with the power supply VDD, and the drain electrode of the sixth P-type MOS transistor MP6 is connected with the drain electrode of the second N-type MOS transistor MN 2;

the grid electrode of the first N-type MOS tube MN1 is simultaneously connected with the drain electrode of the first N-type MOS tube MN1, the drain electrode of the third P-type MOS tube MP3 and the grid electrode of the second N-type MOS tube MN2, and the source electrode and the substrate of the first N-type MOS tube MN1 are both connected with the ground;

the grid electrode of the second N-type MOS tube MN2 is simultaneously connected with the grid electrode of the first N-type MOS tube MN1, the drain electrode of the first N-type MOS tube MN1 and the drain electrode of the third P-type MOS tube MP3, the drain electrode of the second N-type MOS tube MN2 is connected with the drain electrode of the sixth P-type MOS tube MP6 and an input pin Iripple, and the source electrode and the substrate of the second N-type MOS tube MN2 are connected with the ground;

the drain electrode of the third N-type MOS transistor MN3 is simultaneously connected with the emitter electrode of the first N-type triode NPN1 and one end of the first resistor R1, and the source electrode and the substrate of the third N-type MOS transistor MN3 are both connected with the ground;

the gate of the fourth N-type MOS transistor MN4 is connected to the bias voltage BIASN, the drain is connected to the emitter of the second N-type triode NPN2 and the other end of the first resistor R1, and the source and the substrate of the fourth N-type MOS transistor MN4 are both connected to ground.

The commonly used ripple injection is to use an appropriate ESR of the output capacitor to obtain an inductor ripple current ESR × Δ IL, which is used to dominate the output voltage ripple to make the ripple variation consistent with SW, to inject the ripple transfer to the feedback resistor terminal of VOUT, i.e., FB terminal, to compare FB with VREF voltage, and to quickly open the switching tube when VFB < VREF.

The COT control technique relies on the ramp of FB crossing VREF to stabilize the system, and the ramp should be ensured to be large enough to reduce the jitter caused by FB noise, but in practical applications, it is desirable to use a ceramic capacitor with a small volume, and the ESR of the ceramic capacitor is small, so that the ripple control technique by the ESR of the output capacitor is not suitable.

The scheme of the invention technically realizes that the output ripple and the switch switching are carried out in the same phase, the voltages of V2 and V1 are sent to a ripple injection current generating circuit to obtain the required ripple injection current delta Iripple (V1-V2)/R1, the current is consistent with the triangular ripple current of the inductive current, namely, the current is consistent with the ESR multiplied by delta IL of the inductive ripple current, namely, the output ripple and the switch switching are carried out in the same phase, the current is injected into an FB pin to realize the ripple injection technology, and simultaneously, the size of an FB slope can be controlled by controlling the sizes of V1, V2 and a first resistor R1, and the jitter caused by noise when the FB passes through VREF is reduced.

By mixing: Δ Iripple ═ (V1-V2)/R1 is injected into the VFB terminal, and the superposed triangular wave is used for leading the output voltage ripple, so that the good performance of a constant on-time control mode is realized, the application range of the capacitor is expanded in application, the tantalum capacitor and the ceramic capacitor can be used, and the internal circuit is used so as to save the area of a PCB (printed Circuit Board).

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (3)

1. A ripple injection circuit for a constant on-time control mode switching power supply is characterized by comprising a ripple voltage generation circuit and a ripple injection current generation circuit connected with the output end of the ripple voltage generation circuit.

2. The ripple injection circuit for a constant on-time controlled mode switching power supply of claim 1, wherein the ripple voltage generation circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor;

one end of the fifth resistor is connected with one end of a fourth resistor and the positive end of the first capacitor respectively, the negative end of the first capacitor is grounded, and the other end of the fourth resistor is connected with one end of a third resistor and one end of a second resistor respectively; the other end of the third resistor is grounded, and the other end of the second resistor is connected with the positive end of the second capacitor; and the negative end of the second capacitor is grounded.

3. The ripple injection circuit for a constant on-time controlled mode switching power supply of claim 2, wherein the ripple injection current generating circuit comprises a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, and a first resistor;

the base electrode of the first P-type triode is connected with a connection point of one end of a second resistor and the positive end of a second capacitor in the ripple voltage generating circuit, the collector electrode of the first P-type triode is connected with the ground, and the emitter electrode of the first P-type triode is simultaneously connected with the drain electrode of the first P-type MOS tube and the base electrode of the first N-type triode;

the base electrode of the second P-type triode is connected with the connection point of one end of a third resistor, one end of a fourth resistor and one end of a second resistor in the ripple voltage generating circuit, the collector electrode of the second P-type triode is connected with the ground, and the emitter electrode of the second P-type triode is simultaneously connected with the drain electrode of the second P-type MOS tube and the base electrode of the second N-type triode;

the base electrode of the first N-type triode is connected with the emitting electrode of the first P-type triode and the drain electrode of the first P-type MOS tube at the same time, the collector electrode of the first N-type triode is connected with the grid electrode of the third P-type MOS tube, the grid electrode of the fourth P-type MOS tube and the drain electrode of the fourth P-type MOS tube, and the emitting electrode of the first N-type triode is connected with the drain electrode of the third N-type MOS tube and one end of the first resistor;

the base electrode of the second N-type triode is simultaneously connected with the emitting electrode of the second P-type triode and the drain electrode of the second P-type MOS tube, the collector electrode of the second N-type triode is simultaneously connected with the grid electrode of the sixth P-type MOS tube, the grid electrode of the fifth P-type MOS tube and the drain electrode of the fifth P-type MOS tube, and the emitting electrode of the first N-type triode is simultaneously connected with the drain electrode of the fourth N-type MOS tube and the other end of the first resistor;

the drain electrode of the first P-type MOS tube is simultaneously connected with the emitter electrode of the first P-type triode and the base electrode of the first N-type NPN tube;

the drain electrode of the second P-type MOS tube is simultaneously connected with the emitter electrode of the second P-type triode and the base electrode of the second N-type triode;

the grid electrode of the third P-type MOS tube is simultaneously connected with the grid electrode of the fourth P-type MOS tube, the drain electrode of the fourth P-type MOS tube and the collector electrode of the first N-type triode; the drain electrode of the third P-type MOS tube is simultaneously connected with the drain electrode and the grid electrode of the first N-type MOS tube;

the grid electrode of the fourth P-type MOS tube is simultaneously connected with the grid electrode of the third P-type MOS tube, the drain electrode of the fourth P-type MOS tube and the collector electrode of the first N-type triode, and the drain electrode of the fourth P-type MOS tube is simultaneously connected with the grid electrode of the fourth P-type MOS tube, the grid electrode of the third P-type MOS tube and the collector electrode of the first N-type triode;

the grid electrode of the fifth P-type MOS tube is simultaneously connected with the grid electrode of the sixth P-type MOS tube, the drain electrode of the fifth P-type MOS tube and the collector electrode of the second N-type triode, and the drain electrode of the fifth P-type MOS tube is simultaneously connected with the grid electrode of the fifth P-type MOS tube, the grid electrode of the sixth P-type MOS tube and the collector electrode of the second N-type triode;

the grid electrode of the sixth P-type MOS tube is simultaneously connected with the grid electrode of the fifth P-type MOS tube, the drain electrode of the fifth P-type MOS tube and the collector electrode of the second N-type triode, and the drain electrode of the sixth P-type MOS tube is connected with the drain electrode of the second N-type MOS tube;

the grid electrode of the first N-type MOS tube is simultaneously connected with the drain electrode of the first N-type MOS tube, the drain electrode of the third P-type MOS tube and the grid electrode of the second N-type MOS tube, and the source electrode and the substrate of the first N-type MOS tube are both connected with the ground;

the grid electrode of the second N-type MOS tube is simultaneously connected with the grid electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube and the drain electrode of the third P-type MOS tube, the drain electrode of the second N-type MOS tube is connected with the drain electrode of the sixth P-type MOS tube, and the source electrode and the substrate of the second N-type MOS tube are both connected with the ground;

the drain electrode of the third N-type MOS tube is simultaneously connected with the emitting electrode of the first N-type triode and one end of the first resistor, and the source electrode and the substrate of the third N-type MOS tube are both connected with the ground;

and the drain electrode of the fourth N-type MOS tube is simultaneously connected with the emitter electrode of the second N-type triode and the other end of the first resistor, and the source electrode and the substrate of the fourth N-type MOS tube are both connected with the ground.

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