CN110930911A - Monitoring method and monitoring system for display panel control circuit - Google Patents
Monitoring method and monitoring system for display panel control circuit Download PDFInfo
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- CN110930911A CN110930911A CN201911214048.1A CN201911214048A CN110930911A CN 110930911 A CN110930911 A CN 110930911A CN 201911214048 A CN201911214048 A CN 201911214048A CN 110930911 A CN110930911 A CN 110930911A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The application provides a monitoring method and a monitoring system of a display panel control circuit, wherein the control circuit comprises a power management integrated circuit, a time schedule controller and a first memory, wherein a second code and a cyclic redundancy code of the second code, which are required by the normal work of the power management integrated circuit, are prestored in the first memory; the monitoring method comprises the following steps: the time sequence controller reads a first code operated by the power management integrated circuit and calculates a cyclic redundancy code of the first code; then the time sequence controller checks the cyclic redundancy code of the first code and the cyclic redundancy code of the second code; and if the cyclic redundancy code of the first code is consistent with the cyclic redundancy code check result of the second code, continuing monitoring, otherwise, loading the second code to a storage area inside the power management integrated circuit by the time sequence controller so as to update the code in the storage area of the power management integrated circuit into the second code, thereby monitoring the working state of the power management integrated circuit in real time.
Description
Technical Field
The present disclosure relates to display panel technologies, and in particular, to a monitoring method and a monitoring system for a display panel control circuit.
Background
A Liquid Crystal Display (LCD) is a commonly used electronic Display device at present, a Power Management Integrated Circuit (PMIC) is a commonly used circuit in a DC-DC (direct current) circuit of the Display device, the PMIC is a programmable circuit and is internally provided with a code (code) for storing a code required during working, in the LCD panel Display, the code of the PMIC is changed due to some reasons, which causes the panel Display to be abnormal, if the code of the PMIC cannot be found in time after being changed, because the factors generally causing the panel Display to be abnormal are more, the process of checking the abnormal and solving the abnormal often consumes time and Power.
Therefore, a means for solving the above problems is urgently needed.
Disclosure of Invention
The application provides a monitoring method and a monitoring system of a display panel control circuit, and aims to monitor the working condition of the display panel control circuit in real time and automatically correct the monitored working condition when the working condition is abnormal.
In order to achieve the purpose, the technical scheme provided by the application is as follows:
the application provides a monitoring method of a display panel control circuit, wherein the control circuit comprises a power management integrated circuit, a time schedule controller and a first memory, and the monitoring method comprises the following steps:
step S10, the time schedule controller reads the first code operated by the power management integrated circuit, and calculates the cyclic redundancy code of the first code;
step S20, the timing controller reads a cyclic redundancy code of a second code required by the power management integrated circuit when the power management integrated circuit works normally, which is pre-stored in the first memory, and verifies the cyclic redundancy code of the first code and the cyclic redundancy code of the second code;
step S30, when the cyclic redundancy code of the first code is inconsistent with the check result of the cyclic redundancy code of the second code, the timing controller loads the second code pre-stored in the first memory to a storage area inside the power management integrated circuit to update the code in the storage area of the power management integrated circuit to the second code.
In the monitoring method of the present application, before the step S20, the monitoring method further includes the steps of: the time schedule controller downloads the second code from the first memory into a buffer of the time schedule controller.
In the monitoring method of the present application, the timing controller includes:
a cyclic redundancy code checking module, configured to check a cyclic redundancy code of the first code and a cyclic redundancy code of the second code;
and the loading module is used for loading the second code into the power management integrated circuit in a blank time period of a display frame of the display panel when the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code check result of the second code so as to update the code in the storage area of the power management integrated circuit into the second code.
In the monitoring method of the present application, the first memory is a charged erasable programmable read only memory or a flash memory.
In the monitoring method of the present application, the power management integrated circuit is connected to the timing controller via a first wire, and the timing controller is connected to the first memory via a second wire.
In the monitoring method of the application, the time schedule controller is provided with a test mode pin, and the time schedule controller is further used for switching a cyclic redundancy check mode to a test mode through the test mode pin.
In the monitoring method of the present application, in the cyclic redundancy check mode, the timing controller enters a normal download/upload/monitoring state; in the test mode, the time schedule controller stops downloading/uploading/monitoring operation, and the time schedule controller, the power management integrated circuit and the first memory are respectively subjected to read/write debugging operation through a jig.
In order to achieve the above object, the present application further provides a monitoring system for a display panel control circuit, including a power management integrated circuit, a timing controller and a first memory, wherein the power management integrated circuit is connected to the timing controller via a first wire, and the timing controller is connected to the first memory via a second wire;
the time schedule controller is used for reading a first code operated by the power management integrated circuit and calculating a cyclic redundancy code of the first code;
the first memory is used for prestoring a second code required by the normal work of the power management integrated circuit and a cyclic redundancy code of the second code;
the time sequence controller is further configured to verify the cyclic redundancy code of the first code and the cyclic redundancy code of the second code, and when the cyclic redundancy code of the first code and the cyclic redundancy code of the second code are inconsistent, the time sequence controller is configured to load the second code to a storage area inside the power management integrated circuit, so as to update the code in the storage area of the power management integrated circuit to the second code.
In the monitoring system of the present application, the timing controller is further configured to download the second code from the first memory into a buffer of the timing controller.
In the monitoring system of the present application, the timing controller includes:
a cyclic redundancy code checking module, configured to check a cyclic redundancy code of the first code and a cyclic redundancy code of the second code;
and the loading module is used for loading the second code into the power management integrated circuit in a blank time period of a display frame of the display panel when the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code check result of the second code so as to update the code in the storage area of the power management integrated circuit into the second code.
The beneficial effect of this application does: the monitoring method and the monitoring system for the display panel control circuit can monitor the working state of the power management integrated circuit in real time, and can still monitor the abnormity in the power management integrated circuit under the condition that the power management integrated circuit is in an abnormal state and the panel controller cannot identify the abnormity, and can automatically correct when the abnormity is monitored, so that the processing efficiency of the abnormity is improved, and manpower and material resources are saved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a monitoring method of a display panel control circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a monitoring system of a display panel control circuit according to an embodiment of the present disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases used in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals.
The application provides a monitoring method of a display panel control circuit, wherein the control circuit comprises a power management integrated circuit, a time schedule controller and a first memory. The power management integrated circuit is connected to the timing controller through a first wire, and the timing controller is connected to the first memory through a second wire. The power management integrated circuit is internally provided with a storage area, and the storage area is internally stored with a first code operated by the power management integrated circuit. The first memory is prestored with a second code required by the normal operation of the power management integrated circuit and a cyclic redundancy code of the second code.
In this embodiment, the power management integrated circuit is via I2C bus connectionThe time schedule controller is connected to the first memory through an SPI bus.
As shown in fig. 1, a flowchart of a monitoring method of a display panel control circuit according to an embodiment of the present application is provided. The monitoring method comprises the following steps:
in step S10, the timing controller reads a first code run by the power management integrated circuit and calculates a cyclic redundancy code of the first code.
When the control circuit is switched on, the time schedule controller firstly downloads a second code required by the normal work of the power management integrated circuit from the first memory, and loads the second code to the storage area in the power management integrated circuit, so that the second code is converted into a first code operated by the power management integrated circuit, and the power management integrated circuit starts to work normally.
When the power management integrated circuit starts to work, the time sequence controller reads a first code running inside the power management integrated circuit in real time and calculates a cyclic redundancy code of the first code.
It can be understood that, when the second code is loaded into the power management integrated circuit by the timing controller, the second code loaded into the power management integrated circuit is converted into the first code for maintaining the operation of the power management integrated circuit, at this time, the first code and the second code are the same, but the first code is changed due to some reasons during the operation of the power management integrated circuit, so that the operation of the power management integrated circuit is abnormal.
In step S20, the timing controller reads the cyclic redundancy code of the second code, which is pre-stored in the first memory and is required by the power management integrated circuit when the power management integrated circuit works normally, and verifies the cyclic redundancy code of the first code and the cyclic redundancy code of the second code.
While the timing controller calculates the cyclic redundancy code of the first code operated by the power management integrated circuit, the timing controller reads the cyclic redundancy code of the second code from the first memory into a first buffer of the timing controller, and the first buffer can be a dynamic memory buffer.
The time sequence controller comprises a cyclic redundancy code checking module and a loading module, wherein the cyclic redundancy code checking module is used for checking the cyclic redundancy codes of the first code and the second code.
Specifically, the timing controller stores the calculated cyclic redundancy code of the first code into the first buffer, and stores the cyclic redundancy code of the second code read from the first memory into the first buffer. When the cyclic redundancy check module finds the starting bytes of the cyclic redundancy of the first code and the second code, the frame header moves from the starting bytes of the cyclic redundancy of the first code and the second code to the ending bytes respectively, and meanwhile, the cyclic redundancy check module checks the bytes of the cyclic redundancy of the first code and the cyclic redundancy of the second code corresponding to the frame header.
When the cyclic redundancy check results of the first code and the second code are consistent, the power management integrated circuit works normally, the time schedule controller continues to read the first code operated by the power management integrated circuit and calculate the cyclic redundancy of the first code, meanwhile, the time schedule controller continues to read the cyclic redundancy of the second code from the first memory to the first buffer of the time schedule controller, and the time schedule controller continues to perform cyclic redundancy check.
Step S30, when the cyclic redundancy code of the first code is inconsistent with the check result of the cyclic redundancy code of the second code, the timing controller loads the second code pre-stored in the first memory to a storage area inside the power management integrated circuit to update the code in the storage area of the power management integrated circuit to the second code.
When the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code of the second code, the power management integrated circuit is indicated to be abnormal in operation, and at this time, the timing controller downloads the second code from the first memory to a second buffer of the timing controller, where the second buffer may be a static random buffer.
The loading module loads the second code downloaded into the second buffer into the power management integrated circuit in a blank time period of a display frame of the display panel so as to update the code in the storage area of the power management integrated circuit into the second code, so that the second code can be automatically corrected when abnormal work is monitored, and the normal work of the power management integrated circuit is maintained.
When the time schedule controller monitors that the first code operated by the power management integrated circuit is abnormal, the time schedule controller at least executes 1 time of operation of loading the second code into the power management integrated circuit.
In one embodiment, the functions of the first buffer and the second buffer may be integrated, that is, the timing controller downloads the second code and the cyclic redundancy code of the second code from the first memory into the buffer of the timing controller for checking with the cyclic redundancy code of the first code, and loads the second code in the buffer into the power management integrated circuit when checking is not correct.
In this embodiment, the first memory may be a charged erasable programmable read only memory (EEPROM) or a flash memory (flash).
In this embodiment, the display panel control circuit can switch between a cyclic redundancy check mode and a test mode. The time sequence controller is provided with a test mode pin, and the time sequence controller can be switched from the cyclic redundancy code checking mode to the test mode through the test mode pin.
Specifically, in the cyclic redundancy check mode, the timing controller enters a normal downloading/uploading/monitoring state; in the test mode, the time schedule controller stops downloading/uploading/monitoring operation, and the time schedule controller, the power management integrated circuit and the first memory can be respectively debugged by externally connected jigs for reading/writing.
Typically the first code run by the power management integrated circuit is altered as follows: in the stage of turning on the power load codes, the time schedule controller can execute one-time downloading/uploading operation to initialize the codes of the power management integrated circuit; when the test mode is exited, the time schedule controller can execute a downloading/uploading operation again to update the codes of the power management integrated circuit. The method and the device can monitor the working condition of the display panel control circuit in real time, can automatically correct when monitoring that the work is abnormal, and improve the processing efficiency of the work abnormality.
The present application further provides a monitoring system of a display panel control circuit, as shown in fig. 2, which includes a power management integrated circuit 10, a timing controller 20 and a first memory 30, wherein the power management integrated circuit 10 is connected to a first conductive line (I)2C bus) is connected to the timing controller 20, and the timing controller 20 is connected to the first memory 30 via a second wire (SPI bus). The first memory 30 is pre-stored with a second code and a cyclic redundancy code of the second code required by the power management integrated circuit when the power management integrated circuit is operating normally.
The timing controller 20 is configured to read a first code executed by the power management integrated circuit 10 and calculate a cyclic redundancy code of the first code; the timing controller 20 is further configured to download the second code and the cyclic redundancy code of the second code from the first memory 30 into a buffer of the timing controller 20.
The timing controller 20 includes a cyclic redundancy check module 201 and a loading module 202, where the cyclic redundancy check module 201 is configured to check the cyclic redundancy of the first code and the cyclic redundancy of the second code. When the cyclic redundancy check result of the first code is not consistent with the cyclic redundancy check result of the second code, the timing controller 20 is configured to load the second code into a memory area inside the power management integrated circuit 10, so as to update the code in the memory area of the power management integrated circuit 10 to the second code.
Specifically, when the result of the cyclic redundancy check indicates that the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code of the second code, the loading module 202 is configured to load the second code into the power management integrated circuit 10 during a blank period of a display frame of the display panel to update the code in the memory area of the power management integrated circuit 10 to the second code.
The monitoring system can monitor the working condition of the display panel control circuit in real time, can automatically correct when abnormal work is monitored, and improves the processing efficiency of the abnormal work.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. A monitoring method of a display panel control circuit is characterized in that the control circuit comprises a power management integrated circuit, a time schedule controller and a first memory, and the monitoring method comprises the following steps:
step S10, the time schedule controller reads the first code operated by the power management integrated circuit, and calculates the cyclic redundancy code of the first code;
step S20, the timing controller reads a cyclic redundancy code of a second code required by the power management integrated circuit when the power management integrated circuit works normally, which is pre-stored in the first memory, and verifies the cyclic redundancy code of the first code and the cyclic redundancy code of the second code;
step S30, when the cyclic redundancy code of the first code is inconsistent with the check result of the cyclic redundancy code of the second code, the timing controller loads the second code pre-stored in the first memory to a storage area inside the power management integrated circuit to update the code in the storage area of the power management integrated circuit to the second code.
2. The monitoring method according to claim 1, wherein before the step S20, the monitoring method further comprises the steps of: the time schedule controller downloads the second code from the first memory into a buffer of the time schedule controller.
3. The monitoring method of claim 2, wherein the timing controller comprises:
a cyclic redundancy code checking module, configured to check a cyclic redundancy code of the first code and a cyclic redundancy code of the second code;
and the loading module is used for loading the second code into the power management integrated circuit in a blank time period of a display frame of the display panel when the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code check result of the second code so as to update the code in the storage area of the power management integrated circuit into the second code.
4. The method of claim 1, wherein the first memory is a flash memory or a charged-erasable programmable read-only memory.
5. The method of claim 1, wherein the power management integrated circuit is connected to the timing controller via a first wire, and the timing controller is connected to the first memory via a second wire.
6. The method according to claim 1, wherein a test mode pin is disposed on the timing controller, and the timing controller is further configured to switch from a crc mode to a test mode via the test mode pin.
7. The method as claimed in claim 6, wherein in the CRC mode, the timing controller enters a normal download/upload/monitor state; in the test mode, the time schedule controller stops downloading/uploading/monitoring operation, and the time schedule controller, the power management integrated circuit and the first memory are respectively subjected to read/write debugging operation through a jig.
8. A monitoring system of a display panel control circuit is characterized by comprising a power management integrated circuit, a time schedule controller and a first memory, wherein the power management integrated circuit is connected to the time schedule controller through a first lead, and the time schedule controller is connected to the first memory through a second lead;
the time schedule controller is used for reading a first code operated by the power management integrated circuit and calculating a cyclic redundancy code of the first code;
the first memory is used for prestoring a second code required by the normal work of the power management integrated circuit and a cyclic redundancy code of the second code;
the time sequence controller is further configured to verify the cyclic redundancy code of the first code and the cyclic redundancy code of the second code, and when the cyclic redundancy code of the first code and the cyclic redundancy code of the second code are inconsistent, the time sequence controller is configured to load the second code to a storage area inside the power management integrated circuit, so as to update the code in the storage area of the power management integrated circuit to the second code.
9. The monitoring system of claim 8, wherein the timing controller is further configured to download the second code from the first memory into a buffer of the timing controller.
10. The monitoring system of claim 8, wherein the timing controller comprises:
a cyclic redundancy code checking module, configured to check a cyclic redundancy code of the first code and a cyclic redundancy code of the second code;
and the loading module is used for loading the second code into the power management integrated circuit in a blank time period of a display frame of the display panel when the cyclic redundancy code of the first code is inconsistent with the cyclic redundancy code check result of the second code so as to update the code in the storage area of the power management integrated circuit into the second code.
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