CN110928585A - double-Flash switching system and method for server - Google Patents
double-Flash switching system and method for server Download PDFInfo
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- CN110928585A CN110928585A CN201911048991.XA CN201911048991A CN110928585A CN 110928585 A CN110928585 A CN 110928585A CN 201911048991 A CN201911048991 A CN 201911048991A CN 110928585 A CN110928585 A CN 110928585A
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- bmc
- chip
- gpo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/441—Multiboot arrangements, i.e. selecting an operating system to be loaded
Abstract
The invention relates to a double-Flash switching system and method of a server, comprising the following steps: a PCH south bridge chip; the PCH south bridge chip is connected to the BMC module through LPC bus signals, a WDT signal end of the BMC module is electrically connected to a WDT signal end of the CPLD chip module, and a GPO signal end of the BMC module is electrically connected to a GPI signal end of the CPLD chip module; a CS chip selection signal end of the PCH south bridge chip is electrically connected to an A signal receiving end of the Switch chip, an SEL signal receiving end of the Switch chip is electrically connected to a GPO signal end of the CPLD chip module, a B1 signal end of the Switch chip is electrically connected to a CS chip selection signal end of the main Flash, and a B2 signal end of the Switch chip is electrically connected to a CS chip selection signal end of the slave Flash; the PCH south bridge chip is also respectively connected to the master Flash and the slave Flash through the SPI bus.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a double-Flash switching system and method of a server.
Background
In the server system, Firmware programs such as BIOS image, ME image, LAN image, etc. are burned in a Flash chip, which is called Flash.
After a server mainboard is powered on, firmware in Flash provides the most basic hardware initialization and necessary programs for peripheral equipment control of the server; in addition to providing the bottom-most, most direct hardware settings and control to the server, the BIOS also provides the operating system with some system parameters and device information. The BIOS is a bridge for connecting bottom hardware and an upper operating system, and is a key ring for normal operation of the server. If the Flash fails, the service cannot normally run directly.
In the prior art, a server is usually configured with only one Flash, and if the Flash fails, the server cannot be normally started, so that the reliability of the server is not guaranteed.
Aiming at the problem, the design scheme of the double Flash servers is developed; however, the dual Flash server does not have a switching memory function, and when a Flash0 fault occurs, although the dual Flash server function can be logically switched to Flash1, each time the dual Flash server is restarted later, the dual Flash server tries to connect to Flash0 first, and switches to Flash1 after the Flash server fails. Thereby increasing the boot time and being inconvenient to use.
In the prior art, the Flash selection state of the last boot is recorded by an I/O Expander chip with a memory function. The IO Expander chip with the memory function is used, so that the cost is high, and the layout is not facilitated; the BMC controls the I/O expander by using an I2C bus, has large delay and low reliability. This is a disadvantage in the prior art.
In view of the above, the invention provides a dual Flash switching system and method for a server; to solve the above-mentioned drawbacks existing in the prior art; is very necessary.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a dual-Flash switching system and method of a server, so as to solve the technical problems.
In a first aspect, the present invention provides a dual Flash switching system for a server, including:
the system comprises a PCH south bridge chip, a Switch chip, a CPLD chip module, a BMC module, a main Flash module and a slave Flash module;
the PCH south bridge chip is connected to the BMC module through LPC bus signals, a WDT signal end of the BMC module is electrically connected to a WDT signal end of the CPLD chip module, and a GPO signal end of the BMC module is electrically connected to a GPI signal end of the CPLD chip module;
the CS chip selection signal end of the PCH south bridge chip is electrically connected to the A signal receiving end of the Switch chip, the SEL signal receiving end of the Switch chip is electrically connected to the GPO signal end of the CPLD chip module, the B1 signal end of the Switch chip is electrically connected to the CS chip selection signal end of the main Flash module, and the B2 signal end of the Switch chip is electrically connected to the CS chip selection signal end of the slave Flash module;
the PCH south bridge chip is also respectively connected to the main Flash module and the auxiliary Flash module through the SPI bus.
Preferably, an LPC signal end of the BMC module is connected to a processing logic unit in the BMC module, and the processing logic unit in the BMC module is connected to a WDT signal end, a GPO signal end and a built-in Flash of the BMC module; the state of the GPO is stored.
Preferably, a GPO signal end of the CPLD chip module is connected to a processing logic unit in the CPLD chip module, and the processing logic unit in the CPLD chip module is connected to a WDT signal end, a GPI signal end and a built-in UFM of the CPLD chip module; the state of the GPO is stored.
In a second aspect, the present invention provides a dual Flash switching method for a server, including the following steps:
s1: initializing:
the method comprises the steps that initialization is carried out, a main Flash is started, namely a signal output to a Switch control pin SEL is defaulted to be a high level, a default record in a UFM is the high level, a default record in a built-in Flash of a BMC is the high level, and a GPO signal output by the BMC is defaulted to be the high level; at this time, the gating state of Switch is A- > B1, namely BIOS in PCH defaults to main Flash starting;
s2: starting up for the first time:
when receiving a starting instruction, the CPLD judges the state of the BMC through a WDT watchdog signal, if the BMC is not initialized, the GPO is controlled according to the record in the UFM, if the BMC is initialized, the BMC signal is forwarded to the GPO, and the state of the GPO signal is updated to the UFM;
in the starting process, the BMC acquires the POST state of the BIOS in the PCH through the LPC bus, performs timing, judges that the BIOS fails to start if the POST state of the BIOS stays at a certain stage and exceeds a preset threshold value, controls the GPO to output a low level at the moment, and records the state of the GPO into a built-in Flash of the BMC; the low level output by the BMC GPO is forwarded by the CPLD and recorded by the UFM to the SELpin of the Switch, and the gating state of the Switch is A- > B2 at the moment, namely the BIOS in the PCH is switched to start from Flash;
otherwise, keeping the initialization state;
s3: and restarting:
when the system is shut down and restarted, the information recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD is taken as the standard, and the system is switched to the corresponding Flash recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD for starting after being restarted.
Preferably, in step S2, the BMC includes a timer; and timing the POST state of the BIOS.
Preferably, in step S2, the time for the POST state of the BIOS to stay at a certain stage exceeding the predetermined threshold is 2 minutes.
The invention has the advantages that the invention not only can provide redundant BIOSflash switching when the BIOS Flash function is abnormal, ensure the normal starting of the server and improve the overall reliability; and the selection of the BIOS Flash during the last startup can be memorized, thereby improving the overall switching speed and shortening the startup time. The method is realized by using the existing chip on the mainboard, does not need to introduce other chips, and has low cost and simple and convenient realization.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a dual Flash switching system of a server according to the present invention.
Fig. 2 is a flowchart of a dual Flash switching method for a server according to the present invention.
The system comprises a 1-PCH south bridge chip, a 2-Switch chip, a 3-CPLD chip module, a 4-BMC module, a 5-master Flash module and a 6-slave Flash module.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
as shown in fig. 1, the dual Flash switching system of a server provided in this embodiment includes:
the PCH south bridge chip 1 is connected with the BMC module 4 through LPC bus signals, a WDT signal end of the BMC module 4 is electrically connected with a WDT signal end of the CPLD chip module 3, and a GPO signal end of the BMC module 4 is electrically connected with a GPI signal end of the CPLD chip module;
a CS chip selection signal end of the PCH south bridge chip 3 is electrically connected to an A signal receiving end of the Switch chip 2, an SEL signal receiving end of the Switch chip 2 is electrically connected to a GPO signal end of the CPLD chip module, a B1 signal end of the Switch chip is electrically connected to a CS chip selection signal end of the main Flash module 5, and a B2 signal end of the Switch chip is electrically connected to a CS chip selection signal end of the slave Flash module 6;
the PCH south bridge chip is also respectively connected to the main Flash module and the auxiliary Flash module through the SPI bus.
The LPC signal end of the BMC module is connected to a processing logic unit in the BMC module, and the processing logic unit in the BMC module is connected to a WDT signal end, a GPO signal end and a built-in Flash of the BMC module; the state of the GPO is stored.
The GPO signal end of the CPLD chip module is connected to the processing logic unit in the CPLD chip module, and the processing logic unit in the CPLD chip module is connected to the WDT signal end, the GPI signal end and the built-in UFM of the CPLD chip module; the state of the GPO is stored.
Example 2:
as shown in fig. 2, the dual Flash switching method for a server provided in this embodiment includes the following steps:
s1: initializing:
the method comprises the steps that initialization is carried out, a main Flash is started, namely a signal output to a Switch control pin SEL is defaulted to be a high level, a default record in a UFM is the high level, a default record in a built-in Flash of a BMC is the high level, and a GPO signal output by the BMC is defaulted to be the high level; at this time, the gating state of Switch is A- > B1, namely BIOS in PCH defaults to main Flash starting;
s2: starting up for the first time:
when receiving a starting instruction, the CPLD judges the state of the BMC through a WDT watchdog signal, if the BMC is not initialized, the GPO is controlled according to the record in the UFM, if the BMC is initialized, the BMC signal is forwarded to the GPO, and the state of the GPO signal is updated to the UFM;
in the starting process, the BMC acquires the POST state of the BIOS in the PCH through the LPC bus, performs timing, judges that the BIOS fails to start if the POST state of the BIOS stays at a certain stage and exceeds a preset threshold value, controls the GPO to output a low level at the moment, and records the state of the GPO into a built-in Flash of the BMC; the low level output by the BMC GPO is forwarded by the CPLD and recorded by the UFM to the SELpin of the Switch, and the gating state of the Switch is A- > B2 at the moment, namely the BIOS in the PCH is switched to start from Flash; a timer is arranged in the BMC; and timing the POST state of the BIOS. The time for the POST state of the BIOS to stay at a certain stage to exceed a preset threshold is 2 minutes;
otherwise, the initialization state is continuously maintained.
S3: and restarting:
when the system is shut down and restarted, the information recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD is taken as the standard, and the system is switched to the corresponding Flash recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD for starting after being restarted.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A dual Flash switching system of a server, comprising:
the system comprises a PCH south bridge chip, a Switch chip, a CPLD chip module, a BMC module, a main Flash module and a slave Flash module;
the PCH south bridge chip is connected to the BMC module through LPC bus signals, a WDT signal end of the BMC module is electrically connected to a WDT signal end of the CPLD chip module, and a GPO signal end of the BMC module is electrically connected to a GPI signal end of the CPLD chip module;
the CS chip selection signal end of the PCH south bridge chip is electrically connected to the A signal receiving end of the Switch chip, the SEL signal receiving end of the Switch chip is electrically connected to the GPO signal end of the CPLD chip module, the B1 signal end of the Switch chip is electrically connected to the CS chip selection signal end of the main Flash module, and the B2 signal end of the Switch chip is electrically connected to the CS chip selection signal end of the slave Flash module;
the PCH south bridge chip is also respectively connected to the main Flash module and the auxiliary Flash module through the SPI bus.
2. The dual Flash switching system of a server of claim 1, wherein the LPC signal terminal of the BMC module is connected to the processing logic unit in the BMC module, and the processing logic unit in the BMC module is connected to the WDT signal terminal, the GPO signal terminal, and the built-in Flash of the BMC module.
3. The dual-Flash switching system of a server of claim 2, wherein the GPO signal terminal of the CPLD chip module is connected to the processing logic unit in the CPLD chip module, and the processing logic unit in the CPLD chip module is connected to the WDT signal terminal, the GPI signal terminal and the built-in UFM of the CPLD chip module.
4. A double-Flash switching method of a server is characterized by comprising the following steps:
s1: initializing:
the method comprises the steps that initialization is carried out, a main Flash is started, namely a signal output to a Switch control pin SEL is defaulted to be a high level, a default record in a UFM is the high level, a default record in a built-in Flash of a BMC is the high level, and a GPO signal output by the BMC is defaulted to be the high level; at the moment, the gating state of Switch is A- > B1, namely BIOS in PCH defaults to main Flash starting;
s2: starting up for the first time:
when receiving a starting instruction, the CPLD judges the state of the BMC through a WDT watchdog signal, if the BMC is not initialized, the GPO is controlled according to the record in the UFM, if the BMC is initialized, the BMC signal is forwarded to the GPO, and the state of the GPO signal is updated to the UFM;
in the starting process, the BMC acquires the POST state of the BIOS in the PCH through the LPC bus, performs timing, judges that the BIOS fails to start if the POST state of the BIOS stays at a certain stage and exceeds a preset threshold value, controls the GPO to output a low level at the moment, and records the state of the GPO into a built-in Flash of the BMC; the low level output by the BMC GPO is forwarded by the CPLD and recorded by the UFM to the SELpin of the Switch, and the gating state of the Switch is A- > B2 at the moment, namely the BIOS in the PCH is switched to start from Flash;
otherwise, keeping the initialization state;
s3: and restarting:
when the system is shut down and restarted, the information recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD is taken as the standard, and the system is switched to the corresponding Flash recorded in the built-in Flash of the BMC and the built-in UFM of the CPLD for starting after being restarted.
5. The dual Flash switching method of a server according to claim 4, wherein in step S2, a timer is built in the BMC.
6. The dual Flash switching method of server according to claim 5, wherein in step S2, the time for the POST state of BIOS to stay in a certain phase exceeding the predetermined threshold is 2 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911048991.XA CN110928585A (en) | 2019-10-31 | 2019-10-31 | double-Flash switching system and method for server |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911048991.XA CN110928585A (en) | 2019-10-31 | 2019-10-31 | double-Flash switching system and method for server |
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| CN110928585A true CN110928585A (en) | 2020-03-27 |
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| CN201911048991.XA Withdrawn CN110928585A (en) | 2019-10-31 | 2019-10-31 | double-Flash switching system and method for server |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113918389A (en) * | 2021-12-15 | 2022-01-11 | 苏州浪潮智能科技有限公司 | double-Flash switching device and server |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200933A (en) * | 2010-03-23 | 2011-09-28 | 深圳华北工控股份有限公司 | System BIOS (Basic Input/Output System) automatic restoring method based on dual SPI (Serial Peripheral interface) Flashes |
| CN102955724A (en) * | 2011-08-25 | 2013-03-06 | 鸿富锦精密工业（深圳）有限公司 | BIOS (basic input output system) test fixture and method using same for BIOS test |
| CN108228394A (en) * | 2018-01-02 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of double BIOS Flash control systems of server and method |
-
2019
- 2019-10-31 CN CN201911048991.XA patent/CN110928585A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200933A (en) * | 2010-03-23 | 2011-09-28 | 深圳华北工控股份有限公司 | System BIOS (Basic Input/Output System) automatic restoring method based on dual SPI (Serial Peripheral interface) Flashes |
| CN102955724A (en) * | 2011-08-25 | 2013-03-06 | 鸿富锦精密工业（深圳）有限公司 | BIOS (basic input output system) test fixture and method using same for BIOS test |
| CN108228394A (en) * | 2018-01-02 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of double BIOS Flash control systems of server and method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113918389A (en) * | 2021-12-15 | 2022-01-11 | 苏州浪潮智能科技有限公司 | double-Flash switching device and server |
| CN113918389B (en) * | 2021-12-15 | 2022-03-11 | 苏州浪潮智能科技有限公司 | double-Flash switching device and server |
| WO2023109018A1 (en) * | 2021-12-15 | 2023-06-22 | 苏州浪潮智能科技有限公司 | Double-flash switching device and server |
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