CN110928499A - Flash memory embedded in chip, chip and starting method of chip - Google Patents
Flash memory embedded in chip, chip and starting method of chip Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention discloses a flash memory embedded in a chip, the chip and a starting method of the chip; the flash memory is divided into a main storage space and an auxiliary storage space; the main storage space is provided with a program code storage area used for storing program codes, and the program code storage area is a writable storage area; the auxiliary storage space is divided into a calibration parameter storage area, an inherent parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing calibration parameters of the chip and is a one-time programmable and unreadable storage area; the intrinsic parameter storage area is used for storing intrinsic parameters of a chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of a chip and is a writable storage area; the boot code storage area is used for storing boot codes of the chip and is a writable storage area. The chip of the invention has the advantages of low cost, high flexibility and high fault-tolerant rate.
Description
Technical Field
The invention relates to the field of chip application development, in particular to a flash memory embedded in a chip, the chip and a starting method of the chip.
Background
An IC Chip (Integrated Circuit Chip) is a micro-structure having a desired Circuit function, which is formed by fabricating an Integrated Circuit formed by a large number of microelectronic devices (transistors, resistors, capacitors, etc.) on a small or several small semiconductor wafers or dielectric substrates, and then encapsulating the Integrated Circuit in a package.
The chips are provided with executable boot codes, namely boot loaders, and the chips must run the boot codes firstly when being powered on and started; the chip is provided with a special ROM for storing the starting code, and the data stored in the ROM is written in advance before being loaded into the whole chip, and the data can only be read out in the working process of the chip, but can not be quickly and conveniently rewritten like a random access memory; because of the characteristics of the ROM, the development of the boot code must be completed before the development of the chip solution, that is, the boot code needs to be prepared in advance and solidified in the ROM of the chip, the boot code is not changeable after the chip is produced, and once the boot code has a defect (bug) or other security risks (for example, is cracked), the boot code needs to be re-taped, which adversely affects the production of the chip.
Disclosure of Invention
The first purpose of the present invention is to provide a flash memory embedded in a chip, which is to divide the structure of the flash memory, store a part of space in the flash memory to store Bootloader boot codes, and modify the Bootloader boot codes in the development process of the chip, so as to achieve the purpose of saving one ROM memory to reduce the design cost of the chip, and to make the development of the Bootloader boot codes more flexible. The first purpose of the invention is realized by the following technical scheme:
a flash memory embedded in a chip is characterized in that the flash memory is divided into a main storage space and an auxiliary storage space; the main storage space is provided with a program code storage area for storing a program code, the program code storage area is a writable storage area, and the program code stored in the main storage space is unreadable by external equipment and readable by a CPU (central processing unit) of the chip; the auxiliary storage space is divided into a calibration parameter storage area, an inherent parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing calibration parameters of the chip, is a one-time programmable and unreadable storage area, and can not read external equipment and a CPU (central processing unit) of the chip, which are stored in the calibration parameter storage area; the intrinsic parameter storage area is used for storing intrinsic parameters of a chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of a chip and is a writable storage area; the boot code storage area is used for storing boot codes of the chip and is a writable storage area.
Furthermore, the main storage space is further divided into a boot code backup area for backing up boot codes, and the boot code backup area is a writable storage area.
Furthermore, the main storage space is further divided into an auxiliary space upgrading data storage area for storing data to be upgraded in the auxiliary storage space, and the auxiliary space upgrading data storage area is a writable storage area.
Furthermore, the auxiliary storage space is also divided into a user parameter storage area for storing parameters defined by a chip developer for the chip, and the user parameter storage area is a readable and writable storage area.
Furthermore, the auxiliary storage space is also divided into a scheme parameter storage area, and the scheme parameter storage area is a one-time programmable storage area and is used for storing the scheme parameters of the chip development scheme and the parameters to be called in the process of executing the program codes.
Furthermore, the main storage space is also divided into an unreadable RAM storage area for storing some parameters which need to be protected and are generated in the execution of the program code of the chip, and the content stored in the unreadable RAM storage area is unreadable by external devices and readable by a CPU of the chip.
Furthermore, the main storage space is also divided into a readable RAM storage area for storing some changed parameters generated in the execution of the program codes of the chip.
Specifically, the division of the main storage space and the auxiliary storage space of the flash memory and the division of each storage area of the two storage spaces are formed by building an and gate and/or a nor gate and peripheral circuits thereof.
A second object of the present invention is to provide a chip, which does not need to use a ROM memory for storing Bootloader boot codes, thereby effectively reducing the design cost of the chip; and the development of Bootloader starting codes is more flexible. The second purpose of the invention is realized by the following technical scheme:
a chip comprises a flash starting state machine, and is characterized by further comprising a check controller module, a check module, a flash memory protection switch, a check information configuration module, a configuration scheme configuration module and the flash memory according to any one of claims 1 to 8;
the flash starting state machine is used for controlling the working process of a flash memory and is in bidirectional connection with the check controller module;
the checking controller module comprises a parameter checking controller, a starting code checking controller and a program code checking controller; the parameter checking controller is used for sending a checking instruction of the calibration parameter, a checking instruction of the inherent parameter and a checking instruction of the configuration scheme, and sending one instruction each time; the starting code checking controller is used for sending a starting code checking instruction; the program code checking controller is used for sending a program code checking instruction;
the checking module is in bidirectional connection with the checking controller module of the checking controller module; the checking module is in communication connection with the flash memory, and reads corresponding data from the flash memory for checking according to the checking instruction;
the flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the verification controller module;
the output end of the parameter checking controller is respectively connected with the input ends of the checking information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the method comprises the following steps of; and the output end of the configuration scheme configuration module is connected with a chip to be configured with the components of the configuration scheme.
A third object of the present invention is to provide a method for starting the chip according to the second object. The third purpose of the invention is realized by the following technical scheme:
a start-up method of a claim chip, comprising the steps of:
s1, powering on the chip;
s2, information verification of each storage area of the auxiliary storage space:
if the verification is passed, the step S3 is executed after the calibration parameters of the auxiliary storage space and the configuration scheme of the chip are initialized to the chip; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s3, program code verification in the program code storage area of the main storage space:
if the verification of the program code passes, performing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s4, executing Bootloader boot codes in the boot code storage area;
s5, executing the chip program code in the program code storage area.
Specifically, step S2 specifically includes the following steps:
s21, checking the calibration parameters in the calibration parameter storage area:
if the calibration parameter check passes, performing step S22; if the calibration parameter is not verified, the chip stops starting after the flash memory enters a protection state;
s22, checking intrinsic parameters in the intrinsic parameter storage area:
if the verification of the intrinsic parameters passes, step S23 is performed; if the verification of the inherent parameters is not passed, the chip stops starting after the flash memory enters a protection state;
s23, initializing the calibration parameters into the chip;
s24, checking the configuration scheme of the chip in the chip configuration storage area:
if the verification of the configuration scheme passes, performing step S25; if the verification of the configuration scheme is not passed, the chip stops starting after the flash memory enters a protection state;
s25, initializing the configuration scheme of the chip to the chip;
s26, Bootloader boot code verification of the boot code storage area:
if the verification of the Bootloader starting code passes, executing step S3; and if the boot loader boot code is not verified, the chip terminates the boot after the flash memory enters a protection state.
Furthermore, the main storage space is divided into a starting code backup area; the configuration scheme includes configuration of the switch state of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader boot codes of the boot code storage area of the auxiliary storage space;
s262, judging whether the starting code backup area of the main storage space is opened:
if the boot code backup area is open, go to step S263; if the boot code backup area is closed, go to step S265;
s263, checking the backup starting code of the starting code backup area of the main storage space;
s264, confirming the starting code checking results of the main storage space and the auxiliary storage space:
if the boot codes of the primary and secondary storage spaces are verified successfully, executing step S3;
if the boot codes of the primary and secondary storage spaces are verified successfully and failed, updating the data of the storage area failed in verification to the data of the storage area successfully verified, and then executing step S3;
if the verification of the starting codes of the main storage space and the auxiliary storage space fails, the chip stops starting after the flash memory enters a protection state;
s265, confirming the starting code checking result of the starting code storage area of the auxiliary storage space:
if the boot code check passes, perform step S3; if the starting code check is not passed, the chip stops starting after the flash memory enters a protection state.
Further, in the process of running the program code in step S5, if there is an instruction to program data into the Flash memory in the execution command, the following process is entered:
A. judging the programmed area:
if the programming area is in the scheme parameter storage area, executing the step B; if the programming area is a writable storage area except the one-time programmable storage area, performing data programming on the corresponding storage area by combining a programming program of the bootloader;
B. judging the programming record of the scheme parameter storage area:
if the program record exists in the scheme parameter storage area, the program is not executed, and the CPU of the chip is alarmed; and if the program recording does not exist in the scheme parameter storage area, performing data programming on the scheme parameter storage area by combining with a programming program of the bootloader.
Further, the configuration scheme comprises mapping of an upgrade port of a chip and configuration of an enable state of the upgrade port; when the enable state of the upgrade port is configured to be the open state, in the process of running the program code in step S5, if the chip receives a program code upgrade instruction, the CPU of the chip automatically jumps to the Bootloader boot code, executes the upgrade code therein, enters an upgrade flow, and then upgrades the program code in the main storage space.
Further, the configuration scheme comprises mapping of an upgrade port of a chip and configuration of an enable state of the upgrade port; when the enable state of the upgrade port is configured to be an open state, in the process of running the program code in step S5, if the chip receives an upgrade instruction of the secondary storage space, the chip automatically jumps to a Bootloader boot code, executes an upgrade code therein, enters an upgrade process, and stores information to be upgraded in the secondary storage space to a secondary space upgrade data storage area of the primary storage space; after the chip is powered on again, after step S23 and before step S24, the step of upgrading the information of the secondary storage space chip is performed, specifically, the step of upgrading the information of the secondary storage space chip includes:
m1, judging whether the upgrade data exists in the auxiliary space upgrade data storage area of the main storage space, if so, executing step M2; if not, go to step S24;
m2, checking the auxiliary space upgrade data storage area:
if the verification passes, the data of the corresponding storage area in the secondary storage space is updated, and then step S24 is executed; if the verification fails, step S24 is executed directly.
The invention has the beneficial effects that:
the chip can reduce a ROM memory, has low cost and high flexibility and fault tolerance rate, and a chip developer can develop Bootloader starting codes according to the self requirement. The chip has the backup function of the Bootloader starting code, an insurance is added to the Bootloader starting code, and the probability of chip damage caused by the abnormity of the Bootloader starting code is reduced.
Drawings
FIG. 1 is a diagram illustrating a structure division of a flash memory of a chip according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram illustrating the structural division of a flash memory of a chip according to an embodiment of the present invention;
FIG. 3 is a third schematic diagram illustrating the structural division of a flash memory of a chip according to an embodiment of the present invention;
FIG. 4 is a fourth schematic diagram illustrating the structural division of the flash memory of the chip according to the embodiment of the present invention;
FIG. 5 is a flowchart illustrating the start-up of a chip according to an embodiment of the present invention;
FIG. 6 is a flowchart of checking information in each storage area of the secondary storage space of the chip according to an embodiment of the present invention;
FIG. 7 is another flowchart of checking information in each storage area of the secondary storage space of the chip according to the embodiment of the present invention;
FIG. 8 is a flowchart illustrating a process of executing a program in the process of executing program code by the chip according to the embodiment of the present invention;
FIG. 9 is a flowchart of a program code upgrade of a chip provided by an embodiment of the present invention;
FIG. 10 is a partial flowchart of information upgrade of a secondary storage space of a chip according to an embodiment of the present invention;
fig. 11 is a schematic diagram of an internal structure of a chip according to an embodiment of the present invention.
Detailed Description
In order to clearly understand the technical solutions of the present invention, the present invention is further described with reference to the following embodiments, which are only used for the convenience of explaining the technical solutions of the present invention, and the present invention is not limited to the disclosure of the embodiments.
As shown in fig. 1, the present invention provides a chip having a flash memory embedded therein for storing program codes of the chip; the flash memory is divided into a main storage space and an auxiliary storage space; the main storage space is divided into a program code storage area for storing program codes, the program code storage area is a writable storage area which has scrambling and protection functions, the program codes stored in the external equipment cannot be read by external equipment, and the program codes stored in a CPU (central processing unit) reader of a chip can be read by the CPU reader; the auxiliary storage space is divided into a calibration parameter storage area, an inherent parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing calibration parameters of the chip, is a one-time programmable and unreadable storage area, and can not be read by external equipment and a CPU of the chip; the intrinsic parameter storage area is used for storing intrinsic parameters of a chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of the chip and is a writable storage area, and the content stored in the writable storage area can be modified by a special burning device; the boot code storage area is used for storing boot codes of the chip, is a writable storage area, and the content stored in the writable storage area can be modified by a special burning device.
The auxiliary storage space is also divided into a user parameter storage area and a scheme parameter storage area; the user parameter storage area is used for storing parameters defined by a chip developer on a chip, such as the model and other information of the chip, and the storage area is a readable and writable storage area. The scheme parameter storage area is a one-time programmable storage area and is used for storing scheme parameters of some chip development schemes of users and parameters required to be called in the program code execution process; in the prior art, the chip is provided with the OTP memory for storing the information of the chip development scheme, and the invention realizes the function of the OTP memory by dividing the scheme parameter storage area in the auxiliary storage space of the flash memory, so that one OTP memory can be saved for the chip, and the overall cost of the chip is reduced.
The chip of the flash memory structure with the structure can save a ROM memory used for solidifying Bootloader starting codes, can also save OTP memories, reduces the cost of the chip, and the Bootloader starting codes can be changed according to the needs of developers, so that the Bootloader starting codes and the development of the chip are more flexible.
With reference to fig. 2, the main storage space is further divided into a boot code backup area for backing up boot codes. Equivalently, an insurance is added on the boot code of the Bootloader, so that the risk of the whole chip being broken due to the error of the boot code of the Bootloader is effectively reduced.
With reference to fig. 3, the main storage space is further divided into an auxiliary space upgrade data storage area for storing data to be upgraded in the auxiliary storage space, and the auxiliary space upgrade data storage area is a writable storage area. The auxiliary space upgrading data storage area is a transfer station for information upgrading of the auxiliary storage space, and data upgrading of the auxiliary storage space can be completed under the condition that operation of a chip is not influenced; the configuration scheme of the chip configuration storage area of the auxiliary storage space and the Bootloader boot code of the boot code storage area can be upgraded.
With reference to fig. 4, the main storage space is further divided into an unreadable RAM storage area and a readable RAM storage area; wherein the non-readable RAM storage area is used for storing some parameters which need to be protected and are generated in the execution of the program codes of the chip; the parameter external equipment in the storage area can not read, but the CPU of the chip can read the content; the readable RAM is used for storing some changed parameters generated in the execution of the program codes of the chip, the parameters are changed all the time, the parameters can be used for continuing to use when the power is restarted next time, and the problems can be positioned when the problems occur so as to recover the current field condition.
The above configuration scheme of the chip configuration storage area is directed at some configurations of the chip, such as mapping information (debug port, upgrade port, development port) of each functional port of the chip, information such as pull-up and pull-down control of each functional port, selection of a UART upgrade port, and the like, information such as an enable state of the debug port, an enable state of the upgrade port, and a capacity of each storage area of a main storage space.
The calibration parameter storage area stores some calibration parameters of the chip under test; when the chips are produced, due to differences of components, processes and the like, some parameters in the chips are deviated from design values, for example, the design value of the clock frequency is 26MHz, but the actual frequency of each chip may be 24/25/27/28MHz and is not in accordance with the design value, so that the clock frequency of the chips needs to be calibrated, and the clock frequency of each chip is close to 26MHz as much as possible; parameters such as analog circuit clock, ADC, DAC, voltage and the like need to be calibrated; after the calibration is completed, the calibration parameters are saved to a calibration parameter storage area.
The intrinsic parameters refer to identification information, characteristic parameters and the like of the chip; wherein the identification information of the chip refers to information capable of identifying the identity of the chip such as an ID of the chip; the characteristic parameters of the chip refer to parameters of the chip design, such as the clock frequency of the chip is 26MHz, the working voltage is 3.3V, and the like.
The embedded flash memory is structurally divided by the chip, so that one part of the chip is used for storing Bootloader starting codes to save a ROM (read only memory) and the other part of the chip is used for realizing the function of the OTP memory, the number of the memories in the chip is effectively saved, and the overall cost of the chip is reduced; moreover, the Bootloader starting code can be modified in the chip development process, so that the chip development is more flexible.
The division of the main storage space and the auxiliary storage space of the flash memory of the chip and the division of each storage area of the two storage spaces are formed by the construction of an AND gate and/or a NOR gate and peripheral circuits thereof.
Referring to fig. 11, the internal structure of the chip of the present invention includes: the flash memory comprises a flash starting state machine, a verification controller module, a verification module, the flash memory, a flash memory protection switch, a verification information configuration module and a configuration scheme configuration module.
The flash starting state machine is used for controlling the working process of a flash memory and is in bidirectional connection with the check controller module.
The checking controller module comprises a parameter checking controller, a starting code checking controller and a program code checking controller; the checking controller module selects a certain checking controller to develop and send a checking instruction according to a working flow controlled by the flash starting state machine, wherein the parameter checking controller is used for sending the checking instruction of the calibration parameter, the checking instruction of the inherent parameter and the checking instruction of the configuration scheme, and one instruction is sent each time; the starting code checking controller is used for sending a starting code checking instruction; the program code verification controller is used for sending a program code verification instruction.
The checking module is in bidirectional connection with each checking controller of the checking controller module, receives the checking instruction of the checking controller module and feeds back the checking result to the checking controller module; and the checking module is in communication connection with the flash memory, and reads corresponding data from the flash memory for checking according to the checking instruction.
The flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the verification controller module; when the feedback information of the verification module received by the verification controller module is that verification fails, a verification controller corresponding to the verification controller module sends a verification failure signal to a control port of a flash memory protection switch, the flash memory protection switch disconnects the information reading module from a data communication port of the flash memory, the flash memory enters a protection mode, and information in the flash memory cannot be read; when the feedback information of the verification module received by the verification controller module is passed through verification, the verification controller corresponding to the verification controller module can send a verification success signal to a control port of the flash memory protection switch, and the flash memory protection switch conducts connection between the information reading module and a data communication port of the flash memory so that information in the flash memory can be read; the information reading module can be a module in a chip, and can also be a module outside the chip for reading information stored in the flash memory.
The output end of the parameter checking controller is connected with the input ends of the checking information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the method comprises the following steps of; and the output end of the configuration scheme configuration module is connected with a chip to be configured with the components of the configuration scheme.
When the verification instruction received by the verification module is a verification instruction of an inherent parameter (which is set according to a starting process of the chip and is used for verifying the inherent parameter only when the verification of the calibration parameter is successful in the embodiment) from the parameter verification controller, and when the feedback information received by the parameter verification controller is that the verification passes, the verification information configuration module initializes the verification information to the chip (that is, when both the inherent parameter and the verification parameter are successfully verified, the verification information is initialized to the chip); when the verification instruction received by the verification module is a verification instruction from the configuration scheme of the parameter verification controller, and the feedback information received by the parameter verification controller from the verification module is verification passing, the configuration scheme configuration module initializes the configuration scheme to the chip.
The verification module is integrated in an applied chip, so that the cost is reduced.
Specifically, the information in each storage area is checked to verify whether the data in the corresponding storage area is accurate; the data of each storage area can be stored into the corresponding verification information of the data in the storage process; the check information of a certain storage area is information obtained by each data through a certain algorithm after the data of the storage area is generated (information calculated by a non-checking module is check information calculated before being stored in a chip).
The specific verification method of the data in a certain storage area comprises the following steps: the check module in the chip obtains comparison check information by reading each information in the storage area according to the same check algorithm; then comparing the comparison and verification information with the verification information of the storage area, if the comparison and verification information is the same (matched), the verification is passed, and the data of the storage area is proved to be correct; if the two are not the same (not matched), the check fails, and the data of the storage area is proved to be in error.
In particular, the verification algorithm may be, but is not limited to, the following algorithm: a parity check algorithm, an MD5 check algorithm, a CRC check algorithm, a BCC check algorithm, etc.; an embodiment of the present invention uses a CRC check algorithm, and a specific check algorithm is a common algorithm for information check in the prior art, which is not described herein again.
The following describes the production and start-up procedure of the chip of the invention:
stage one, design of chip hardware structure
At this stage, the chip completes the design of the hardware structure and completes the structure division of the flash memory; the structure of the flash memory is divided as described above.
Stage two, testing and parameter calibration of chip
In the production process of the chip, the possibility of chip damage may exist, the chip is screened out through the test of the chip, and the chip with good performance is reserved; the parameter calibration has already been described above and will not be described here.
After the parameter calibration of the chip is completed, each calibration parameter is stored in a calibration parameter storage area in the auxiliary storage space, when the calibration is completed and the calibration parameters are stored, the calibration parameter storage area completes self-locking, and the information in the calibration parameter storage area cannot be changed; that is, the calibration parameter storage area is also a one-time programmable area.
At this stage, intrinsic parameters such as identification information and characteristic parameters of the chip are stored in the intrinsic parameter storage area of the sub-storage space.
In terms of hardware, a calibration parameter storage area and an inherent parameter storage area in the auxiliary storage space are set to be one-time programmable areas, so that in the second stage, after data in the two storage areas are burned, the information of the two areas cannot be modified in the future; the information in the calibration parameter storage area is in an unreadable state, and a user cannot know the content of the unreadable information; the information in the intrinsic parameter storage area is public and is in a readable state.
At this stage, the chip writes the initial Bootloader boot code into the boot code storage area, and the Bootloader boot code can be upgraded in a corresponding mode according to the development scheme of the chip at the later stage of chip development.
Stage three, development of chip and program code burning
After the chip is developed, the program code of the chip is required to be burned into a program code storage area of the main storage space; bootloader starting codes have corresponding burning processes so as to guide the burning of program codes.
At this stage, the Bootloader boot code can be upgraded according to the development condition of the chip.
At this stage, the chip writes the configuration scheme of the chip into the chip configuration storage area; the storage area is a writable storage area, and when the information in the storage area needs to be changed (for example, the capacity of each storage area in the main storage space needs to be changed), the information in the user configuration area is burned again.
Specifically, the chip configuration storage area is configured with mapping and enabling states of an upgrade port, when the upgrade port is enabled to be opened, the upgrade port is connected through a UART, and an upgrade process in the Bootloader is executed after a fixed upgrade sequence is input, so that in the upgrade process, the chip is connected with a special burning device to realize configuration scheme upgrade of the chip configuration storage area, upgrade of a Bootloader starting code, upgrade of a program code and the like.
At this stage, the information content in the scheme parameter storage area is burned according to the development condition of the chip, and the information in the scheme parameter storage area cannot be changed after the content in the scheme parameter storage area is burned once.
At this stage, the information in the user parameter storage area is burned according to the development condition of the user.
As shown in fig. 5, after the chip development is completed, the chip of the present invention is started up by the following processes:
s1, powering on the chip;
s2, information verification of each storage area of the auxiliary storage space:
if the verification is passed, the step S3 is executed after the calibration parameters of the auxiliary storage space and the configuration scheme of the chip are initialized to the chip; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S3, program code verification in the program code storage area of the main storage space:
if the verification of the program code passes, performing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S4, executing Bootloader boot codes in the boot code storage area:
s5, executing the chip program code in the program code storage area.
Specifically, as shown in fig. 5, the step S2 specifically includes the following steps:
s21, checking the calibration parameters in the calibration parameter storage area:
if the calibration parameter check passes, performing step S22; and if the calibration parameter is not verified, stopping starting the chip after the flash memory enters a protection state.
S22, checking intrinsic parameters in the intrinsic parameter storage area:
if the verification of the intrinsic parameters passes, step S23 is performed; and if the verification of the inherent parameters is not passed, the chip stops starting after the flash memory enters a protection state.
The sequence of the above steps S21 and S22 is not required, and the step S22 may be performed first, and then the step S21 may be performed, and the execution sequence is determined according to the flow set by the flash startup state machine.
S23, initializing the calibration parameters into the chip;
s24, checking the configuration scheme of the chip in the chip configuration storage area:
verifying the configuration scheme of the chip in the chip configuration storage area, and if the verification is passed, executing step S25; if the verification is not passed, the chip stops starting after the flash memory enters a protection state.
S25, initializing the configuration scheme of the chip to the chip;
s26, Bootloader boot code verification of the boot code storage area:
if the verification of the Bootloader starting code passes, executing step S3; and if the boot loader boot code is not verified, the chip terminates the boot after the flash memory enters a protection state.
As shown in fig. 7, when the main storage space has a boot code backup area, step S26 further includes a step of checking the boot code of the backup of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader boot codes of the boot code storage area of the auxiliary storage space;
s262, judging whether the starting code backup area of the main storage space is opened:
if the boot code backup area is open, go to step S263; if the boot code backup area is closed, step S265 is performed.
Specifically, the open/close state of the boot code backup area is set in the chip configuration storage area.
S263, checking the backup starting code of the starting code backup area of the main storage space;
s264, confirming the starting code checking results of the main storage space and the auxiliary storage space:
if the boot codes of the primary and secondary storage spaces are verified successfully, executing step S3;
if the boot codes of the primary and secondary storage spaces are verified successfully and failed, updating the data failed to be verified into the data successful to be verified, and then executing step S3;
if the verification of the starting codes of the main storage space and the auxiliary storage space fails, the chip stops starting after the flash memory enters a protection state.
S265, confirming the starting code checking result of the starting code storage area of the auxiliary storage space
If the boot code check passes, perform step S3; if the starting code check is not passed, the chip stops starting after the flash memory enters a protection state.
Specifically, with reference to fig. 8, when the chip is started, in the process of running the program code in step S5, if there is an instruction to program data into the Flash memory in the execution command, the following process is performed:
A. judging the programmed area:
if the programming area is in the scheme parameter storage area, executing the step B; if the programming area is a writable storage area except the one-time programmable storage area, performing data programming on the corresponding storage area by combining a programming program of the bootloader;
B. judging the programming record of the scheme parameter storage area:
if the program record exists in the scheme parameter storage area, the program is not executed, and the CPU of the chip is alarmed; and if the program recording does not exist in the scheme parameter storage area, performing data programming on the scheme parameter storage area by combining with a programming program of the bootloader.
With reference to fig. 9, the method for upgrading the program code of the chip according to the present invention is as follows, when the upgrade port is in an open state (according to the configuration of the chip configuration storage area), in the process of running the program code in step S5, if the chip receives a program code upgrade instruction, the CPU of the chip automatically jumps to the Bootloader boot code, executes the upgrade code therein, enters an upgrade flow, and then upgrades (updates the content of) the program code of the main storage space to update the program code by using a proprietary burning device matched with the chip.
If the main storage space is divided into the auxiliary space upgrading data storage area, the information upgrading method of the auxiliary storage space of the chip of the invention comprises the following steps that the contents of the chip configuration storage area, the starting code storage area and the user parameter storage area of the auxiliary storage space can be upgraded, and the contents of the scheme parameter storage area, the calibration parameter storage area and the inherent parameter storage area can not be changed; when the upgrade port is in an open state (configuration of the chip configuration storage area), in the process of running the program code in step S5, if the chip receives an upgrade instruction of the secondary storage space, the chip automatically jumps to a Bootloader boot code, executes the upgraded code therein, enters an upgrade process, and stores the information to be upgraded in the secondary storage space to a secondary space upgrade data storage area of the main storage space; then, after the chip is powered on again, an upgrade step of the information of the sub storage space is carried out after step S23 and before step S24. The auxiliary space upgrading data storage area is a transfer station for information upgrading of the auxiliary storage space, when an upgrading instruction exists, the information to be upgraded is stored in the transfer station, and after the power is supplied again, the information upgrading of the auxiliary storage space is completed through a certain flow.
Specifically, with reference to fig. 10, the step of upgrading the information of the secondary storage space chip includes:
m1, judging whether the upgrade data exists in the auxiliary space upgrade data storage area of the main storage space, if so, executing step M2; if not, go to step S24;
m2, checking the auxiliary space upgrade data storage area:
if the verification is passed, the data of the corresponding area in the secondary storage space is updated, and then step S24 is executed; if the verification fails, step S24 is executed directly.
Specifically, the verification of the auxiliary space upgrading data storage area comprises the verification of a configuration scheme to be upgraded and the verification of a Bootloader starting code to be upgraded, and if one of the verification fails, the data of the auxiliary storage space cannot be updated.
If the verification fails, it indicates that the chip may be attacked by the outside world or the information security of the chip is threatened by other reasons, and therefore, once the verification fails, the flash memory of the chip enters a protection state and the outside world cannot read any information therein.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (15)
1. A flash memory embedded in a chip is characterized in that the flash memory is divided into a main storage space and an auxiliary storage space; the main storage space is provided with a program code storage area for storing a program code, the program code storage area is a writable storage area, and the program code stored in the writable storage area is unreadable by external equipment and readable by a CPU of a chip; the auxiliary storage space is divided into a calibration parameter storage area, an inherent parameter storage area, a chip configuration storage area and a starting code storage area; the calibration parameter storage area is used for storing calibration parameters of the chip, is a one-time programmable and unreadable storage area, and can not read external equipment and a CPU (central processing unit) of the chip, which are stored in the calibration parameter storage area; the intrinsic parameter storage area is used for storing intrinsic parameters of a chip and is a one-time programmable and readable storage area; the chip configuration storage area is used for storing a configuration scheme of a chip and is a writable storage area; the boot code storage area is used for storing boot codes of the chip and is a writable storage area.
2. The flash memory according to claim 1, wherein the main storage space is further divided into a boot code backup area for backing up boot codes as a writable storage area.
3. The flash memory according to claim 1, wherein the main storage space is further divided into a secondary space upgrade data storage area for storing data to be upgraded in the secondary storage space, and the secondary space upgrade data storage area is a writable storage area.
4. The flash memory according to claim 1, wherein the secondary storage space is further divided into a user parameter storage area for storing parameters defined by a chip developer for a chip, and the user parameter storage area is a readable and writable storage area.
5. The flash memory according to claim 1, wherein the auxiliary memory space is further divided into a scheme parameter memory area, and the scheme parameter memory area is a one-time programmable memory area for storing scheme parameters of a chip development scheme and parameters to be called in a process of executing a program code.
6. The flash memory according to any one of claims 1 to 5, wherein the main storage space is further divided into an unreadable RAM storage area for storing some parameters to be protected generated during the execution of the program code of the chip, and the stored contents are unreadable by external devices and readable by the CPU of the chip.
7. The flash memory according to claim 6, wherein the main storage space is further divided into a readable RAM storage area for storing some changed parameters generated by the program code of the chip during execution.
8. The flash memory according to claim 7, wherein the division of the main storage space and the auxiliary storage space of the flash memory, and the division of each storage area of the two storage spaces are formed by building and gates and/or nor gates and peripheral circuits thereof.
9. A chip comprises a flash starting state machine, and is characterized by further comprising a check controller module, a check module, a flash memory protection switch, a check information configuration module, a configuration scheme configuration module and the flash memory according to any one of claims 1 to 8;
the flash starting state machine is used for controlling the working process of a flash memory and is in bidirectional connection with the check controller module;
the checking controller module comprises a parameter checking controller, a starting code checking controller and a program code checking controller; the parameter checking controller is used for sending a checking instruction of the calibration parameter, a checking instruction of the inherent parameter and a checking instruction of the configuration scheme, and sending one instruction each time; the starting code checking controller is used for sending a starting code checking instruction; the program code checking controller is used for sending a program code checking instruction;
the checking module is in bidirectional connection with the checking controller module of the checking controller module; the checking module is in communication connection with the flash memory, and reads corresponding data from the flash memory for checking according to the checking instruction;
the flash memory protection switch is arranged between a data communication port of the flash memory and an information reading module for reading information in the flash memory, and is provided with a control port which is connected with one output end of the verification controller module;
the output end of the parameter checking controller is respectively connected with the input ends of the checking information configuration module and the configuration scheme configuration module; the output end of the verification information configuration module is connected with a component of the chip to be configured with verification information; the method comprises the following steps of; and the output end of the configuration scheme configuration module is connected with a chip to be configured with the components of the configuration scheme.
10. A method for starting up a chip according to claim 9, comprising the steps of:
s1, powering on the chip;
s2, information verification of each storage area of the auxiliary storage space:
if the verification is passed, the step S3 is executed after the calibration parameters of the auxiliary storage space and the configuration scheme of the chip are initialized to the chip; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s3, program code verification in the program code storage area of the main storage space:
if the verification of the program code passes, performing step S4; if the verification is not passed, the chip stops starting after the flash memory enters a protection state;
s4, executing Bootloader boot codes in the boot code storage area;
s5, executing the chip program code in the program code storage area.
11. The method for starting a chip according to claim 10, wherein the step S2 specifically includes the steps of:
s21, checking the calibration parameters in the calibration parameter storage area:
if the calibration parameter check passes, performing step S22; if the calibration parameter is not verified, the chip stops starting after the flash memory enters a protection state;
s22, checking intrinsic parameters in the intrinsic parameter storage area:
if the verification of the intrinsic parameters passes, step S23 is performed; if the verification of the inherent parameters is not passed, the chip stops starting after the flash memory enters a protection state;
s23, initializing the calibration parameters into the chip;
s24, checking the configuration scheme of the chip in the chip configuration storage area:
if the verification of the configuration scheme passes, performing step S25; if the verification of the configuration scheme is not passed, the chip stops starting after the flash memory enters a protection state;
s25, initializing the configuration scheme of the chip to the chip;
s26, Bootloader boot code verification of the boot code storage area:
if the verification of the Bootloader starting code passes, executing step S3; and if the boot loader boot code is not verified, the chip terminates the boot after the flash memory enters a protection state.
12. A starting method of chip according to claim 11, wherein said main storage space is divided into a starting code backup area; the configuration scheme includes configuration of the switch state of the boot code backup area, and step S26 specifically includes:
s261, checking Bootloader boot codes of the boot code storage area of the auxiliary storage space;
s262, judging whether the starting code backup area of the main storage space is opened:
if the boot code backup area is open, go to step S263; if the boot code backup area is closed, go to step S265;
s263, checking the backup starting code of the starting code backup area of the main storage space;
s264, confirming the starting code checking results of the main storage space and the auxiliary storage space:
if the boot codes of the primary and secondary storage spaces are verified successfully, executing step S3;
if the boot codes of the primary and secondary storage spaces are verified successfully and failed, updating the data of the storage area failed in verification to the data of the storage area successfully verified, and then executing step S3;
if the verification of the starting codes of the main storage space and the auxiliary storage space fails, the chip stops starting after the flash memory enters a protection state;
s265, confirming the starting code checking result of the starting code storage area of the auxiliary storage space:
if the boot code check passes, perform step S3; if the starting code check is not passed, the chip stops starting after the flash memory enters a protection state.
13. The method for starting up a chip according to claim 11 or 12, wherein in the process of running the program code in step S5, if there is an instruction to program data into the Flash memory in the execution command, the following process is entered:
A. judging the programmed area:
if the programming area is in the scheme parameter storage area, executing the step B; if the programming area is a writable storage area except the one-time programmable storage area, performing data programming on the corresponding storage area by combining a programming program of the bootloader;
B. judging the programming record of the scheme parameter storage area:
if the program record exists in the scheme parameter storage area, the program is not executed, and the CPU of the chip is alarmed; and if the program recording does not exist in the scheme parameter storage area, performing data programming on the scheme parameter storage area by combining with a programming program of the bootloader.
14. The starting method of the chip according to claim 11 or 12, wherein the configuration scheme includes a mapping of an upgrade port of the chip and a configuration of an enable state of the upgrade port; when the enable state of the upgrade port is configured to be the open state, in the process of running the program code in step S5, if the chip receives a program code upgrade instruction, the CPU of the chip automatically jumps to the Bootloader boot code, executes the upgrade code therein, enters an upgrade flow, and then upgrades the program code in the main storage space.
15. The starting method of the chip according to claim 11 or 12, wherein the configuration scheme includes a mapping of an upgrade port of the chip and a configuration of an enable state of the upgrade port; when the enable state of the upgrade port is configured to be an open state, in the process of running the program code in step S5, if the chip receives an upgrade instruction of the secondary storage space, the chip automatically jumps to a Bootloader boot code, executes an upgrade code therein, enters an upgrade process, and stores information to be upgraded in the secondary storage space to a secondary space upgrade data storage area of the primary storage space; after the chip is powered on again, after step S23 and before step S24, the step of upgrading the information of the secondary storage space chip is performed, specifically, the step of upgrading the information of the secondary storage space chip includes:
m1, judging whether the upgrade data exists in the auxiliary space upgrade data storage area of the main storage space, if so, executing step M2; if not, go to step S24;
m2, checking the auxiliary space upgrade data storage area:
if the verification passes, the data of the corresponding storage area in the secondary storage space is updated, and then step S24 is executed; if the verification fails, step S24 is executed directly.
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