CN110910804A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110910804A CN110910804A CN201911364787.9A CN201911364787A CN110910804A CN 110910804 A CN110910804 A CN 110910804A CN 201911364787 A CN201911364787 A CN 201911364787A CN 110910804 A CN110910804 A CN 110910804A
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- isolation circuit
- test
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises: the display device comprises a display area and a non-display area surrounding the display area, wherein the display area is provided with a plurality of data lines, the non-display area is provided with a plurality of fan-out lines in one-to-one correspondence with the data lines, and one fan-out line comprises a first fan-out line and a corresponding second fan-out line; the non-display area further comprises: the high-frequency binding area consists of binding pads, the testing area consists of testing pads, and the isolating circuit consists of a binding isolating circuit and a testing isolating circuit; the binding isolation circuits are arranged on the first fanout lines and the second fanout lines and are connected with the binding pads one by one; the test isolation circuit is arranged between the first fan-out lines and the test area; in the visual test stage, the binding isolation circuit is in an off state, and the test isolation circuit is in an on state, so that a high-frequency binding area which possibly falls dirty is isolated, the voltage of a data line cannot be influenced, and the accuracy of the visual test is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
At present, with the continuous development of the mobile game industry, the demand of an AMOLED (Active Matrix/Organic light emitting Diode) panel on a game mobile phone is increasing, the demand of a display on image quality is higher and higher based on the high standard requirement of a user on game experience, and in order to meet the demand, a Hi-pin (demux1:1) design has to be adopted when the AMOLED panel is designed.
However, since the Bonding pads (Bonding leads) on the AMOLED panel adopting the Hi-pin design are very small and the interval between the Bonding leads is also very small, after dirt (such as silver) and the like fall on the Bonding leads, when the AMOLED panel is subjected to visual detection (also called VT detection), adjacent data lines are conducted, so that weak leakage current exists between the adjacent data lines, and further, many dark lines appear during VT detection, the problems of over-detection and leakage are caused, and the accuracy of VT detection is reduced.
Therefore, how to effectively improve the accuracy of VT detection becomes an urgent technical problem to be solved when VT detection is performed.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the technical problem of low accuracy of VT detection in the prior art.
In a first aspect, to solve the above technical problem, an embodiment of the present invention provides a display panel, including: the display device comprises a display area and a non-display area surrounding the display area, wherein the display area is provided with a plurality of data lines which are arranged in an array manner, the non-display area is provided with a plurality of fan-out lines which are in one-to-one correspondence with the plurality of data lines, and one fan-out line comprises a first fan-out line and a corresponding second fan-out line; the non-display area further comprises: the device comprises a high-frequency binding region, a test region and an isolation circuit; the high-frequency binding region further comprises a binding pad which is a working signal access end of the display panel, and the test region further comprises a test pad which is a visual test signal access end of the display panel;
the isolation circuit comprises a binding isolation circuit and a testing isolation circuit, the binding isolation circuit is arranged between the first fanout lines and the second fanout lines, and the second fanout lines are connected with the binding pads in the high-frequency binding region one by one;
the test isolation circuit is arranged between the first fan-out lines and the test area;
in the visual test stage, the binding isolation circuit is in a disconnected state, and the test isolation circuit is in a conducting state;
in the working stage, the binding isolation circuit is in a conducting state, and the testing isolation circuit is in a disconnecting state.
Optionally, the binding isolation circuit includes: a plurality of first switching circuits;
the first switch circuit is a connecting wire, wherein the connecting wire is not conductive before the visual test stage and is conductive after the visual test stage;
alternatively, the first switch circuit is a first transistor.
Optionally, when the first switch circuit is the connection line, the connection line includes two non-conductive organic layers disposed oppositely, and a metal ion layer located between the two non-conductive organic layers; after the visual test stage, the connecting wire is heated to enable metal ions in the metal ion layer to be doped in the non-conductive organic layer, so that the connecting wire is conductive;
one end of the connecting wire is connected with the first fanout wire, and the other end of the connecting wire is connected with the corresponding second fanout wire.
Optionally, the bonding isolation circuit and the test isolation circuit have respective control pads in the high-frequency bonding region and the test region; and one control pad of each of the high-frequency binding region and the test region is used for receiving a control signal for controlling the conduction or the disconnection of the binding isolation circuit, and the other control pad is used for receiving a control signal for controlling the conduction or the disconnection of the test isolation circuit.
Optionally, the bonding isolation circuit and the test isolation circuit share the same control pad in the high-frequency bonding region and the test region; the control pad is used for receiving control signals for controlling the binding isolation circuit and the test isolation circuit to be switched on or off.
Optionally, when the first switch circuit is the first transistor, the binding isolation circuit further includes a first control terminal;
in the binding isolation circuit, a first pole of a first transistor is connected with one first fanout line, and a second pole of the first transistor is connected with the corresponding second fanout line;
the first control terminal is connected with the gates of all the first transistors and the control pad.
Optionally, the test isolation circuit comprises a second switching circuit:
the second switch circuit comprises a plurality of second transistors and a second control end, wherein the second transistors are connected with the first fanout lines one by one;
a first pole of a second transistor is connected with one first fanout line, and a second pole of the second transistor is connected with one test bonding pad; the second pole of the second transistor corresponding to the data line for controlling the same three primary colors is connected with the same test bonding pad;
the second control end is connected with the grid electrodes of all the second transistors;
when the second transistor and the first transistor are transistors with the same polarity, the test isolation circuit further comprises a not gate, wherein one end of the not gate is connected with the second control end, and the other end of the not gate is connected with the corresponding control bonding pad;
when the second transistor and the first transistor are transistors with different polarities, the second control terminal is connected with the corresponding control pad.
Optionally, the sum of the resistance values of the first switch circuit corresponding to each data line and the fan-out line is the same within a preset range.
Optionally, the sum of the resistance values of the first switch circuit corresponding to each data line and the fan-out line is the same within a preset range, and the method includes:
when the first switch circuit is the connecting wire, the length of the connecting wire is inversely proportional to the resistance value corresponding to the fanout wire;
or, when the first switch circuit is the connecting line, the cross-sectional area of the connecting line is in direct proportion to the resistance value of the corresponding fanout line.
Optionally, the sum of the resistance values of the first switch circuit corresponding to each data line and the corresponding fanout line is the same within a preset range, and the method includes:
when the first switch circuit is the first transistor, the width-length ratio of the first transistor is in direct proportion to the resistance value of the corresponding fanout line;
or, when the first switch circuit is the first transistor, the resistance value of the polysilicon connected in series with the first transistor is inversely proportional to the resistance value of the corresponding fanout line.
In a second aspect, an embodiment of the present invention provides a display device, which includes the display panel according to the first aspect.
The invention has the following beneficial effects:
in the embodiment provided by the invention, the binding isolation circuit is arranged between the first fan-out lines and the second fan-out lines of the non-display area, and the test isolation circuit is arranged between the first fan-out lines and the test area, so that the binding isolation circuit is in an off state and the test isolation circuit is in an on state in the visual test stage, and thus the high-frequency binding area which possibly falls with dirt is isolated, the signal on the data line cannot be interfered, and the accuracy of the visual test is further improved; in the working stage, the binding isolation circuit is set to be in a conducting state, the testing isolation circuit is set to be in a disconnecting state, and interference signals possibly introduced by the testing area are isolated outside due to the disconnection of the testing isolation circuit, so that the signals in the working stage are prevented from being influenced.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a first schematic diagram of a binding isolation circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a binding isolation circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a third binding isolation circuit according to an embodiment of the present invention;
fig. 5 is a fourth schematic diagram of a binding isolation circuit according to an embodiment of the present invention;
fig. 6 is a first schematic structural diagram of a first switch circuit according to an embodiment of the present invention;
fig. 7 is a second schematic structural diagram of the first switch circuit as a connection line according to the embodiment of the present invention;
fig. 8 is a first schematic structural diagram of a high-frequency binding region and a test region according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram ii of a high-frequency binding region and a test region according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a binding isolation circuit when the first switching circuit is the first transistor according to an embodiment of the present invention;
FIG. 11 is a first schematic diagram of an isolation circuit according to an embodiment of the present invention;
fig. 12 is a second schematic diagram of an isolation circuit according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a display panel and a display device, which are used for solving the technical problem of low accuracy of VT detection in the prior art.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
The following describes a display panel according to an embodiment of the present invention with reference to the drawings.
Referring to fig. 1, a schematic structural diagram of a display panel according to an embodiment of the present invention is shown, where the display panel includes: the display device comprises a display area A and a non-display area B surrounding the display area, wherein the display area B is provided with a plurality of data lines 1 which are arranged in an array manner, the non-display area B is provided with a plurality of fan-out lines 2 which are in one-to-one correspondence with the plurality of data lines 1, and one fan-out line 2 comprises a first fan-out line 21 and a corresponding second fan-out line 22; the non-display area B further comprises: a high-frequency binding region 3, a test region 4, and an isolation circuit 5; the high-frequency binding region 3 further includes a binding pad 31 which is a working signal access terminal of the display panel, and the testing region 4 further includes a testing pad 41 which is a visual testing signal access terminal of the display panel.
In circuit design, products with frequency of 120Hz or more are high-frequency products, and the high-frequency circuit is generally very dense in wiring and susceptible to signal interference. The signal of binding district 3 access through the high frequency is the high frequency signal that the frequency is greater than 120Hz, and the pad setting in the high frequency binding district 3 is very intensive, drops when high frequency binding district 3 when dirty, and these dirty have not been washd yet when carrying out the visual test, just can wash before the working phase.
It should be noted that, the size ratio of the display area a and the non-display area B in fig. 1 is not an actual ratio, in the embodiment provided by the present invention, the display area a is drawn smaller for clearly showing the scheme, and in actual application, the difference between the size of the display area a and the size of the non-display area B is smaller.
The isolation circuit 5 comprises a binding isolation circuit 51 and a testing isolation circuit 52, the binding isolation circuit 51 is arranged between the first fanout lines 21 and the second fanout lines 22, and the second fanout lines 22 are connected with the binding pads 31 in the high-frequency binding region 3 one by one; the test isolation circuit 52 is disposed between the plurality of first fanout lines 21 and the test area 4.
In the visual testing stage, the binding isolation circuit 51 is in an off state, and the testing isolation circuit 52 is in an on state; in the working phase, the binding isolation circuit 51 is in the on state, and the test isolation circuit 52 is in the off state.
In the embodiment provided by the invention, the binding isolation circuit 51 is arranged between the first fan-out lines 21 and the second fan-out lines 22 of the non-display area B, and the testing isolation circuit 52 is arranged between the first fan-out lines 21 and the testing area 4, so that in the visual testing stage, the binding isolation circuit 51 is in a disconnected state, and the testing isolation circuit 52 is in a connected state, so that the high-frequency binding area 3 which possibly falls with dirt is isolated, the visual testing cannot be interfered, and the accuracy of the visual testing is further improved; in the working phase, the binding isolation circuit 51 is set to be in the on state, and the test isolation circuit 52 is set to be in the off state, so that the interference signals which may be introduced by the test area 4 are isolated due to the off state of the test isolation circuit 52, thereby preventing the signals in the working phase from being influenced.
Referring to fig. 2 to 5, fig. 2 is a first schematic diagram of a binding isolation circuit according to an embodiment of the present invention, fig. 3 is a second schematic diagram of a binding isolation circuit according to an embodiment of the present invention, fig. 4 is a third schematic diagram of a binding isolation circuit according to an embodiment of the present invention, and fig. 5 is a fourth schematic diagram of a binding isolation circuit according to an embodiment of the present invention.
The binding isolation circuit 51 includes: the plurality of first switch circuits 511. The first switch circuits 511 correspond to the fan-out lines 2 one by one, or the first switch circuits 511 and the fan-out lines 2 are arranged at intervals. When the first switch circuit 511 is disposed at a distance from the fan-out line 2, the fan-out line 2 is disposed at the M2 layer, and the first transistor is disposed at the MC layer.
Referring to fig. 2 and 3, the first switch circuit 511 is a connection line, wherein the connection line is not conductive before the vision testing stage and is conductive after the vision testing stage.
Alternatively, referring to fig. 4 and 5, the first switch circuit 511 is a first transistor.
Through setting up first switch circuit 511 to be non-conductive before the visual test stage, electrically conductive connecting wire behind the visual test stage, or set up to first transistor, can bind district 3 with the high frequency at the visual test stage and keep apart, prevent that the dirt that drops in high frequency binds district 3 from influencing the data line voltage to can effectual improvement display panel's display effect.
Referring to fig. 6 and 7, fig. 6 is a first schematic structural diagram of a connection line as a first switch circuit according to an embodiment of the present invention, fig. 7 is a second schematic structural diagram of a connection line as a first switch circuit according to an embodiment of the present invention, and when the first switch circuit 511 is a connection line, the connection line includes two non-conductive organic layers 5111 disposed opposite to each other and a metal ion layer 5112 (see fig. 6) disposed between the two non-conductive organic layers 5111; wherein, a layer of non-conductive organic layer 5111 is disposed on the same layer as the fan-out line 2, and after the visual test stage, the connecting line is heated to dope the metal ions in the metal ion layer 5112 into the non-conductive organic layer 5111, so that the connecting line is conductive (see fig. 7); one end of the connecting line is connected with the first fanout line 21, and the other end is connected with the corresponding second fanout line 22.
The material of the metal ion layer 5112 is silver Ag, lithium Li, one of lanthanide metals or a combination of metals.
The material of the non-conductive organic layer 5111 is indium tin oxide ITO, indium zinc oxide IZO, or polymer PEDOT of 3, 4-ethylenedioxythiophene monomer.
After the visual test stage, the connecting wire is heated, so that metal ions in the metal ion layer 5112 are diffused into the non-conductive organic layer 5111, and the connecting wire is conductive, so that the non-conductive organic layer 5111 in the connecting wire is electrically disconnected from the fan-out wire 2 in the visual test stage, and the test isolation circuit 52 is set to be in a conduction state, so that when a test signal is transmitted from the test pad 41 to the data wire 1 for visual detection, the high-frequency binding region 3 which is possibly dropped with dirt can be isolated, the signal on the data wire cannot be interfered, and the accuracy of the visual test is improved; in the working phase, the metal ions in the metal ion layer 5112 are diffused into the non-conductive organic layer 5111 to make the connection line conductive by heating the connection line, so that the working signal is transmitted to the data line 1 through the bonding pad 31, the display area can work normally, and the test isolation circuit 52 is set to be in the off state, and because the test isolation circuit 52 is off, the interference signal possibly introduced by the test area 4 is isolated, thereby preventing the signal in the working phase from being influenced.
It should be noted that, in fig. 6 and fig. 7, only one of the non-conductive organic layers 5111 in the connection line is shown to be disposed at the same layer as the fan-out line 2, but actually, another one of the non-conductive organic layers 5111 in the connection line may also be disposed at the same layer as the fan-out line 2, and specifically, the fan-out line 2 and which one of the non-conductive organic layers 5111 are disposed at the same layer, which is not limited herein.
Referring to fig. 8, which is a schematic structural diagram of a high-frequency bonding area and a test area provided in the embodiment of the present invention, a bonding isolation circuit 51 and a test isolation circuit 52 have respective control pads in the high-frequency bonding area 3 and the test area 4; one control pad of each of the high-frequency binding region 3 and the test region is used for receiving a control signal for controlling the conduction or the disconnection of the binding isolation circuit, and the other control pad is used for receiving a control signal for controlling the conduction or the disconnection of the test isolation circuit. As shown in fig. 8, the binding isolation circuit 51 and the test isolation circuit 52 have a control pad 32 and a control pad 33 in the high-frequency binding region 3, respectively, and the binding isolation circuit 51 and the test isolation circuit 52 have a control pad 42 and a control pad 43 in the test region 4, respectively.
In the embodiment provided by the invention, the binding isolation circuit 51 and the test isolation circuit 52 can be conveniently and respectively controlled by providing the binding isolation circuit 51 and the test isolation circuit 52 with respective control pads in the high-frequency binding region 3 and the test region 4.
Referring to fig. 9, which is a schematic structural diagram of a high-frequency bonding region and a test region provided in the embodiment of the present invention, a bonding isolation circuit 51 and a test isolation circuit 52 share a same control pad in the high-frequency bonding region 3 and the test region 4; the control pad is used for receiving a control signal for controlling the binding isolation circuit 51 and the test isolation circuit 52 to be switched on or off. As shown in fig. 9, the bonding isolation circuit 51 and the test isolation circuit 52 share the same control pad 34 in the high-frequency bonding area 3 and the same control pad 44 in the test area 4.
In the embodiment provided by the invention, the binding isolation circuit 51 and the test isolation circuit 52 share the same control pad in the high-frequency binding region 3 and the test region 4, so that the binding isolation circuit 51 and the test isolation circuit 52 can be simultaneously controlled by the same control signal, the number of pads can be effectively reduced, and the space is saved.
Optionally, the test areas 4 may be two groups, two groups of test areas 4 are respectively arranged on two sides of the binding area 3, and the two groups of test areas 4 are used for inputting the detection signal, so that the detection signal can be enhanced under the condition that the detection signal is weak.
In fig. 9, two control pads 34 are provided, and one control pad 34 may be provided as needed. In fig. 8 and 9, the pads located within the dashed box of test isolation circuit 52 are test pads for receiving VT test signals; the pad located in the dashed box of the bond isolation circuit 51 is a bond pad for receiving an operating signal.
Referring to fig. 10, which is a schematic diagram of the binding isolation circuit when the first switch circuit is the first transistor according to the embodiment of the present invention, when the binding isolation circuit 51 and the test isolation circuit 52 share the same control pad 34 in the high-frequency binding region 3, the same control pad 44 in the test region 4, and the first switch circuit 511 is the first transistor, the binding isolation circuit 51 further includes a first control terminal 512.
In the binding isolation circuit 51, a first pole 5113 of a first transistor is connected to a first fanout line 21, and a second pole 5114 of the first transistor is connected to a corresponding second fanout line 22; the first control terminal 512 is connected to the gates 5115 of all the first transistors and to the control pad 34 and the control pad 44 (not shown in fig. 10).
In the embodiment provided by the present invention, when the first switch circuit 511 is a first transistor, the gates 5115 of all the first transistors in the binding isolation circuit 51 are connected to the control pad 34 and the control pad 44, the first poles 5113 of the first transistors are connected to the first fanout lines 21, and the second poles 5114 are connected to the corresponding second fanout lines 22, so that the on/off of all the fanout lines 2 can be simultaneously controlled by inputting a control signal to the control pad 34 or the control pad 44.
Referring to fig. 11 and 12, fig. 11 is a first schematic diagram of an isolation circuit according to an embodiment of the present invention, fig. 12 is a second schematic diagram of an isolation circuit according to an embodiment of the present invention, and the test isolation circuit 52 includes a second switch circuit 521: the second switching circuit 521 includes a plurality of second transistors connected to the plurality of first fanout lines 21 one by one and a second control terminal 522.
A first pole 5211 of a second transistor is connected to a first fanout line 21, and a second pole 5212 of a second transistor is connected to a test pad 41; wherein the second poles of the second transistors corresponding to the data lines controlling the same three primary colors are connected to the same test pad 41; the second control terminal 522 is connected to the gates 5213 of all the second transistors.
Referring to fig. 11, when the second transistor and the first transistor are transistors with the same polarity, the test isolation circuit 4 further includes a not gate 523, one end of the not gate 523 is connected to the second control terminal 522, and the other end is connected to the corresponding control pad 34 and the control pad 44. In fig. 11, the first transistor in the binding isolation circuit 51 may be a P-type transistor or an N-type transistor, and when the first transistor is a P-type transistor, the second transistor in the test isolation circuit 52 is also a P-type transistor, and when the first transistor is an N-type transistor, the second transistor in the test isolation circuit 52 is also an N-type transistor. When the second transistor and the first transistor are transistors with the same polarity, the binding isolation circuit 51 and the testing isolation circuit 52 can be controlled by the same control signal by adding the not gate 523 between the second control terminal 522 of the testing isolation circuit 52 and the control pad 34 and the control pad 44.
Referring to fig. 12, when the second transistor and the first transistor are transistors with different polarities, the second control terminal 522 is connected to the corresponding control pad 34 and the control pad 44.
In fig. 12, the first transistor in the binding isolation circuit 51 may be a P-type transistor or an N-type transistor, and when the first transistor is a P-type transistor, the second transistor in the test isolation circuit 52 is an N-type transistor, and when the first transistor is an N-type transistor, the second transistor in the test isolation circuit 52 is a P-type transistor. By setting the first transistor in the binding isolation circuit 51 and the second transistor in the test isolation circuit 52 as transistors with different polarities, the binding isolation circuit 51 and the test isolation circuit 52 can be controlled by the same control signal. FIG. 12 illustrates an embodiment, and is not intended to be limiting.
It should be noted that the test zones 4 may also be a group in fig. 11 and 12.
In the embodiment of the present invention, the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the fan-out line 2 is the same within the preset range.
In the embodiment provided by the present invention, by making the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the corresponding fanout line 2 the same within the preset range, the resistance difference between the edge fanout line and the corresponding first switch circuit 511 and the middle fanout line and the corresponding first switch circuit 512 can be balanced, and the problem of uneven display can be prevented.
It should be noted that, in practical applications, the sum of the resistance values of each fan-out line 2 and the corresponding first switch circuit 511 may not be completely the same, and may be considered to be the same as long as the sum is within an error range, so that the sum of the resistance values of each fan-out line 2 and the corresponding first switch circuit 511 may be considered to be the same as long as the resistance values of each fan-out line 2 and the corresponding first switch circuit 511 are the same within a preset range.
Since the resistance of the fanout line 2 corresponding to the middle bonding pad 31 in the high-frequency bonding region 3 is the smallest, and the resistance of the fanout line 2 corresponding to the edge bonding pad 31 in the high-frequency bonding region 3 is the largest, in order to make the sum of the resistances of each fanout line 2 and the corresponding first switch circuit 511 approximately the same (i.e., within a preset range), the resistance of the first switch circuit 511 corresponding to the middle bonding pad 31 is the largest, and the resistance of the first switch circuit 511 corresponding to the edge bonding pad 31 is the smallest.
Since the first switch circuit 511 may be a connection line or a transistor, a solution is provided below in which the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the corresponding fanout line 2 is the same within a predetermined range for each different type of the first transistor 511.
In the first scheme, when the first switch circuit 511 is a connection line, the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the resistance value of the corresponding fanout line 2 is the same within a preset range, and the first switch circuit 511 and the corresponding fanout line 2 can be implemented in the following two ways:
in the first mode, the length of the connecting line is inversely proportional to the resistance value of the corresponding fanout line 2. By setting the length of the connection line to be inversely proportional to the resistance value of the corresponding fanout line 2, the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the corresponding fanout line 2 can be made to be the same within a preset range.
In the second mode, the cross-sectional area of the connecting wire is in direct proportion to the resistance value of the corresponding fanout line 2. By making the cross-sectional area of the connection line proportional to the resistance of the corresponding fanout line 2, the sum of the resistance of the first switch circuit 511 corresponding to each data line 1 and the resistance of the corresponding fanout line 2 can be the same within a preset range.
In the second scheme, when the first switch circuit 511 is a first transistor, the sum of the resistance values of the first switch circuit 511 corresponding to each data line and the corresponding fanout line 2 is the same within a preset range, and the second scheme can be implemented in the following two ways:
in the first mode, the width-to-length ratio of the first transistor is proportional to the resistance value of the corresponding fanout line 2.
By adjusting the width-to-length ratio of the first transistor, the sum of the resistance values of the first switch circuit 511 corresponding to each data line 1 and the corresponding fanout line 2 is the same within a preset range, so that the problem of uneven screen display caused by the difference of the resistance values of the edge fanout line 2 and the middle fanout line 2 can be reduced. Since the resistance of the fanout line 2 changes gradually from the fanout line 2 to the edge fanout line 2, the width-to-length ratio of the first transistor also changes gradually.
Taking the change of the width-to-length ratio of the first transistor as an example, if the resistance value of the fanout line 2 gradually changes from 300 Ω to 2000 Ω, the width-to-length ratio of the first transistor may gradually change from 150um/3um to 55um/3um, so that the sum of the resistance values of the first switch circuit 511 corresponding to each data line and the corresponding fanout line 2 is the same in a preset range, and uneven display caused by different middle and edge resistance values is reduced.
In the second mode, the resistance value of the polysilicon connected in series with the first transistor is inversely proportional to the resistance value of the corresponding fanout line 2.
The resistance value of the polysilicon is changed by changing the length of the polysilicon connected in series at the first transistor, that is, the length of the polysilicon corresponding to the binding pad 31 at the edge is the shortest or 0, the resistance value is smaller, the length of the polysilicon corresponding to the binding pad 31 at the middle is the longest, and the resistance value is larger, so that the sum of the resistance values of the first switch circuit 511 corresponding to each data line and the corresponding fanout line 2 can be ensured to be the same in a preset range, and uneven display caused by different resistance values at the middle and the edge can be reduced.
When the first transistor and the fanout line 2 are disposed at intervals, the fanout line 2 provided with the first transistor is disposed on the MC layer, the fanout line 2 without the first transistor is disposed on the M2 layer, and the resistance of the M2 layer is greater than that of the MC layer.
Based on the same inventive concept, embodiments of the present invention provide a display device including the display panel as described above.
The display device can be a display, a display screen, a television and other display devices, and can also be mobile equipment such as a mobile phone, a tablet computer, a notebook computer and the like.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A display panel is characterized by comprising a display area and a non-display area surrounding the display area, wherein the display area is provided with a plurality of data lines which are arranged in an array manner, the non-display area is provided with a plurality of fan-out lines which are in one-to-one correspondence with the plurality of data lines, and one fan-out line comprises a first fan-out line and a second fan-out line which is in correspondence with the first fan-out line; the non-display area further comprises: the device comprises a high-frequency binding region, a test region and an isolation circuit; the high-frequency binding region further comprises a binding pad which is a working signal access end of the display panel, and the test region further comprises a test pad which is a visual test signal access end of the display panel;
the isolation circuit comprises a binding isolation circuit and a testing isolation circuit, the binding isolation circuit is arranged between the first fanout lines and the second fanout lines, and the second fanout lines are connected with the binding pads in the high-frequency binding region one by one;
the test isolation circuit is arranged between the first fan-out lines and the test area;
in the visual test stage, the binding isolation circuit is in a disconnected state, and the test isolation circuit is in a conducting state;
in the working stage, the binding isolation circuit is in a conducting state, and the testing isolation circuit is in a disconnecting state.
2. The display panel of claim 1, wherein the binding isolation circuit comprises: a plurality of first switching circuits;
the first switch circuit is a connecting wire, wherein the connecting wire is not conductive before the visual test stage and is conductive after the visual test stage;
alternatively, the first switch circuit is a first transistor.
3. The display panel according to claim 2, wherein when the first switching circuit is the connection line, the connection line includes two non-conductive organic layers disposed opposite to each other, and a metal ion layer between the two non-conductive organic layers; after the visual test stage, the connecting wire is heated to enable metal ions in the metal ion layer to be doped in the non-conductive organic layer, so that the connecting wire is conductive;
one end of the connecting wire is connected with the first fanout wire, and the other end of the connecting wire is connected with the corresponding second fanout wire.
4. The display panel of claim 2, wherein the binding isolation circuit, the test isolation circuit have respective control pads at the high frequency binding region and the test region; and one control pad of each of the high-frequency binding region and the test region is used for receiving a control signal for controlling the conduction or the disconnection of the binding isolation circuit, and the other control pad is used for receiving a control signal for controlling the conduction or the disconnection of the test isolation circuit.
5. The display panel of claim 2, wherein the bonding isolation circuit and the test isolation circuit share a same control pad in the high frequency bonding region and the test region; the control pad is used for receiving control signals for controlling the binding isolation circuit and the test isolation circuit to be switched on or off.
6. The display panel of claim 5, wherein when the first switch circuit is the first transistor, the binding isolation circuit further comprises a first control terminal;
in the binding isolation circuit, a first pole of a first transistor is connected with one first fanout line, and a second pole of the first transistor is connected with the corresponding second fanout line;
the first control terminal is connected with the gates of all the first transistors and the control pad.
7. The display panel of claim 6, wherein the test isolation circuit comprises a second switching circuit:
the second switch circuit comprises a plurality of second transistors and a second control end, wherein the second transistors are connected with the first fanout lines one by one;
a first pole of a second transistor is connected with one first fanout line, and a second pole of the second transistor is connected with one test bonding pad; the second pole of the second transistor corresponding to the data line for controlling the same three primary colors is connected with the same test bonding pad;
the second control end is connected with the grid electrodes of all the second transistors;
when the second transistor and the first transistor are transistors with the same polarity, the test isolation circuit further comprises a not gate, wherein one end of the not gate is connected with the second control end, and the other end of the not gate is connected with the corresponding control bonding pad;
when the second transistor and the first transistor are transistors with different polarities, the second control terminal is connected with the corresponding control pad.
8. The display panel according to any one of claims 2 to 7, wherein a sum of resistance values of the first switch circuit corresponding to each of the data lines and the fan-out line is the same within a preset range.
9. The display panel according to claim 8, wherein a sum of the resistance values of the first switch circuit corresponding to each of the data lines and the fan-out line is the same within a preset range, and the method comprises:
when the first switch circuit is the connecting wire, the length of the connecting wire is inversely proportional to the resistance value corresponding to the fanout wire;
or, when the first switch circuit is the connecting line, the cross-sectional area of the connecting line is in direct proportion to the resistance value of the corresponding fanout line.
10. The display panel according to claim 8, wherein a sum of the resistance values of the first switch circuit corresponding to each of the data lines and the corresponding fanout line is the same within a preset range, and the method comprises:
when the first switch circuit is the first transistor, the width-length ratio of the first transistor is in direct proportion to the resistance value of the corresponding fanout line;
or, when the first switch circuit is the first transistor, the resistance value of the polysilicon connected in series with the first transistor is inversely proportional to the resistance value of the corresponding fanout line.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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