CN110909659A - Layout key region extraction method and extraction system thereof - Google Patents

Layout key region extraction method and extraction system thereof Download PDF

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CN110909659A
CN110909659A CN201911133017.3A CN201911133017A CN110909659A CN 110909659 A CN110909659 A CN 110909659A CN 201911133017 A CN201911133017 A CN 201911133017A CN 110909659 A CN110909659 A CN 110909659A
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layout
grid point
product
line width
point window
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朱忠华
姜立维
魏芳
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Shanghai Huali Microelectronics Corp
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Abstract

The invention discloses a layout key area extraction method for integrated circuit layout failure area positioning, which comprises the steps of determining layout levels of key areas to be extracted, dividing the extracted layout levels into grid point windows according to grid point window division rules, extracting line width product values and space product values of graphs in each grid point window, extracting product value threshold values defined into key areas from historical mature stable production products, wherein the product value threshold values comprise line width product value threshold values and space product value threshold values, judging whether the graphs in each grid point window are the key areas according to the product value threshold values, and extracting the key areas. The invention also discloses a layout key region extraction system. The method can quickly and accurately position the key area of the layout, can reduce the key area in the new product layout to at least 30% of the original layout compared with the prior art, saves 70% of cycle time of subsequent failure analysis, and greatly improves the economic benefit of manufacturers.

Description

Layout key region extraction method and extraction system thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a layout key region extraction method capable of positioning by using an integrated circuit layout failure region. The invention also relates to a layout key region extraction system capable of positioning by using the integrated circuit layout failure region.
Background
As the integrated circuit fabrication process nodes continue to advance, manufacturability and reliability checks of integrated circuit designs become increasingly important. The reduction of the size of the process node and the continuous deepening of the complexity of the design graph force the manufacturer to invest huge manpower and financial resources to evaluate the manufacturability of the design layout. Once a failure is discovered in a newly designed product, a common manufacturer typically uses Static Random Access Memory (SRAM) as the most critical area in the layout to perform various process checks. However, in most cases, the finally discovered failure region is not the SRAM region, and the efficiency of the carpet search check similar to the marine fishing needle is obviously very low.
If the key area with a smaller manufacturable process window in the layout can be extracted quickly, the positioning of the failure area can be accelerated, and the economic benefit of a manufacturer is further improved.
Disclosure of Invention
In this summary, the description is included in part in a simplified form that is a shorthand for understanding the concepts of the present invention, as will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing a layout key region extraction method which is used for positioning a layout failure region of an integrated circuit and can quickly and accurately position a layout key region compared with the prior art.
The invention aims to solve another technical problem of providing a layout key region extraction system which is used for positioning a layout failure region of an integrated circuit and can quickly and accurately position a layout key region compared with the prior art.
In order to solve the technical problem, the method for extracting the critical area of the layout, provided by the invention, comprises the following steps:
s1, determining the layout level of the key region to be extracted;
s2, dividing the extracted layout level into grid point windows according to grid point window division rules;
s3, extracting the line width product value and the space product value of the graph in each lattice point window;
s4, extracting product value threshold values defined as key areas from the historical mature stable production products, wherein the product value threshold values comprise line width product value threshold values and space product value threshold values;
and S5, judging whether the graph in each grid point window is a key area according to the product threshold value, and extracting the key area.
Optionally, the layout key region extraction method is further improved, and in step S2, the grid point window division rule is as follows;
taking the initial point of the lower left corner of the layout hierarchy as the origin (0, 0), dividing the layout hierarchy into a plurality of m x n grid point windows by the size w x w, wherein each grid point window is provided with a corresponding intercepting graph, w is more than or equal to 0, the row number m of each grid point window is more than 1, the column number n of each grid point window is more than 1, and the intercepting graph refers to the key layer layout graph in each grid point window.
Optionally, the method for extracting the critical area of the layout is further improved, and the range of the preset size w is 0um-200 um.
Optionally, the method for extracting the critical area of the layout is further improved, and in step S3, the line width product value is obtained by the following steps;
s3.1, determining the minimum recommended value w of the line width of the layout level according to the manufacturing processr
S3.2, calculating the line width product value of all the graphs in each grid point window which is smaller than the recommended value,
Figure BDA0002278845250000021
wrrepresents a minimum recommended value of line width, wiRepresenting the actual value of the line width, aiRepresents the area of the line width, n represents the grid point window column number, r is the recommend identifier, so w is the DFM recommendationrA minimum recommended value of the line width of the finger; assuming that the line width patterns within the grid window are numbered from 1, 2, … … up to n, i denotes any number;
wherein when wr-wiIf < 0, then wr-wiTake 0.
Optionally, the method for extracting the critical area of the layout is further improved, and in step S3, the distance product value is obtained by calculation through the following steps;
s3.3, determining the minimum recommended value S of the layout level spacing according to the manufacturing processr
S3.4, calculating the interval product value of all the graphs in each grid point window which is smaller than the recommended value
Figure BDA0002278845250000022
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresents the area of the space, m represents the grid point window row number, r is the recommend identifier, so s is the DFM recommendationrMinimum recommended value of finger spacing; assuming that the line width patterns within the grid window are numbered from 1, 2, … … up to n, i denotes any number;
wherein when sr-siIf < 0, then sr-siTake 0.
Optionally, the layout key region extraction method is further improved, and in step S4, the line width product threshold and the space product threshold are obtained by calculating probability distribution according to the product distribution range of the product which has been produced stably in a large scale.
Optionally, the method for extracting the key regions of the layout is further improved, and the probability distribution calculation is Gamma probability fitting solution.
Optionally, the method for extracting the key regions of the layout is further improved, the point with the cumulative probability of g% is set as a threshold value in the probability distribution calculation, and the range of g is 80-100.
Optionally, the method for extracting the critical area of the layout is further improved, and in step S5, the graphic area higher than the grid point window of the line width product value threshold or the space product value threshold is extracted as the critical area of the layout.
Optionally, the method for extracting the critical area of the layout is further improved, and the method further includes:
and S6, representing the extracted critical area of the layout in a thermodynamic diagram form.
The invention provides a layout key region extraction system for integrated circuit layout failure region positioning, which comprises:
the layout level selection module is suitable for selecting the layout level of the key area to be extracted;
the grid point window division module is suitable for the layout level selection module to select layout levels and divide the grid point windows according to the grid point window division rule;
a product value extraction module, which is suitable for extracting the line width product value and the space product value of the graph in each grid point window;
a product threshold acquisition module adapted to extract product thresholds defined as key regions in historical mature stable production products, the product thresholds including line width product thresholds and space product thresholds;
and the judgment and extraction module is suitable for judging whether the graph in each grid point window is a key area according to the product threshold value and extracting the key area.
Optionally, the layout key region extraction system is further improved, the grid point window division module divides the layout hierarchy into a plurality of m × n grid point windows by taking the initial point of the lower left corner of the layout hierarchy as the origin (0, 0) and by the size w × w, each grid point window is provided with a corresponding intercepting graph, w is larger than or equal to 0, the row number m of each grid point window is larger than 1, the column number n of each grid point window is larger than 1, and the intercepting graph refers to the key layer layout graph in the grid point window.
Optionally, the layout key region extraction system is further improved, and the range of the preset size w is 0um-200 um.
Optionally, the layout key region extraction system is further improved, and the product value extraction module calculates the line width product value in the following manner;
determining minimum recommended value w of layout level line width according to manufacturing processrCalculating the line width product value of all the patterns in each grid point which is smaller than the recommended value,
Figure BDA0002278845250000031
wrrepresentative line width minimumRecommended value, wiActual value, a, representing line widthiRepresenting the area of the line width, n representing the column number of the grid point window, r being the recommend mark as DFM recommendation, i being the line width graph number in the grid point window; wherein when wr-wiIf < 0, then wr-wiTake 0.
Optionally, the layout key region extraction system is further improved, and the product value extraction module calculates the distance product value in the following way;
determining minimum recommended value s of layout level spacing according to manufacturing processrCalculating the interval product value of all the graphs in each grid point window smaller than the recommended value
Figure BDA0002278845250000041
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresenting the area of the interval, wherein m represents the row number of the lattice point window, r is the recommend mark and is recommended by DFM, and i is the interval graph number in the lattice point window; wherein when sr-siIf < 0, then sr-siTake 0.
Optionally, the layout key region extraction system is further improved, and the product threshold acquisition module acquires the line width product threshold and the space product threshold by adopting probability distribution calculation according to the product distribution range of the stable mass production product.
Optionally, the layout key region extraction system is further improved, and the probability distribution calculation is Gamma probability fitting solution.
Optionally, the layout key region extraction system is further improved, the point with the cumulative probability of g% is set as a threshold value in the probability distribution calculation, and the range of g is 80-100.
Optionally, the layout key region extraction system is further improved, and the judgment and extraction module extracts the graphic region higher than the grid point window of the line width product value threshold or the space product value threshold as the key region of the layout.
Optionally, further improving the layout key region extraction system, further includes:
and the display module is suitable for representing the extracted critical areas of the layout in a thermodynamic diagram form.
The invention provides a method for extracting key areas in a graph, which comprises the steps of firstly dividing a pre-extracted layout into grid point windows, extracting line width product values and space product values of graphs in each grid point window, judging whether the graphs in each grid point window are the key areas or not according to product value threshold values which are extracted from historical mature stable production products and defined as the key areas, and extracting the key areas. The key area of the pre-extracted layout level is judged by extracting the product threshold value defined as the key area from the historical mature stably-produced product, and because the condition for judging cheating by the product threshold value of the mature stably-produced product is utilized, compared with the prior art, the key area in the new product layout can be reduced to at least 30% of the original layout, the cycle time of subsequent failure analysis is saved by 70%, and the economic benefit of a manufacturer is greatly improved.
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The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic flow diagram of the extraction method of the present invention.
FIG. 2 is a schematic diagram of the grid point window division, in which A represents the grid point window, m represents the row number of the grid point window, and n represents the column number of the grid point window.
FIG. 3 is a schematic diagram of the extraction of line width product values in a grid point window.
Fig. 4 is a first schematic diagram of threshold solution.
FIG. 5 is a second schematic diagram of threshold solution showing cumulative probability value distributions.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As shown in fig. 1, a first embodiment of the layout key region extraction method provided by the present invention includes the following steps:
s1, determining the layout level of the key region to be extracted;
s2, dividing the extracted layout level into grid point windows according to grid point window division rules;
s3, extracting the line width product value and the space product value of the graph in each lattice point window;
s4, extracting product value threshold values defined as key areas from the historical mature stable production products, wherein the product value threshold values comprise line width product value threshold values and space product value threshold values;
and S5, judging whether the graph in each grid point window is a key area according to the product threshold value, and extracting the key area.
The layout key region extraction method comprises the steps of extracting a product threshold value defined as a key region from a historical mature stably-produced product, judging the key region of a pre-extracted layout level, and comparing the key region in a new product layout with the prior art to reduce the key region to be at least 30% of the original layout due to the utilization of a cheating judgment condition of the product threshold value of the mature stably-produced product, so that 70% of cycle time of subsequent failure analysis is saved, and the economic benefit of a manufacturer is greatly improved.
The second embodiment of the layout key region extraction method provided by the invention comprises the following steps:
s1, determining the layout level of the key region to be extracted;
s2, dividing the layout hierarchy into a plurality of m x n grid point windows by using the starting point of the lower left corner of the layout hierarchy as the origin (0, 0), wherein each grid point window is provided with a corresponding intercepting graph, 200um is larger than or equal to w and larger than or equal to 0, the row number m of each grid point window is larger than 1, the column number n of each grid point window is larger than 1, the intercepting graph refers to the key layer layout graph in each grid point window, and the intercepting graph is shown by referring to FIG. 2;
s3, extracting the line width product value and the space product value of the graph in each lattice point window;
wherein, the line width product value is obtained by the following steps;
s3.1, determining the minimum recommended value w of the line width of the layout level according to the manufacturing processr
S3.2, calculating the line width product value of all the graphs in each grid point window which is smaller than the recommended value,
Figure BDA0002278845250000061
wrrepresents a minimum recommended value of line width, wiRepresenting the actual value of the line width, aiRepresenting the area of the line width, n representing the column number of the grid point window, r being the recommend mark as DFM recommendation, i being the line width graph number in the grid point window;
wherein when wr-wiIf < 0, then wr-wiTake 0.
The distance product value is obtained by the following steps;
s3.3, determining the minimum recommended value S of the layout level spacing according to the manufacturing processr
S3.4, calculating the interval product value of all the graphs in each grid point window which is smaller than the recommended value
Figure BDA0002278845250000062
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresenting the area of the interval, wherein m represents the row number of the lattice point window, r is the recommend mark and is recommended by DFM, and i is the interval graph number in the lattice point window;
wherein when sr-siIf < 0, then sr-si Take 0.
S4, extracting product value threshold values defined as key areas from the historical mature stable production products, wherein the product value threshold values comprise line width product value threshold values and space product value threshold values; the line width product value threshold and the spacing product value threshold are obtained by adopting probability distribution calculation according to the product value distribution range of the stable mass production product, for example, the line width product value threshold and the spacing product value threshold are obtained by adopting Gamma probability fitting solution; wherein, the probability distribution calculation sets the point with the cumulative probability of g% as a threshold value, and the range of g is 80-100;
s5, extracting a graph area higher than a grid point window of a line width product value threshold or a space product value threshold as a key area of the layout;
and S6, representing the extracted critical area of the layout in a thermodynamic diagram form.
A second embodiment of the present invention will be further described with reference to the structure shown in fig. 3, in which fig. 3 is an actual graph in a certain grid window after grid windowing;
extracting the product of each grid point window, taking fig. 3 as an example, the graph contains rectangle 301 with line width w1 and area a 1; the line width of the rectangle 302 is w2, and the area is a 2; the maximum line width of the polygon 303 containing the L shape is w4, the minimum line width is w3, and the area is a 3; 301 and 303 have a minimum separation of s14, corresponding to an area of a 14; the minimum separation of 301 and 302 is s12, corresponding to an area a 12. Wherein w3 and w4 are both largeAt minimum linewidth recommendation wrW1 and w2 are less than the minimum recommended line width wr(ii) a Meanwhile, s12 and s14 are also smaller than the minimum spacing recommendation value sr. According to the lattice point product value calculation method provided by the invention, the calculation can be as follows:
line width product value: w ═ a1+ (Wr-W1) × (Wr-W2) × a 2;
the product of the distances: s ═ S12 × a12+ (Sr-S14) × a 14;
the layout product probability distribution of the hierarchically stable mass-produced product is shown in fig. 4. Where 401 represents the probability of occurrence of the (550,650) interval product value, where the original probability distribution is fit to a Gamma distribution, such as curve 402. 404 of FIG. 5 is a cumulative probability distribution plot of 402Gamma distribution of FIG. 4. As shown in 403 in fig. 4, the product value corresponding to 90% is used as a warning line, and the corresponding product value threshold value is obtained as 1090.
And expressing the product values of all grid points of the layout by using corresponding colors to form a thermodynamic diagram commonly used in the industry.
The lattice window region exceeding the threshold 1090 in the thermodynamic diagram is a key region in the layout, and failure analysis needs to be performed in an important mode.
The invention provides a layout key region extraction system for integrated circuit layout failure region positioning, comprising:
the layout level selection module is suitable for selecting the layout level of the key area to be extracted;
the grid point window division module is suitable for the layout level selection module to select layout levels and divide the grid point windows according to the grid point window division rule;
a product value extraction module, which is suitable for extracting the line width product value and the space product value of the graph in each grid point window;
a product threshold acquisition module adapted to extract product thresholds defined as key regions in historical mature stable production products, the product thresholds including line width product thresholds and space product thresholds;
and the judgment and extraction module is suitable for judging whether the graph in each grid point window is a key area according to the product threshold value and extracting the key area.
The invention provides a layout key region extraction system for integrated circuit layout failure region positioning, comprising:
the layout level selection module is suitable for selecting the layout level of the key area to be extracted;
the grid point window dividing module is used for dividing the layout hierarchy into a plurality of m × n grid point windows by taking the initial point of the lower left corner of the layout hierarchy as an original point (0, 0) and by the size w × w, wherein each grid point window is provided with a corresponding intercepted graph, and the intercepted graph refers to a key layer layout graph in the grid point window; wherein w is more than or equal to 0, the row number m of the lattice point window is more than 1, the column number n of the lattice point window is more than 1, and the range of w is 0um-200 um.
The product value extraction module calculates the line width product value in the following mode;
determining minimum recommended value w of layout level line width according to manufacturing processrCalculating the line width product value of all the graphs in each grid point window which is smaller than the recommended value,
Figure BDA0002278845250000081
wrrepresents a minimum recommended value of line width, wiRepresenting the actual value of the line width, aiRepresenting the area of the line width, wherein n represents the column number of the lattice point window, n is more than 1, r is the recommend mark and is recommended by DFM, and i is the line width graph number in the lattice point window; wherein when wr-wiIf < 0, then wr-wiTake 0.
Calculating a pitch product value in the following manner;
determining minimum recommended value s of layout level spacing according to manufacturing processrCalculating the interval product value of all the graphs in each grid point window smaller than the recommended value
Figure BDA0002278845250000082
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresenting the area of the interval, wherein m represents the row number of the lattice point window, m is greater than 1r, namely, recommend is marked as DFM recommendation, and i is the interval graph number in the lattice point window; wherein whensr-siIf < 0, then sr-si Take 0.
And the product value threshold acquisition module is used for calculating and acquiring a line width product value threshold and a space product value threshold by adopting probability distribution according to the product value distribution range of the stable mass production product. The probability distribution calculation is Gamma probability fitting solution, points with g percent of cumulative probability are set as threshold values in the probability distribution calculation, and the range of g is 80-100;
and the judgment and extraction module is used for extracting the graphic area of the grid point window higher than the line width product value threshold value or the space product value threshold value as a key area of the layout and extracting the key area.
And the display module is suitable for representing the extracted critical areas of the layout in a thermodynamic diagram form.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (20)

1. A layout key region extraction method is used for integrated circuit layout failure region positioning, and is characterized by comprising the following steps:
s1, determining the layout level of the key region to be extracted;
s2, dividing the extracted layout level into grid point windows according to grid point window division rules;
s3, extracting the line width product value and the space product value of the graph in each lattice point window;
s4, extracting product value threshold values defined as key areas from the historical mature stable production products, wherein the product value threshold values comprise line width product value threshold values and space product value threshold values;
and S5, judging whether the graph in each grid point window is a key area according to the product threshold value, and extracting the key area.
2. The layout key region extraction method according to claim 1, characterized in that: in step S2, the lattice point window division rule is as follows;
taking the initial point of the lower left corner of the layout hierarchy as the origin (0, 0), dividing the layout hierarchy into a plurality of m x n grid point windows by the size w x w, wherein each grid point window is provided with a corresponding intercepting graph, w is more than or equal to 0, the row number m of each grid point window is more than 1, the column number n of each grid point window is more than 1, and the intercepting graph refers to the key layer layout graph in each grid point window.
3. The layout key region extraction method according to claim 2, characterized in that: the range of the preset size w is 0um-200 um.
4. The layout key region extraction method according to claim 1, characterized in that: in step S3, the line width product value is obtained by the following calculation;
s3.1, determining the minimum recommended value w of the line width of the layout level according to the manufacturing processr
S3.2, calculating the line width product value of all the graphs in each grid point window which is smaller than the recommended value,
Figure FDA0002278845240000011
wrrepresents a minimum recommended value of line width, wiRepresenting the actual value of the line width, aiRepresenting the area of the line width, n representing the column number of the grid point window, r being the recommend mark as DFM recommendation, i being the line width graph number in the grid point window;
wherein when wr-wiIf < 0, then wr-wiTake 0.
5. The layout key region extraction method according to claim 1, characterized in that: in step S3, the pitch product value is obtained by the following calculation;
s3.3, determining the minimum recommended value S of the layout level spacing according to the manufacturing processr
S3.4, calculating the interval product value of all the graphs in each grid point window which is smaller than the recommended value
Figure FDA0002278845240000012
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresenting the area of the interval, wherein m represents the row number of the lattice point window, r is the recommend mark and is recommended by DFM, and i is the interval graph number in the lattice point window;
wherein when sr-siIf < 0, then sr-siTake 0.
6. The layout key region extraction method according to claim 1, characterized in that: in step S4, the line width product threshold and the space product threshold are calculated and obtained by probability distribution according to the product distribution range of the product that has been stably produced in large quantities.
7. The layout key region extraction method according to claim 6, characterized in that: the probability distribution calculation is a Gamma probability fitting solution.
8. The layout key region extraction method according to claim 7, characterized in that: the probability distribution calculation sets a threshold at the point where the cumulative probability is g%, with g ranging from 80 to 100.
9. The layout key region extraction method according to claim 1, characterized in that: in step S5, the graphic area higher than the line width product threshold or the space product threshold grid point window is extracted as the key area of the layout.
10. The layout key region extraction method according to any one of claims 1 to 9, further comprising:
and S6, representing the extracted critical area of the layout in a thermodynamic diagram form.
11. A territory key region extraction system is used for locating a failure region of an integrated circuit territory and is characterized by comprising the following components:
the layout level selection module is suitable for selecting the layout level of the key area to be extracted;
the grid point window division module is suitable for the layout level selection module to select layout levels and divide the grid point windows according to the grid point window division rule;
a product value extraction module, which is suitable for extracting the line width product value and the space product value of the graph in each grid point window;
a product threshold acquisition module adapted to extract product thresholds defined as key regions in historical mature stable production products, the product thresholds including line width product thresholds and space product thresholds;
and the judgment and extraction module is suitable for judging whether the graph in each grid point window is a key area according to the product threshold value and extracting the key area.
12. The layout key region extraction system of claim 11, wherein: the grid point window dividing module divides the layout hierarchy into a plurality of m x n grid point windows by taking the initial point of the lower left corner of the layout hierarchy as the original point (0, 0) and by the size w x w, wherein each grid point window is provided with a corresponding intercepting graph, w is more than or equal to 0, the row number m of each grid point window is more than 1, the column number n of each grid point window is more than 1, and the intercepting graph refers to the key layer layout graph in each grid point window.
13. The layout key region extraction system according to claim 12, characterized in that: the preset size w ranges from 0um to 200 um.
14. The layout key region extraction system of claim 11, wherein:
the product value extraction module calculates the line width product value in the following mode;
determining minimum recommended value w of layout level line width according to manufacturing processrCalculating the line width product value of all the graphs in each grid point window which is smaller than the recommended value,
Figure FDA0002278845240000031
wrminimum recommended value, w, of representative line widthiRepresenting the actual value of the line width, aiRepresenting the area of the line width, n representing the column number of the grid point window, r being the recommend mark as DFM recommendation, i being the line width graph number in the grid point window; wherein when wr-wiIf < 0, then wr-wiTake 0.
15. The layout key region extraction system of claim 11, wherein: the product value extraction module calculates the distance product value in the following mode;
determining minimum recommended value s of layout level spacing according to manufacturing processrCalculating the interval product value of all the graphs in each grid point window smaller than the recommended value
Figure FDA0002278845240000032
srRepresenting the minimum recommended value of the spacing, siRepresenting the actual value of the spacing, biRepresenting the area of the interval, wherein m represents the row number of the lattice point window, r is the recommend mark and is recommended by DFM, and i is the interval graph number in the lattice point window; wherein when sr-siIf < 0, then sr-siTake 0.
16. The layout key region extraction system of claim 11, wherein: the product value threshold acquisition module adopts probability distribution calculation to acquire a line width product value threshold and a space product value threshold according to the product value distribution range of the stable mass production product.
17. The layout key region extraction system of claim 16, wherein: the probability distribution calculation is a Gamma probability fitting solution.
18. The layout key region extraction system of claim 16, wherein: the probability distribution calculation sets a threshold at the point where the cumulative probability is g%, with g ranging from 80 to 100.
19. The layout key region extraction system of claim 11, wherein: and the judgment and extraction module extracts the graphic area of the grid point window higher than the line width product value threshold or the space product value threshold as a key area of the layout.
20. The layout key region extraction system according to any one of claims 11 to 19, further comprising:
and the display module is suitable for representing the extracted critical areas of the layout in a thermodynamic diagram form.
CN201911133017.3A 2019-11-19 2019-11-19 Layout key region extraction method and extraction system thereof Pending CN110909659A (en)

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