CN110896104B - Multiple gate power MOSFET device - Google Patents

Multiple gate power MOSFET device Download PDF

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Publication number
CN110896104B
CN110896104B CN201910203692.2A CN201910203692A CN110896104B CN 110896104 B CN110896104 B CN 110896104B CN 201910203692 A CN201910203692 A CN 201910203692A CN 110896104 B CN110896104 B CN 110896104B
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pillar
gate conductor
power mosfet
gate
drain
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CN110896104A (en
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汤铭
焦世平
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PTEK Tech Co Ltd
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PTEK Tech Co Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present disclosure provides a multiple gate power MOSFET (power metal oxide semiconductor field effect transistor) device disposed on a substrate. The multiple gate power MOSFET device includes a first transistor cell, a second transistor cell, and a first insulator. The first transistor unit is provided with a first drain electrode column, a first source electrode column and a first grid electrode conductor, wherein the first grid electrode conductor is arranged between the first drain electrode column and the first source electrode column. The second transistor unit is provided with a second drain electrode column, a second source electrode column and a second grid electrode conductor, wherein the second grid electrode conductor is arranged between the second drain electrode column and the second source electrode column. The first insulator is disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically isolates the second transistor cell from the first transistor cell. During operation, the first transistor cell and the second transistor cell share a common source and a common drain, and the conductive states of the first gate conductor and the second gate conductor are separately controlled.

Description

Multiple gate power MOSFET device
Technical Field
The present disclosure claims priority and benefits of U.S. official application No. 16/130,409 of the 2018/09/13 application, the contents of which are incorporated herein by reference in their entirety.
The present disclosure relates to semiconductor devices, and more particularly to a multiple gate power MOSFET (metal-oxide-semiconductor field-effect transistor) device.
Background
Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) having trench gate structures are widely used because of their low conduction Resistance (RDSON) performance. U.S. patent application Ser. No. 11/930,380 (application Ser. No. 31, 10/2007) discloses a trench MOS gate device that provides a constant conduction resistance. In addition, see U.S. Pat. No. 4, 5,973,367 (granted by the following 10 th and 26 th 1999), which is incorporated herein by reference, discloses a double diffused vertical metal oxide semiconductor field effect transistor (double-diffused vertical MOSFET) in which the gate is formed in a trench and is separated by a P-doped region.
The above description of "prior art" is merely provided as background, and is not admitted to disclose the subject matter of the present disclosure, do not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure.
Disclosure of Invention
The present disclosure provides a power MOSFET device having a multiple gate transistor disposed on a substrate. The multiple gate transistor includes a first transistor cell, a second transistor cell, and a first insulator. The first transistor unit is provided with a first drain electrode column, a first source electrode column and a first grid electrode conductor, wherein the first grid electrode conductor is arranged between the first drain electrode column and the first source electrode column. The second transistor unit is provided with a second drain electrode column, a second source electrode column and a second grid electrode conductor, wherein the second grid electrode conductor is arranged between the second drain electrode column and the second source electrode column. The first insulator is disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically isolates the second transistor cell from the first transistor cell. During operation, the first transistor cell and the second transistor cell share a common source and a common drain, and the conductive states of the first gate conductor and the second gate conductor are separately controlled.
In some embodiments, the first gate conductor includes a trench gate surrounding the first drain pillar and the first source pillar.
In some embodiments, the first gate conductor includes an insulating material electrically insulating the trench gate from the first drain pillar and the first source pillar.
In some embodiments, the first gate conductor includes a gate oxide layer, a portion of the gate oxide layer being formed over a sidewall of the first drain pillar and the first source pillar, wherein the gate oxide layer separates the insulating material from the first drain pillar and the source pillar.
In some embodiments, the first insulator includes at least one sidewall in direct contact with the insulating material and the gate oxide.
In some embodiments, the first insulator includes at least one sidewall that directly contacts the substrate.
In some embodiments, a portion of the gate oxide of the first gate conductor is located over the substrate and coplanar with the first insulator.
In some embodiments, the first drain pillar includes a body and a metal silicide layer disposed over the body.
In some embodiments, the body of the first drain pillar includes a lightly doped region and a heavily doped region above the lightly doped region.
In some embodiments, the body of the first drain pillar includes an N-type doping.
In some embodiments, the substrate includes a double diffusion layer disposed under the first drain pillar and the first gate conductor.
In some embodiments, the double diffusion layer is disposed below the first insulator.
In some embodiments, the first drain pillar includes a body and a metal silicide layer disposed over the body.
In some embodiments, the body of the first source pillar includes a well portion; a central portion disposed above the well portion; and a wall portion surrounding the central portion.
In some embodiments, the central portion includes a P-type doping and the wall portion includes an N-type doping.
In some embodiments, the first transistor cell and the second transistor cell are physically insulated by the first insulator.
In some embodiments, the multiple gate transistor further comprises a third transistor cell having a third drain pillar, a third source pillar, and a third gate conductor disposed between the third drain pillar and the third source pillar, the third gate conductor being electrically isolated from the first gate conductor and the second gate conductor by the second insulator.
In some embodiments, the first insulator and the second insulator are physically connected.
In some embodiments, the multiple gate transistor further comprises a fourth transistor cell having a fourth drain pillar, a fourth source pillar, and the first gate conductor shared with the first transistor cell, wherein the fourth transistor cell and the first transistor cell together provide a resistance that is different from the resistance provided by the second transistor cell when the conductive states of the first gate conductor and the second gate conductor are both conductive.
In some embodiments, the drain pillars and the source pillars of the first transistor unit and the fourth transistor unit are disposed above the substrate in an interleaved manner.
The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Drawings
The disclosure will become more fully understood from the disclosure, when the detailed description and claims are taken together with the accompanying drawings, wherein like reference numerals refer to like elements.
Fig. 1 is a top view illustrating a multiple gate power MOSFET device according to some embodiments of the present disclosure.
Fig. 2 is a schematic diagram illustrating a connection configuration of the multiple gate power MOSFET device of fig. 1 according to some embodiments of the present disclosure.
Fig. 3 is a schematic table illustrating the resistance of the power MOSFET device of fig. 1 in accordance with some embodiments of the present disclosure.
Fig. 4 is a perspective view illustrating a portion of the power MOSFET device of fig. 1 in accordance with some embodiments of the present disclosure.
Fig. 5 is a cross-sectional view illustrating a cross-sectional structure of a power MOSFET device according to some embodiments of the present disclosure along line A-A' in fig. 4.
Fig. 6 is a cross-sectional view illustrating a cross-sectional structure of a power MOSFET device according to some embodiments of the present disclosure along line B-B' in fig. 4.
Wherein reference numerals are as follows:
100. multiple gate transistor
101. First gate conductor
101A trench gate
102. Second gate conductor
102A trench gate
103. Third gate conductor
103A trench gate
104. First insulator
104A side wall
104B side wall
104C side wall
105. Second insulator
105A side wall
105B side wall
107. Insulating material
108. Gate oxide layer
109. Insulating material
110. Gate oxide layer
111. Insulating material
112. Gate oxide layer
401. Substrate
510. Source pole
511. Metal silicide layer
512. Well section
513. A central portion
514. Wall portion
520. Drain electrode column
521. Metal silicide layer
522. Heavily doped region
523. Lightly doped region
524. Double diffusion layer
530. Source pole
540. Drain electrode column
550. Source pole
560. Drain electrode column
D drain electrode column
RDSon conductive resistor
RDSon1 conductive resistor
RDSon2 conductive resistor
RDSon3 conductive resistor
S source pole
Detailed Description
The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the disclosure, however, the disclosure is not limited to such embodiments. Furthermore, the following embodiments may be suitably combined to complete other embodiments.
"some embodiments," "example embodiments," "other embodiments," etc., mean that the embodiments described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, although it may.
The following description provides detailed steps and structures in order that the present disclosure may be fully understood. It will be apparent that implementations of the present disclosure are not limited to the specific details known to those skilled in the art. In other instances, well-known structures and steps have not been described in detail in order to not unnecessarily obscure the present disclosure. Preferred embodiments of the present disclosure are detailed below. However, the present disclosure may be widely practiced in other embodiments besides the implementation. The scope of the present disclosure is not limited to the contents of the embodiments, but is defined by the claims.
Fig. 1 is a top view illustrating a power MOSFET device according to some embodiments of the present disclosure. In some embodiments of the present disclosure, the power MOSFET device includes a multiple gate transistor 100 disposed over a substrate 401. The multiple gate transistor 100 includes a first mosfet cell having a first gate conductor 101; a second mosfet cell having a second gate conductor 102; and a third mosfet cell having a third gate conductor 103.
In some embodiments of the present disclosure, the metal oxide semiconductor field effect transistor cells of the multiple gate transistor 100 have different numbers of transistor cells. For example, a transistor cell is composed of a drain pillar (denoted by "D" in FIG. 1) and a source pillar (denoted by "S" in FIG. 1). In some embodiments of the present disclosure, the first mosfet cell has a first gate conductor 101, the first gate conductor 101 having three transistor cells; the second mosfet cell has a second gate conductor 102, the second gate conductor 102 having three mosfet cells; the third mosfet cell has a third gate conductor 103, the third gate conductor 103 having sixteen mosfet cells.
In some embodiments of the present disclosure, the drain pillars and the source pillars are disposed above the substrate in an alternating manner. In some embodiments of the present disclosure, the drain pillar and the source are rectangular when viewed from above.
In some embodiments of the present disclosure, the first gate conductor 101, the second gate conductor 102, and the third gate conductor 103 are a trench gate. In some embodiments of the present disclosure, the trench gate surrounds the drain pillar and the source pillar.
In some embodiments of the present disclosure, the first gate conductor 101, the second gate conductor 102, and the third gate conductor 103 each surround a different number of transistor cells.
In some embodiments of the present disclosure, different numbers of transistor cells are designed such that the mosfet cells can provide different resistances.
Fig. 2 is a schematic diagram illustrating a connection configuration of the power MOSFET device of fig. 1 according to some embodiments of the present disclosure. In some embodiments of the present disclosure, the first mosfet cell, the second mosfet cell, and the third mosfet cell of the multiple gate transistor 100 are represented in fig. 2 by three mosfet symbols. In some embodiments of the present disclosure, the first mosfet cell, the second mosfet cell, and the third mosfet cell share a common source and a common drain.
In some embodiments of the present disclosure, the first gate conductor 101, the second gate conductor 102, and the third gate conductor 103 are denoted as "gate 1", "gate 2", and "gate 3" in fig. 2, and the "gate 1", "gate 2", and "gate 3" are each separately controlled, that is, the conductive states of the first gate conductor 101, the second gate conductor 102, and the third gate conductor 103 may be set to be ON ("ON") or OFF ("OFF"), respectively.
Fig. 3 is a schematic table illustrating the resistance of the power MOSFET device of fig. 1 in accordance with some embodiments of the present disclosure. In some embodiments of the present disclosure, the first mosfet cell of the multiple gate transistor 100 provides an on-resistance RDSON1 when the conductive state of the first gate conductor 101 is on. In some embodiments of the present disclosure, the second gate conductor 102 and the third gate conductor 103 may provide conductive resistance resistances RDSON2 and RDSON3 when their conductive states are set to ON. In some embodiments of the present disclosure, the conductive resistance RDSON1, the conductive resistance RDSON2, and the conductive resistance RDSON3 are different from one another due to the different numbers of transistor cells of the metal oxide semiconductor field effect transistor cells. In some embodiments of the present disclosure, the conductive resistances RDSON1, RDSON2, and RDSON3 may be combined into seven possible conductive resistance RDSON values.
Fig. 4 is a perspective view illustrating a portion of the power MOSFET device of fig. 1 in accordance with some embodiments of the present disclosure. In some embodiments of the present disclosure, the first mosfet cell has a drain pillar 540 and a source pillar 550, and the first gate conductor 101 surrounds the drain pillar 540 and the source pillar 550. In some embodiments of the present disclosure, the second mosfet cell has a drain pillar 520 and a source pillar 510, and the second gate conductor 102 surrounds the drain pillar 520 and the source pillar 510. In some embodiments of the present disclosure, the third mosfet cell has a drain pillar 560 and a source pillar 530, and the third gate conductor 103 surrounds the drain pillar 560 and the source pillar 530.
In some embodiments of the present disclosure, the first gate conductor 101, the drain pillar 540, and the source pillar 550 may function as one transistor cell.
In some embodiments of the present disclosure, the first gate conductor 101 of the first mosfet cell is electrically insulated from the second gate conductor 102 of the second mosfet cell by a first insulator 104 disposed over the substrate 401.
In some embodiments of the present disclosure, the first mosfet cell and the second mosfet cell are physically insulated from each other by the first insulator.
In some embodiments of the present disclosure, the third gate conductor 103 of the third mosfet cell is electrically insulated from the first gate conductor 101 and the second gate conductor 102 by a second insulator 105 disposed over the substrate 401.
In some embodiments of the present disclosure, the first insulator 104 and the second insulator 105 are physically connected.
Fig. 5 is a cross-sectional view illustrating a cross-sectional structure of a power MOSFET device according to some embodiments of the present disclosure along line A-A' in fig. 4. In some embodiments of the present disclosure, the second gate conductor 102 includes an insulating material 107, the insulating material 107 electrically insulating the trench gate 102A from the source and drain pillars in the second mosfet cell, such as from the source and drain pillars 510, 520.
In some embodiments of the present disclosure, the second gate conductor 102 further includes a gate oxide layer 108. In some embodiments of the present disclosure, a portion of the gate oxide layer 108 is formed on a sidewall of the source and drain pillars, such as source pillar 510 and drain pillar 520. In some embodiments of the present disclosure, the gate oxide layer 108 separates the insulating material 107 from the source pillars 510 and the drain pillars 520.
In some embodiments of the present disclosure, the first gate conductor 101 and the third gate conductor 103 have a similar structure as the third gate conductor 103.
In some embodiments of the present disclosure, the third gate conductor 103 includes an insulating material 109, the insulating material 109 electrically insulating the trench gate 103A from the source and drain pillars in the third mosfet cell, such as from the source pillar 530 and the drain pillar 560.
In some embodiments of the present disclosure, the third gate conductor 103 further includes a gate oxide layer 110. In some embodiments of the present disclosure, a portion of the gate oxide layer 110 is formed on a sidewall of the source and drain pillars, e.g., the source pillar 530. In some embodiments of the present disclosure, the gate oxide layer 110 separates the insulating material 109 from the source pillars 530.
In some embodiments of the present disclosure, the second insulator 105 has a sidewall 105A directly contacting the source pillar 520 of the second mosfet cell, and the second insulator 105 has a sidewall 105B directly contacting the source pillar 530 of the third mosfet cell.
In some embodiments, the source pillar 510 includes a body and a metal silicide layer 511, the metal silicide layer 511 being disposed over the body.
In some embodiments, the body of source pillar 510 includes a well portion 512; a central portion 513 disposed above the well portion 512; and a wall portion 514 surrounding the central portion 512.
In some embodiments of the present disclosure, well portion 512 and central portion 513 comprise a P-type doping. In some embodiments of the present disclosure, the central portion 513 has a higher doping concentration than the well portion 512.
In some embodiments of the present disclosure, wall portion 514 includes an N-type doping.
In some embodiments, the source pillar 520 includes a body and a metal silicide layer 521, and the metal silicide layer 521 is disposed over the body.
In some embodiments of the present disclosure, the body of the drain pillar 520 includes a lightly doped region 520 and a heavily doped region 522 above the lightly doped region 520.
In some embodiments of the present disclosure, the body of the drain pillar 520 includes an N-type doping.
In some embodiments of the present disclosure, the substrate 401 includes a double diffusion layer 524 disposed under the drain pillar 520 and the second gate conductor 102. In some embodiments of the present disclosure, double diffusion layer 524 includes an N-type doping. In some embodiments of the present disclosure, this doping concentration of double diffusion layer 524 varies gradually within double diffusion layer 524, with the doping concentration in the portion near drain pillar 520 being greater than the doping concentration in the portion near substrate 401.
In some embodiments of the present disclosure, a double diffusion layer 524 is disposed below the second insulator. In some embodiments of the present disclosure, the second insulator 105 directly contacts the double diffusion layer 524.
Fig. 6 is a cross-sectional view illustrating a cross-sectional structure of a power MOSFET device according to some embodiments of the present disclosure along line B-B' in fig. 4. In some embodiments of the present disclosure, the first gate conductor 101 includes an insulating material 111, the insulating material 111 electrically isolating the trench gate 101A from the source and drain pillars in the first mosfet cell.
In some embodiments of the present disclosure, the first gate conductor 101 further includes a gate oxide layer 112. In some embodiments of the present disclosure, a portion of the gate oxide layer 112 is formed on a sidewall of the source and drain pillars of the first mosfet cell. The gate oxide 112 separates the insulating material 11 from the source and drain pillars of the first mosfet cell.
In some embodiments, the first insulator 104 includes an insulating material 111 and a gate oxide layer 112 with a sidewall 104A in direct contact with the first gate conductor 101.
In some embodiments, the first insulator 104 includes an insulating material 107 and a gate oxide layer 108 having a sidewall 104B in direct contact with the first gate conductor 102.
In some embodiments, the first insulator 104 includes a sidewall 104C that directly contacts the substrate 401.
In some embodiments of the present disclosure, a portion of the gate oxide layer 112 of the first gate conductor 101 is located above the substrate 401 and below the trench gate 101A and coplanar with the first insulator 104. In some embodiments of the present disclosure, a portion of the gate oxide layer 108 of the second gate conductor 108 is located above the substrate 401 and below the trench gate 102A and coplanar with the first insulator 104.
The present disclosure provides a power MOSFET device having a multiple gate transistor disposed on a substrate. The multiple gate transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gate transistor further includes a second transistor unit having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gate transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically isolates the second transistor cell from the first transistor cell. During operation, the first transistor cell and the second transistor cell share a common source and a common drain, and the conductive states of the first gate conductor and the second gate conductor are separately controlled.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or future developed that perform the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of the present disclosure.

Claims (19)

1. A power MOSFET device comprising:
a multiple gate transistor disposed over a substrate, comprising:
a first transistor unit having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar;
a second transistor unit having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar; and
a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor, wherein the first insulator electrically insulates the second gate conductor from the first gate conductor;
wherein the first transistor cell and the second transistor cell share a common source and a common drain during operation, the conductive states of the first gate conductor and the second gate conductor are separately controlled,
the first gate conductor comprises a trench gate surrounding the first drain pillar and the first source pillar.
2. The power MOSFET device of claim 1, wherein said first gate conductor comprises an insulating material electrically insulating said trench gate from said first drain pillar and said first source pillar.
3. The power MOSFET device of claim 2, wherein said first gate conductor comprises a gate oxide layer, a portion of said gate oxide layer being formed over a sidewall of said first drain pillar and said first source pillar, said gate oxide layer separating said insulating material from said first drain pillar and said source pillar.
4. The power MOSFET device of claim 3, wherein said first insulator comprises at least one sidewall in direct contact with said insulating material and said gate oxide layer.
5. The power MOSFET device of claim 1, wherein said first insulator comprises at least one sidewall in direct contact with said substrate.
6. The power MOSFET device of claim 3, wherein a portion of said gate oxide of said first gate conductor is above said substrate and coplanar with said first insulator.
7. The power MOSFET device of claim 1, wherein said first drain pillar comprises a body and a metal silicide layer disposed above said body.
8. The power MOSFET device of claim 7, wherein said body of said first drain pillar comprises a lightly doped region and a heavily doped region above said lightly doped region.
9. The power MOSFET device of claim 8, wherein said body of said first drain pillar comprises an N-type doping.
10. The power MOSFET device of claim 1, wherein said substrate comprises a double-diffusion layer disposed under said first drain pillar and said first gate conductor.
11. The power MOSFET device of claim 10, wherein said double-diffusion layer is disposed below said first insulator.
12. The power MOSFET device of claim 2, wherein said first source pillar comprises a body and a metal silicide layer disposed above said body.
13. The power MOSFET device of claim 12, wherein said body of said first source pillar comprises:
a well section;
a central portion disposed above the well portion; and
a wall portion surrounding the central portion.
14. The power MOSFET device of claim 13, wherein said central portion comprises a P-type doping and said wall portion comprises an N-type doping.
15. The power MOSFET device of claim 1, wherein said first transistor cell and said second transistor cell are physically insulated by said first insulator.
16. The power MOSFET device of claim 1, further comprising a third transistor cell having a third drain pillar, a third source pillar, and a third gate conductor disposed between said third drain pillar and said third source pillar, said third gate conductor being electrically isolated from said first gate conductor and said second gate conductor by a second insulator.
17. The power MOSFET device of claim 16, wherein said first insulator and said second insulator are physically connected.
18. The power MOSFET device of claim 1, further comprising a fourth transistor cell having a fourth drain pillar, a fourth source pillar, and said first gate conductor common to said first transistor cell, wherein said fourth transistor cell and said first transistor cell together provide a resistance that is different from a resistance provided by said second transistor cell when both conductive states of said first gate conductor and said second gate conductor are conductive.
19. The power MOSFET device of claim 18, wherein said drain pillars and said source pillars of said first transistor cell and said fourth transistor cell are disposed above said substrate in an alternating fashion.
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