CN110895642A

CN110895642A - Microprocessor instruction level random verification method and device

Info

Publication number: CN110895642A
Application number: CN201810974237.8A
Authority: CN
Inventors: 王朋宇
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2018-08-24
Filing date: 2018-08-24
Publication date: 2020-03-20
Anticipated expiration: 2038-08-24
Also published as: CN110895642B

Abstract

The invention provides a microprocessor instruction level random verification method and a microprocessor instruction level random verification device. The microprocessor instruction level random verification method comprises the following steps: generating a random instruction and operation data related to the operation of the random instruction; if the random instruction is a first access instruction, updating the virtual page number lookup table according to the first access address; the virtual page number lookup table is used for indicating whether virtual page numbers corresponding to the virtual addresses are mapped in a one-to-one correspondence with physical page numbers; and executing the random instruction according to the operation data and the virtual page number lookup table so as to realize instruction-level random verification of the microprocessor. According to the microprocessor instruction level random verification method provided by the invention, the mapping relation between the virtual page number and the physical page number can be constructed through the virtual page number lookup table, and the sufficiency of instruction level random verification is improved.

Description

Microprocessor instruction level random verification method and device

Technical Field

The invention relates to the technical field of computers, in particular to a microprocessor instruction level random verification method and a microprocessor instruction level random verification device.

Background

Instruction level random verification based on simulation is a method for verifying a microprocessor by directly operating instruction level random verification vectors on the basis of no operating system or even no boot program. Emulation-based instruction-level random verification is the most dominant verification method for microprocessor verification. According to statistics, more than three-quarters of design errors are discovered by running instruction level random verification vectors throughout the microprocessor verification process.

In a von neumann computer, programs (or instructions) and data are stored in a memory inside the computer. Memory internal to a computer typically includes memory external to the microprocessor and cache memory internal to the microprocessor. Any program is first fetched from memory before being executed by the computer. In the simulation-based microprocessor instruction level random verification process, the microprocessor can fetch data and programs from the memory for execution only by storing the programs and the data in the memory of the computer according to the mapping relation of virtual addresses and real addresses.

Currently, for the storage of instructions and data in memory, the address of each instruction and data has a corresponding virtual page number. Each virtual page number is assigned a physical page number. The page table of the virtual-real address mapping is one-to-one correspondence of virtual page numbers and physical page numbers. This results in many states in the microprocessor design not being verified, resulting in insufficient verification of the processor and poor verification results.

Disclosure of Invention

The invention provides a microprocessor instruction level random verification method and device, which improve the sufficiency of instruction level random verification.

In a first aspect, the present invention provides a microprocessor instruction level random verification method, including:

generating a random instruction and operation data related to the operation of the random instruction;

if the random instruction is a first access instruction, updating a virtual page number lookup table according to a first access address; the first memory access address of the first memory access instruction is one of a plurality of virtual addresses mapped to a target physical address, and the virtual page number lookup table is used for indicating whether virtual page numbers corresponding to the virtual addresses and physical page numbers are mapped in a one-to-one correspondence manner;

and operating the random instruction according to the operating data and the virtual page number lookup table so as to realize instruction level random verification of the microprocessor.

Optionally, in a possible implementation manner of the first aspect, the virtual page number lookup table includes at least one address mapping record, where the address mapping record includes identification bit information and a virtual page number corresponding to a virtual address; and mapping virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information into the same physical page number.

Optionally, in a possible implementation manner of the first aspect, the updating the virtual page number lookup table according to the first access address includes:

judging whether a virtual page number corresponding to the first memory access address exists in the virtual page number lookup table or not;

if the virtual page number does not exist in the virtual page number lookup table, adding a first address mapping record in the virtual page number lookup table, wherein the first address mapping record comprises first identification bit information and a virtual page number corresponding to the first memory access address, and the first identification bit information is identification bit information which exists in the virtual page number lookup table and is less than a preset number, or is identification bit information which does not exist in the virtual page number lookup table;

if the virtual page number exists, adding a second address mapping record in the virtual page number lookup table, wherein the second address mapping record comprises second identification bit information and a virtual page number corresponding to the first memory access address, and the second identification bit information is identification bit information which exists in the virtual page number lookup table, is smaller than the preset number, is different from target identification bit information, or is identification bit information which does not exist in the virtual page number lookup table; and the target identification bit information is identification bit information corresponding to the first memory access address in the virtual page number lookup table.

Optionally, in a possible implementation manner of the first aspect, the address mapping record further includes mapping identification information;

the updating of the virtual page number lookup table according to the first memory access address further comprises:

judging whether mapping identification information included in at least one address mapping record which is the same as the first identification bit information or the second identification bit information in the virtual page number lookup table is equal to a preset first numerical value or not;

if not, determining a target address mapping record in the at least one address mapping record, and setting mapping identification information in the target address mapping record as the preset first numerical value.

Optionally, in a possible implementation manner of the first aspect, before the executing the random instruction according to the execution data and the virtual page number lookup table, the method further includes:

if the random instruction is a second memory access instruction, adding a third address mapping record in the virtual page number lookup table, wherein the third address mapping record comprises third identification bit information and a virtual page number corresponding to a second memory access address, and the third identification bit information is a preset second numerical value; and mapping the second memory access address of the second memory access instruction and the target physical address in a one-to-one correspondence manner.

Optionally, in a possible implementation manner of the first aspect, adding a third address mapping record to the virtual page number lookup table includes:

when the virtual page number corresponding to the second memory access address does not exist in the virtual page number lookup table, adding the third address mapping record in the virtual page number lookup table; alternatively, the first and second electrodes may be,

and when the virtual page number corresponding to the second memory access address exists in the virtual page number lookup table and the identification bit information corresponding to the virtual page number corresponding to the second memory access address is not the preset second numerical value, adding the third address mapping record in the virtual page number lookup table.

Optionally, in a possible implementation manner of the first aspect, the method further includes:

if the virtual page number corresponding to the address of the random instruction does not exist in the virtual page number lookup table, adding a fourth address mapping record in the virtual page number lookup table, where the fourth address mapping record includes fourth identification bit information and the virtual page number corresponding to the address of the random instruction, and the fourth identification bit information is a preset third numerical value.

Optionally, in a possible implementation manner of the first aspect, the executing the random instruction according to the execution data and the virtual page number lookup table to implement instruction-level random verification of the microprocessor includes:

operating the random instruction according to the operating data and the virtual page number lookup table to obtain an expected operating result;

generating a page table according to the operating data and the virtual page number lookup table, and loading the random instruction and the operating data into a memory and a register of the analog microprocessor according to the page table; wherein the page table is used for indicating a mapping relation between a virtual page number and a physical page number;

acquiring the random instruction from the memory and operating the random instruction to obtain an actual operation result;

and determining an instruction-level random verification result for the microprocessor according to the expected operation result and the actual operation result.

Optionally, in a possible implementation manner of the first aspect, the generating a page table according to the operation data and the virtual page number lookup table includes:

and mapping virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information into the same physical page number.

In a second aspect, the present invention provides a microprocessor instruction level random verification apparatus, comprising:

the random instruction generation module is used for generating a random instruction and running data related to the running of the random instruction;

and the random instruction verification module is used for operating the random instruction according to the operating data and the virtual page number lookup table so as to realize instruction level random verification of the microprocessor.

Optionally, in a possible implementation manner of the second aspect, the virtual page number lookup table includes at least one address mapping record, where the address mapping record includes identification bit information and a virtual page number corresponding to a virtual address; and mapping virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information into the same physical page number.

Optionally, in a possible implementation manner of the second aspect, the random instruction generating module is specifically configured to:

Optionally, in a possible implementation manner of the second aspect, the address mapping record further includes mapping identification information;

the random instruction generation module is further configured to:

Optionally, in a possible implementation manner of the second aspect, the random instruction generating module is further configured to:

Optionally, in a possible implementation manner of the second aspect, the random instruction verification module includes: the system comprises a random instruction control module, a microprocessor execution module and a result verification module;

the random instruction generating module is further configured to operate the random instruction according to the operation data and the virtual page number lookup table to obtain an expected operation result;

the random instruction control module is used for generating a page table according to the operating data and the virtual page number lookup table, and loading the random instruction and the operating data into a memory and a register of the analog microprocessor according to the page table; wherein the page table is used for indicating a mapping relation between a virtual page number and a physical page number;

the microprocessor execution module is used for acquiring the random instruction from the memory and operating the random instruction to obtain an actual operation result;

and the result verification module is used for determining an instruction level random verification result of the microprocessor according to the expected operation result and the actual operation result.

Optionally, in a possible implementation manner of the second aspect, the random instruction control module is specifically configured to:

In a third aspect, the present invention provides a microprocessor instruction level random verification device comprising:

a memory and a processor;

the memory to store program instructions;

the processor is used for calling the program instructions stored in the memory to realize the microprocessor instruction level random verification method provided by any one of the implementation modes of the first aspect of the invention.

In a fourth aspect, the present invention provides a storage medium comprising: a readable storage medium and a computer program for implementing the microprocessor instruction level random verification method provided in any embodiment of the first aspect of the present invention.

The invention provides a microprocessor instruction level random verification method and a device, wherein a mapping relation between virtual page numbers and physical page numbers can be constructed through a virtual page number lookup table, and the mapping relation can be one-to-one mapping between the virtual page numbers and the physical page numbers or many-to-one mapping between the virtual page numbers and the physical page numbers. The verification state of address mapping can be increased in the instruction level random verification process of the microprocessor through the virtual page number lookup table, so that the address mapping relation is more fit with the actual address mapping relation, and the sufficiency of instruction level random verification is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flowchart illustrating a method for instruction level random verification in a microprocessor according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for random verification at an instruction level of a microprocessor according to a second embodiment of the present invention;

FIG. 3 is a block diagram of an exemplary embodiment of a microprocessor instruction level random access memory device;

FIG. 4 is a block diagram of an apparatus for random verification at instruction level of a microprocessor according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a flowchart illustrating a method for instruction level random verification in a microprocessor according to an embodiment of the present invention. In the microprocessor instruction level random verification method provided by this embodiment, the execution subject may be a microprocessor instruction level random verification apparatus or a microprocessor instruction level random verification device. As shown in fig. 1, the method for randomly verifying an instruction level of a microprocessor according to this embodiment may include:

and S101, generating a random instruction and operation data related to the operation of the random instruction.

The present embodiment does not limit the type and number of the random instructions. Optionally, the type of random instruction may include, but is not limited to, memory access instructions and arithmetic instructions.

The running data related to the running of the random instruction refers to data required for running the random instruction, and may be different according to different types of the random instruction.

Optionally, if the random instruction is a memory access instruction, the running data related to the running of the random instruction may include at least one of the following: the address of the access instruction, the access address of the access instruction, the data (access number from the memory or storage number to the memory) related to the access instruction, and the virtual address mapped by the access address.

Optionally, if the random instruction is an operation instruction, the operation data related to the operation of the random instruction may include at least one of the following: an address of an operation instruction, an input operand of the operation instruction, an output operand of the operation instruction, a storage address of the input operand, a storage address of the output operand, and a virtual address to which the storage address maps.

And S102, if the random instruction is a first memory access instruction, updating the virtual page number lookup table according to the first memory access address.

The first memory access address of the first memory access instruction is one of a plurality of virtual addresses mapped to the target physical address, and the virtual page number lookup table is used for indicating whether virtual page numbers corresponding to the virtual addresses and physical page numbers are mapped in a one-to-one correspondence manner.

Specifically, in this embodiment, for a memory access instruction, if a memory access address of the memory access instruction is one of multiple virtual addresses mapped to the same physical address (which may be referred to as a target physical address), the memory access instruction may be referred to as a first memory access instruction, and a memory access address of the memory access instruction may be referred to as a first memory access address. The memory access address can be represented by a virtual page number corresponding to the memory access address and an offset within a page (or referred to as an address within a page). If the random instruction is the first access instruction, the virtual page number lookup table can be updated according to the first access address. Whether the virtual page numbers corresponding to the virtual addresses and the physical page numbers are mapped in a one-to-one correspondence mode can be determined through the virtual page number lookup table.

It can be seen that the mapping relationship between the virtual page numbers and the physical page numbers can be constructed through the virtual page number lookup table, and the mapping relationship can be a one-to-one mapping between the virtual page numbers and the physical page numbers, or a many-to-one mapping between the virtual page numbers and the physical page numbers. The verification state of address mapping can be increased in the instruction level random verification process of the microprocessor through the virtual page number lookup table, so that the address mapping relation is more fit with the actual address mapping relation, and the sufficiency of instruction level random verification is improved.

And S103, operating a random instruction according to the operating data and the virtual page number lookup table so as to realize instruction level random verification of the microprocessor.

Specifically, the mapping relationship between the virtual page number and the physical page number can be constructed according to the operation data and the virtual page number lookup table, and the random instruction is operated on the basis of constructing the address mapping relationship, so that the instruction-level random verification of the microprocessor is realized.

It can be seen that, in the microprocessor instruction level random verification method provided in this embodiment, when the memory access address of the memory access instruction is one of the virtual addresses mapped to the same physical address, an address mapping relationship in which the virtual page number and the physical page number are mapped in many-to-one manner can be constructed by updating the virtual page number lookup table, so that the verification state of address mapping is increased, the sufficiency of microprocessor instruction level random verification is improved, and the verification effect is improved.

Optionally, the virtual page number lookup table may include at least one address mapping record. The address mapping record may include identification bit information and a virtual page number corresponding to the virtual address. Virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information are mapped into the same physical page number.

Through the virtual page number lookup table, the mapping relation between the virtual page number and the physical page number can be constructed, the many-to-one mapping relation between the virtual page number and the physical page number is increased, and the sufficiency of instruction-level random verification is improved.

The following is exemplified by table 1. As shown in table 1, each row represents an address mapping record. Each address mapping record comprises identification bit information and a virtual page number corresponding to the virtual address. In table 1, there are 2 values of the flag bit information, which are 2 and 3, respectively. Two address mapping records with identification bit information of 2 are recorded. The virtual page numbers 00000 and 00001 may map to the same physical page number. Three address mapping records with identification bit information of 3 are recorded. The virtual page numbers 00002, 00003, and 00004 may map to the same physical page number.

TABLE 1

Identification bit information	Virtual page number corresponding to virtual address	Mapping identification information	Line number
				2	00000 (virtual address A)	1	1
2	00001 (virtual address B)		2
				3	00002 (virtual address C)		3
3	00003 (virtual address D)	1	4
				3	00004 (virtual address E)		5

Optionally, the address mapping record may further include mapping identification information.

A plurality of virtual page numbers with the same identification bit information may be mapped to the virtual page number corresponding to the mapping identification information being the preset first numerical value. Or, a plurality of virtual addresses with the same identification bit information may be mapped to the virtual address corresponding to the mapping identification information being the preset first numerical value.

The following is exemplified by table 1. Assume that the first value is preset to be 1. The virtual addresses in the address mapping records shown in the 1 st to 5 th rows are the virtual address a to the virtual address E, respectively.

Two address mapping records with identification bit information of 2 are recorded. The mapping identification information corresponding to the virtual page number 00000 (virtual address a) is 1. Then both the virtual page number 00000 and virtual page number 00001 may be mapped to virtual page number 00000 in executing the random instruction to obtain the desired execution result. Alternatively, both virtual address a and virtual address B may be mapped to virtual address a. That is, the access operation to virtual address A, B is an access operation to virtual address A in executing the random instruction to obtain the desired execution result.

Three address mapping records with identification bit information of 3 are recorded. The mapping identification information corresponding to the virtual page number 00003 (virtual address D) is 1. Then the dummy page number 00002, dummy page number 00003, and dummy page number 00004 may all be mapped to dummy page number 00003 in the execution of the random instruction to obtain the desired result of the operation. Alternatively, virtual address C, virtual address D, and virtual address E may all be mapped to virtual address D. That is, during execution of the random instruction to achieve the desired execution result, the access operations to virtual addresses C, D and E are both access operations to virtual address D.

It should be noted that, in this embodiment, specific values of the identification bit information and the preset first value are not limited, and are set as needed.

It should be noted that, in this embodiment, the storage form of the virtual page number lookup table is not limited. For example, it may be in the form of a table, or in the form of a file.

Optionally, in S102, updating the virtual page number lookup table according to the first access address may include:

and judging whether the virtual page number corresponding to the first memory access address exists in the virtual page number lookup table or not.

If the virtual page number does not exist in the virtual page number lookup table, adding a first address mapping record in the virtual page number lookup table, wherein the first address mapping record comprises first identification bit information and a virtual page number corresponding to the first access address, and the first identification bit information is identification bit information which exists in the virtual page number lookup table and is less than a preset number, or identification bit information which does not exist in the virtual page number lookup table.

If the virtual page number exists, adding a second address mapping record in the virtual page number lookup table, wherein the second address mapping record comprises second identification bit information and a virtual page number corresponding to the first memory access address, and the second identification bit information is identification bit information which exists in the virtual page number lookup table, is smaller than a preset number and is different from the target identification bit information, or is identification bit information which does not exist in the virtual page number lookup table. And the target identification bit information is identification bit information corresponding to the first memory access address in the virtual page number lookup table.

By updating the virtual page number lookup table, the mapping relation between the virtual page number and the physical page number can be constructed, the many-to-one mapping relation between the virtual page number and the physical page number is increased, and the sufficiency of instruction-level random verification is improved.

The following is a description by specific examples. Wherein, table 1 is a virtual page number lookup table before updating, and table 2 is a virtual page number lookup table after updating. Assume that the predetermined number is 3. That is, the number of virtual addresses mapped to the same physical address is at most 3.

TABLE 2

Identification bit information	Virtual page number corresponding to virtual address	Mapping identification information	Line number
				2	00000 (virtual address A)	1	1
2	00001 (virtual address B)		2
				3	00002 (virtual address C)		3
3	00003 (virtual address D)	1	4
				3	00004 (virtual address E)		5
2	00005 (virtual address F)		6
				4	00005 (virtual address F)	1	7
2	00004 (virtual address G)		8
				4	00004 (virtual address G)		9

In one example, the first memory access address is F, and the virtual page number corresponding to the first memory access address is 00005. Since the virtual page number 00005 is not in the virtual page number lookup table shown in table 1, an address mapping record, referred to as a first address mapping record, is added to table 1. In one implementation, the first identification bit information in the first address mapping record may be identification bit information that exists in a virtual page number lookup table and is less than a preset number (3). Since the number of identification bit information 2 is 2 and the number of identification bit information 3 is 3 in table 1. At this time, the first identification information may be 2, and the first address mapping record may be referred to as row 6 in table 2. The virtual page numbers 00000, 00001, and 00005 may map to the same physical page number. Accordingly, virtual addresses A, B and F may map to the same physical address. In another implementation, the first identification bit information may be identification bit information that is not present in the virtual page number lookup table, for example, 4. The first address mapping record can be seen in line 7 of table 2. At this time, the virtual page number 00005 maps the virtual page number with the identification bit information of 4 in the subsequent address mapping record to the same physical page number, and the virtual address F maps the virtual address corresponding to the other identification bit information of 4 to the same physical address.

In another example, the first memory access address is G, and the virtual page number corresponding to the first memory access address is 00004. Since the virtual page number 00004 is in the virtual page number lookup table shown in table 1, an address map record, referred to as a second address map record, is added to table 1. In one implementation, the second identification bit information in the second address mapping record may be identification bit information that exists in a virtual page number lookup table, is less than the preset number (3), and is different from the target identification bit information. At this time, the identification bit information present in table 1 is 2 and 3. Wherein, the identification bit information of which the number is less than the preset number (3) is 2. The target identification information is identification bit information corresponding to the first memory access address in the virtual page number lookup table, and is specifically 3. Therefore, the second identification bit information may be 2. The second address map record may be seen in Table 2, line 8. At this time, the dummy page numbers 00000, 00001, and 00004 may be mapped to the same physical page number. Accordingly, virtual addresses A, B and G may map to the same physical address. In another implementation, the second identification bit information may be identification bit information that is not present in the virtual page number lookup table, for example, 4. The second address map record may be seen in Table 2, line 9. At this time, the virtual page number 00004 maps the virtual page number with the identification bit information of 4 in the subsequent address mapping record to the same physical page number, and the virtual address G maps the virtual address corresponding to the other identification bit information of 4 to the same physical address.

Optionally, the address mapping record further includes mapping identification information. In S102, updating the virtual page number lookup table according to the first access address, which may further include:

and judging whether the mapping identification information included in at least one address mapping record which is the same as the first identification bit information or the second identification bit information in the virtual page number lookup table is equal to a preset first numerical value or not.

If not, determining a target address mapping record in at least one address mapping record, and setting mapping identification information in the target address mapping record as a preset first numerical value.

By determining one address mapping record (called as a target address mapping record) in at least one address mapping record with the same identification bit information and setting the mapping identification information in the target address mapping record to be a preset first value, the virtual address with the same identification bit information can be mapped to one virtual address in the process of executing a random instruction to obtain an expected operation result, so that the random verification of a microprocessor instruction level is facilitated.

The following is described by specific examples in conjunction with table 2.

For the first address mapping record shown in row 7 of table 2, the first identification bit information is 4. Since there is no other address mapping record with the identification bit information of 4 in table 2, the mapping identification information in the first address mapping record shown in row 7 may be set to the preset first value. In this way, in the address mapping records added subsequently in table 2, all the virtual addresses corresponding to the identification bit information 4 can be mapped to the virtual address F.

Optionally, before determining the target address mapping record in the at least one address mapping record, determining whether the number of the at least one address mapping record is greater than 1.

If the address mapping record is larger than 1, determining a target address mapping record in at least one address mapping record.

The first address mapping record shown in row 7 of table 2 will be described as an example. Since there is no other address mapping record with the identification bit information of 4 in table 2, the mapping identification information in the first address mapping record shown in row 7 may not be set to the preset first value. When other address mapping records with identification bit information of 4 are subsequently added in table 2, the target address mapping record can be determined in the plurality of address mapping records with identification bit information of 4.

Optionally, after S101 and before S103, the method for randomly verifying an instruction level of a microprocessor according to this embodiment may further include:

and if the random instruction is a second memory access instruction, adding a third address mapping record in the virtual page number lookup table, wherein the third address mapping record comprises third identification bit information and a virtual page number corresponding to the second memory access address, and the third identification bit information is a preset second numerical value. And mapping the second memory access address of the second memory access instruction and the target physical address in a one-to-one correspondence manner.

And executing the random instruction according to the operation data and the virtual page number lookup table so as to realize instruction-level random verification of the microprocessor.

Specifically, in this embodiment, for a memory access instruction, if the memory access address of the memory access instruction is mapped in a one-to-one correspondence with a physical address (which may be referred to as a target physical address), the memory access instruction may be referred to as a second memory access instruction, and the memory access address of the memory access instruction may be referred to as a second memory access address. If the random instruction is a second access instruction, the virtual page number lookup table can be updated according to the first access address. Specifically, a third address mapping record is added to the virtual page number lookup table. Whether the virtual page numbers corresponding to the virtual addresses and the physical page numbers are mapped in a one-to-one correspondence mode can be determined through the virtual page number lookup table. And a mapping relation between the virtual page number and the physical page number is constructed according to the operation data and the virtual page number lookup table, and the second access instruction is operated on the basis of constructing the address mapping relation, so that the completeness of the instruction level random verification of the microprocessor is improved.

It should be noted that, in this embodiment, specific values of the preset second value are not limited, and are set as needed.

The following is a description by specific examples. Wherein, table 1 is a lookup table of virtual page numbers before updating, and table 3 is a lookup table of virtual page numbers after updating. Assume that the second value is 0.

In one example, the second memory access address is a virtual address H, and the virtual page number corresponding to the second memory access address is 00006. An address mapping record, called the third address mapping record, is added to table 1. And the third identification bit information in the third address mapping record is a preset second numerical value (0). The third address mapping record can be seen in line 6 of table 3.

In another example, the second memory access address is a virtual address I, and the virtual page number corresponding to the second memory access address is 00001. An address mapping record, called the third address mapping record, is added to table 1. And the third identification bit information in the third address mapping record is a preset second numerical value (0). The third address mapping record can be seen in line 7 of table 3.

In yet another example, the second memory access address is a virtual address J, and the virtual page number corresponding to the second memory access address is 00001. An address mapping record, called the third address mapping record, is added to table 1. And the third identification bit information in the third address mapping record is a preset second numerical value (0). The third address mapping record can be seen in line 8 of table 3.

Note that the virtual page numbers corresponding to the virtual addresses B, I and J are 00001, and the page offsets corresponding to the virtual addresses B, I and J are different.

TABLE 3

Identification bit information	Virtual page number corresponding to virtual address	Mapping identification information	Line number
				2	00000 (virtual address A)	1	1
2	00001 (virtual address B)		2
				3	00002 (virtual address C)		3
3	00003 (virtual address D)	1	4
				3	00004 (virtual address E)		5
0	00006 (virtual address H)		6
				0	00001 (virtual address I)		7
0	00001 (virtual address J)		8

Optionally, before adding the third address mapping record in the virtual page number lookup table, the method may further include:

and judging whether the virtual page number corresponding to the second memory access address exists in the virtual page number lookup table or not and whether the identification bit information corresponding to the virtual page number corresponding to the second memory access address is a preset second numerical value or not.

And if the virtual page number corresponding to the second memory access address does not exist in the virtual page number lookup table, adding a third address mapping record in the virtual page number lookup table.

And if the virtual page number corresponding to the second memory access address exists in the virtual page number lookup table and the identification bit information corresponding to the virtual page number corresponding to the second memory access address is not a preset second numerical value, adding a third address mapping record in the virtual page number lookup table.

And if the virtual page number corresponding to the second memory access address exists in the virtual page number lookup table and the identification bit information corresponding to the virtual page number corresponding to the second memory access address is a preset second numerical value, not adding a third address mapping record in the virtual page number lookup table.

The virtual page number lookup table is simplified by avoiding duplicate recording of the third address mapping record in the virtual page number lookup table.

Optionally, before S103, the microprocessor instruction level random verification method provided in this embodiment may further include:

and judging whether the virtual page number corresponding to the address of the random instruction exists in the virtual page number lookup table or not.

And if the virtual page number does not exist, adding a fourth address mapping record in the virtual page number lookup table, wherein the fourth address mapping record comprises fourth identification bit information and a virtual page number corresponding to the address of the random instruction, and the fourth identification bit information is a preset third numerical value.

Specifically, the virtual page number lookup table can be updated according to the address of the random instruction, so that the completeness of the instruction level random verification of the microprocessor is improved.

The following is a description by specific examples. Wherein, table 1 is a lookup table of virtual page numbers before updating, and table 4 is a lookup table of virtual page numbers after updating. Assume that the third value is preset to be 1.

TABLE 4

Identification bit information	Virtual page number corresponding to virtual address	Mapping identification information	Line number
				2	00000 (virtual address A)	1	1
2	00001 (virtual address B)		2
				3	00002 (virtual address C)		3
3	00003 (virtual address D)	1	4
				3	00004 (virtual address E)		5
1	00007 (virtual address K)		6

In one example, the address of the random instruction may be virtual address K, and the address of the random instruction corresponds to a virtual page number of 00007. An address mapping record is added to table 1, called the fourth address mapping record. And the fourth identification bit information in the fourth address mapping record is a preset third numerical value (1). The third address mapping record can be seen in line 6 of table 4.

It should be noted that, in this embodiment, a specific value of the preset third value is not limited, and is set as needed.

Optionally, in S103, executing a random instruction according to the operation data and the virtual page number lookup table to implement instruction-level random verification of the microprocessor, where the executing step may include:

and operating the random instruction according to the operating data and the virtual page number lookup table to obtain an expected operating result.

And generating a page table according to the operation data and the virtual page number lookup table, and loading the random instruction and the operation data into a memory and a register of the analog microprocessor according to the page table. The page table is used for indicating a mapping relation between a virtual page number and a physical page number.

And acquiring the random instruction from the memory and operating the random instruction to obtain an actual operation result.

It should be noted that the instruction level random verification process in the present embodiment may refer to an existing microprocessor instruction level random verification process. Since the virtual page number lookup table is set and updated, the virtual page number lookup table needs to be considered when constructing the mapping relationship between the virtual page number and the physical page number and the mapping relationship between the virtual address and the physical address. Optionally, for the first access instruction, in the process of obtaining the expected operation result, according to the identification bit information and the mapping identification information in the virtual page number lookup table, a plurality of virtual addresses with the same identification bit information may be mapped to virtual addresses whose mapping identification information is corresponding to the preset first numerical value. In the process of generating the page table and obtaining the actual operation result, the virtual page numbers corresponding to the virtual addresses with the same identification bit information can be mapped into the same physical page number according to the identification bit information in the virtual page number lookup table, and the virtual addresses with the same identification bit information can be mapped into the same physical address.

The embodiment provides a microprocessor instruction level random verification method, which comprises the following steps: generating a random instruction and operation data related to the operation of the random instruction, if the random instruction is a first access instruction, and a first access address of the first access instruction is one of a plurality of virtual addresses mapped to a target physical address, updating a virtual page number lookup table according to the first access address, and operating the random instruction according to the operation data and the virtual page number lookup table to realize instruction level random verification of the microprocessor. In the microprocessor instruction level random verification method provided by this embodiment, when the memory address of the memory access instruction is one of the virtual addresses mapped to the same physical address, an address mapping relationship in which the virtual page number and the physical page number are mapped in a many-to-one manner can be constructed by using the virtual page number lookup table, so that the verification state of address mapping is increased, the sufficiency of microprocessor instruction level random verification is improved, and the verification effect is improved.

FIG. 2 is a flowchart illustrating a method for random verification at an instruction level of a microprocessor according to a second embodiment of the present invention. The embodiment of the present invention provides a specific implementation manner of the instruction level random verification method of the microprocessor based on the embodiment shown in fig. 1. As shown in fig. 2, the method for randomly verifying the instruction level of the microprocessor according to the present embodiment may include:

s201, initializing preset parameters.

Specifically, the preset parameters may include: the method comprises the steps of presetting the number, presetting a first numerical value, presetting a second numerical value and presetting a third numerical value.

S202, initializing a virtual page number lookup table.

And S203, generating the random instruction and operation data related to the operation of the random instruction.

And S204, updating a virtual page number lookup table according to the random instruction and the operation data.

Wherein updating the virtual page number lookup table may include:

and if the random instruction is a first access instruction, updating the virtual page number lookup table according to a first access address of the first access instruction. And/or the presence of a gas in the gas,

and if the random instruction is a second access instruction, updating the virtual page number lookup table according to a second access address of the second access instruction. And/or the presence of a gas in the gas,

and updating the virtual page number lookup table according to the address of the access instruction.

Optionally, if the random instruction is a first access instruction, updating the virtual page number lookup table according to a first access address of the first access instruction, where the updating may include:

If the virtual page number does not exist, adding a first address mapping record in the virtual page number lookup table, wherein the first address mapping record comprises first identification bit information and a virtual page number corresponding to the first access address, and the first identification bit information is identification bit information which exists in the virtual page number lookup table and is less than a preset number, or identification bit information which does not exist in the virtual page number lookup table.

And if the virtual page number exists, adding a second address mapping record in the virtual page number lookup table, wherein the second address mapping record comprises second identification bit information and a virtual page number corresponding to the first memory access address, and the second identification bit information is identification bit information which exists in the virtual page number lookup table, is less than a preset number and is different from the target identification bit information, or is identification bit information which does not exist in the virtual page number lookup table. And the target identification bit information is identification bit information corresponding to the first memory access address in the virtual page number lookup table.

Optionally, if the random instruction is a second access instruction, updating the virtual page number lookup table according to a second access address of the second access instruction, where the updating may include:

and if the random instruction is a second memory access instruction, adding a third address mapping record in the virtual page number lookup table, wherein the third address mapping record comprises third identification bit information and a virtual page number corresponding to the second memory access address, and the third identification bit information is a preset second numerical value.

Optionally, updating the virtual page number lookup table according to the address of the access instruction may include:

For a specific principle, reference may be made to the description in the embodiment shown in fig. 1, which is similar to the principle and is not described herein again.

It should be noted that, in this embodiment, the execution sequence of each step of the above-mentioned updating the virtual page number lookup table is not limited.

And S205, operating the random instruction according to the operating data and the virtual page number lookup table to obtain an expected operating result.

Specifically, for the first memory access instruction, the first memory access address of the first memory access instruction may be remapped to a virtual address having the same identification bit information and mapping flag information to a preset first numerical value. And executing the access operation indicated by the first access instruction according to the virtual address, wherein the access operation, such as memory number or access number, is required to be performed in the mapped virtual address.

S206, generating a page table according to the operation data and the virtual page number lookup table, and loading the random instruction and the operation data into a memory and a register of the analog microprocessor according to the page table.

The page table is used for indicating a mapping relation between a virtual page number and a physical page number.

Specifically, according to the operating data and the virtual page number lookup table, a physical page number may be assigned to the virtual page number, and the virtual page numbers with the same flag bit information in the virtual page number lookup table are mapped to the same physical page number. And establishing a page table according to the mapping relation between the virtual page number and the physical page number. And loading the random instruction and the operation data into a memory and a register of the analog microprocessor according to the allocated physical page number.

And S207, acquiring the random instruction from the memory and operating the random instruction to obtain an actual operation result.

Specifically, the verified microprocessor fetches the random instruction from the memory and executes the random instruction. And if the address of the random instruction or the virtual page number corresponding to the access address of the random instruction generates a page table miss exception, feeding back an exception signal and exception information. And according to the exception signal and the exception information, finding a physical page number corresponding to the virtual page number with the exception from the page table, and writing the physical page number into a page table entry of the verified microprocessor. Thus, the dummy page numbers in the page table that correspond to the same physical page number are all mapped to the same page in memory. When the page table of the verified microprocessor is not subjected to exceptional resolution, the random instruction fetching or the data fetching execution is continued.

And S208, determining an instruction level random verification result of the microprocessor according to the expected operation result and the actual operation result.

Specifically, if the expected operation result is consistent with the actual operation result, the instruction level random verification of the microprocessor is determined to be passed.

The embodiment provides a microprocessor instruction level random verification method, which increases the verification state of address mapping, improves the sufficiency of microprocessor instruction level random verification, and improves the verification effect.

FIG. 3 is a block diagram of an apparatus for random verification at instruction level of a microprocessor according to an embodiment of the present invention. The microprocessor instruction level random verification apparatus provided in this embodiment is used for executing the microprocessor instruction level random verification method provided in the embodiments shown in fig. 1-2. As shown in fig. 3, the microprocessor instruction level random verification apparatus provided in this embodiment may include:

and the random instruction generating module 11 is configured to generate a random instruction and operation data related to the operation of the random instruction.

And if the random instruction is a first access instruction, updating the virtual page number lookup table according to the first access address. The first memory access address of the first memory access instruction is one of a plurality of virtual addresses mapped to the target physical address, and the virtual page number lookup table is used for indicating whether virtual page numbers corresponding to the virtual addresses and physical page numbers are mapped in a one-to-one correspondence manner.

And the random instruction verification module 12 is configured to execute a random instruction according to the operation data and the virtual page number lookup table, so as to implement instruction-level random verification of the microprocessor.

Optionally, the virtual page number lookup table includes at least one address mapping record, and the address mapping record includes identification bit information and a virtual page number corresponding to the virtual address. Virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information are mapped into the same physical page number.

Optionally, the random instruction generating module 11 is specifically configured to:

Optionally, the address mapping record further includes mapping identification information.

The random instruction generating module 11 is further configured to:

Optionally, the random instruction generating module 11 is further configured to:

when the virtual page number corresponding to the second memory access address does not exist in the virtual page number lookup table, adding a third address mapping record in the virtual page number lookup table; alternatively, the first and second electrodes may be,

and when the virtual page number corresponding to the second memory access address exists in the virtual page number lookup table and the identification bit information corresponding to the virtual page number corresponding to the second memory access address is not a preset second numerical value, adding a third address mapping record in the virtual page number lookup table.

Optionally, the random instruction verification module 12 includes: a random instruction control module 121, a microprocessor execution module 122, and a result verification module 123.

The random instruction generating module 11 is further configured to execute a random instruction according to the operation data and the virtual page number lookup table, so as to obtain an expected operation result.

And the random instruction control module 121 is configured to generate a page table according to the operation data and the virtual page number lookup table, and load the random instruction and the operation data into a memory and a register of the analog microprocessor according to the page table. The page table is used for indicating a mapping relation between a virtual page number and a physical page number.

The microprocessor executing module 122 is configured to fetch the random instruction from the memory and execute the random instruction to obtain an actual operation result.

And the result verification module 123 is used for determining an instruction level random verification result for the microprocessor according to the expected operation result and the actual operation result.

Optionally, the random instruction control module 121 is specifically configured to:

The microprocessor instruction level random verification apparatus provided in this embodiment is used to execute the microprocessor instruction level random verification method provided in the embodiments shown in fig. 1-2, and the technical principle and technical effect are similar, which are not described herein again.

FIG. 4 is a block diagram of an apparatus for random verification at instruction level of a microprocessor according to an embodiment of the present invention. As shown in fig. 4, the microprocessor instruction level random verification device includes a processor 21 and a memory 22, where the memory 22 is configured to store instructions, and the processor 21 is configured to execute the instructions stored in the memory 22, so that the microprocessor instruction level random verification device executes the microprocessor instruction level random verification method provided in the embodiments shown in fig. 1-2, and specific implementation manners and technical effects are similar, and are not described again here.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A microprocessor instruction level random verification method, comprising:

2. The method of claim 1, wherein the virtual page number lookup table comprises at least one address mapping record, the address mapping record comprising identification bit information and a virtual page number corresponding to a virtual address; and mapping virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information into the same physical page number.

3. The method of claim 2, wherein updating the virtual page number lookup table according to the first memory access address comprises:

4. The method of claim 3, wherein the address mapping record further comprises mapping identification information;

5. The method of any of claims 2-4, wherein prior to executing the random instruction based on the execution data and the virtual page number lookup table, further comprising:

6. The method of claim 5, wherein adding a third address mapping record to the virtual page number lookup table comprises:

7. The method according to any one of claims 1-4, further comprising:

8. The method of any of claims 2-4, wherein said executing the random instruction according to the execution data and the virtual page number lookup table to implement instruction level random validation of a microprocessor comprises:

9. The method of claim 8, wherein generating a page table from the operational data and the virtual page number lookup table comprises:

10. An instruction level random verification apparatus for a microprocessor, comprising:

11. The apparatus of claim 10, wherein the virtual page number lookup table comprises at least one address mapping record, the address mapping record comprising identification bit information and a virtual page number corresponding to a virtual address; and mapping virtual page numbers corresponding to a plurality of virtual addresses with the same identification bit information into the same physical page number.

12. The apparatus of claim 11, wherein the random instruction generation module is specifically configured to:

13. The apparatus of claim 12, wherein the address mapping record further comprises mapping identification information;

the random instruction generation module is further configured to:

14. The apparatus according to any of claims 11-13, wherein the random instruction generation module is further configured to:

15. The apparatus of claim 14, wherein the random instruction generation module is specifically configured to:

16. The apparatus of any of claims 10-13, wherein the random instruction generation module is further configured to:

17. The apparatus of any of claims 11-13, wherein the random instruction validation module comprises: the system comprises a random instruction control module, a microprocessor execution module and a result verification module;

18. The apparatus of claim 17, wherein the random command control module is specifically configured to:

19. A microprocessor instruction level random authentication device, comprising: a memory and a processor;

the memory to store program instructions;

the processor for invoking the program instructions stored in the memory to implement the microprocessor instruction level random authentication method of any one of claims 1-9.

20. A storage medium, comprising: readable storage medium and computer program for implementing a microprocessor instruction level random authentication method according to any one of claims 1-9.