CN110890414B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN110890414B CN110890414B CN201811042994.8A CN201811042994A CN110890414B CN 110890414 B CN110890414 B CN 110890414B CN 201811042994 A CN201811042994 A CN 201811042994A CN 110890414 B CN110890414 B CN 110890414B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 50
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 115
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 68
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device also includes an upper recess and a lower recess disposed within the AlGaN layer, wherein the upper recess is adjacent to the lower recess and the upper recess has a width greater than that of the lower recess. The semiconductor device further includes a second gallium nitride layer disposed within the upper recess and the lower recess, and a gate structure disposed on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having recesses with different depths and methods of fabricating the same.
Background
Semiconductor devices are used in a variety of electronic applications such as high power devices, personal computers, cell phones, digital cameras, and other electronic devices. These semiconductor devices are generally manufactured by depositing an insulating layer or a dielectric layer, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers by using a photolithography (photolithography) process. Thus, circuit devices and components are formed on a semiconductor substrate (substrate).
Among these devices, high-electron mobility transistors (HEMTs) are widely used in high-power applications because they have advantages such as high output power and high breakdown voltage.
Although existing semiconductor devices and methods for fabricating them are adequate for their intended purposes, they have not yet fully met the requirements in every aspect, and thus semiconductor integrated circuits and techniques are still in need of overcoming the problems.
Disclosure of Invention
Embodiments of a semiconductor device and methods of fabricating the same, in particular an enhancement-mode (E-mode) High Electron Mobility Transistor (HEMT), are provided. In some embodiments of the present invention, upper and lower recesses are provided in the aluminum gallium nitride layer, and the gallium nitride layer is filled in the upper and lower recesses. Specifically, the upper recess is adjacent to the lower recess, and the width of the upper recess is greater than the width of the lower recess, so that the bottom surface of the GaN layer is stepped. In other words, the gallium nitride layer has at least two different thicknesses, so that the threshold voltage of the semiconductor device can be easily and precisely controlled without affecting the breakdown voltage of the semiconductor device.
According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a first gallium nitride layer arranged on a semiconductor substrate, and an aluminum gallium nitride layer arranged on the first gallium nitride layer. The semiconductor device also includes an upper recess and a lower recess disposed within the AlGaN layer, wherein the upper recess is adjacent to the lower recess and the upper recess has a width greater than that of the lower recess. The semiconductor device further includes a second gallium nitride layer disposed within the upper recess and the lower recess, and a gate structure disposed on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.
According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a first gallium nitride layer arranged on a semiconductor substrate, and an aluminum gallium nitride layer arranged on the first gallium nitride layer. The semiconductor device also includes a first recess and a second recess disposed within the AlGaN layer, wherein the first recess is laterally adjacent to the second recess, and the second recess has a depth greater than the first recess. The semiconductor device further comprises a second gallium nitride layer arranged in the first recess and the second recess, and a gate structure arranged on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.
According to some embodiments, a method of manufacturing a semiconductor device is provided. A method of manufacturing a semiconductor device includes forming a first gallium nitride layer on a semiconductor substrate, and forming an aluminum gallium nitride layer on the first gallium nitride layer. The method also includes forming an upper recess in the AlGaN layer and forming a lower recess in the AlGaN layer through the upper recess, wherein the upper recess is adjacent to the lower recess and has a width greater than that of the lower recess. The method further includes forming a second gallium nitride layer within the upper and lower recesses, and forming a gate structure on the second gallium nitride layer. In addition, the method of manufacturing a semiconductor device includes forming a source electrode and a drain electrode on the aluminum gallium nitride layer.
The following embodiments and the accompanying reference drawings will provide detailed descriptions.
Drawings
The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.
Fig. 1A-1H are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor device of fig. 1H, in accordance with some embodiments; and
fig. 2 is a schematic cross-sectional view illustrating a semiconductor device according to some other embodiments.
Reference numerals:
100. 200-a semiconductor device;
101-a semiconductor substrate;
103. 115-gallium nitride layer;
105. 205-aluminum gallium nitride layer;
107. 111-patterned mask;
109-upper concave;
110-etching process;
113-undercut;
117-source electrode;
119-a drain electrode;
121-a gate structure;
123. 223 to a first recess;
125. 225 to a second recess;
130-two-dimensional electron gas channel;
D 1 、D 2 -depth;
T 1 -a first thickness;
T 2 -a second thickness;
T 3 -a third thickness;
W 1 、W 2 width.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different components of the provided semiconductor devices. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.
Fig. 1A-1H are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor device 100 of fig. 1H, according to some embodiments. As shown in fig. 1A, a gallium nitride layer 103 (also referred to as a first gallium nitride layer) is formed on a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), silicon dioxide (SiO) 2 ) Sapphire (sapphire), or a combination thereof.
Further, the gallium nitride layer 103 is undoped (undoped). In some embodiments, the gallium nitride layer 103 may be formed using a metal-organic chemical vapor deposition (MOCVD) process, a Molecular Beam Epitaxy (MBE) process, or a combination thereof. In some embodiments, the gallium nitride layer 103 may be a multi-layer structure.
According to some embodiments, as shown in fig. 1B, an aluminum gallium nitride layer 105 is formed on the gallium nitride layer 103, and a patterned mask 107 is formed on the aluminum gallium nitride layer 105. Some processes for forming the aluminum gallium nitride layer 105 may be similar or identical to those used for forming the gallium nitride layer 103, and thus, a description thereof will not be repeated. In some embodiments, the aluminum gallium nitride layer 105 has a thickness in the range of about 20nm to about 35nm, and particularly about 25nm. Further, in one embodiment, the aluminum gallium nitride layer 105 is undoped.
In some embodiments, a masking layer (not shown) is formed on the AlGaN layer 105. Then, the mask layer is patterned by performing a patterning process to form a patterned mask 107. The patterning process includes a photolithography process and an etching process. Photolithography processes include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and baking (e.g., hard baking). The etching process includes dry etching or wet etching. As a result, the patterned mask 107 exposes a portion of the aluminum gallium nitride layer 105.
Then, referring to fig. 1B and 1C, an etching process 110 is performed to form an upper recess 109 in the aluminum gallium nitride layer 105 using the patterned mask 107 as a mask. Notably, the upper recess 109 does not pass through the aluminum gallium nitride layer 105. In other words, the upper recess 109 does not expose the gallium nitride layer 103. The patterned mask 107 is removed after the upper recess 109 is formed.
In some embodiments, the aluminum gallium nitride layer 105 has a thickness of about 25nm before the etching process 110 is performed, and the depth of the upper recess 109 is in a range of about 5nm to about 10nm after the etching process 110. That is, the thickness of the aluminum gallium nitride layer 105 under the upper recess 109 is in the range of about 15nm to about 20 nm.
According to some embodiments, a patterned mask 111 is formed on the aluminum gallium nitride layer 105, as shown in FIG. 1D. Specifically, the patterned mask 111 extends into the upper recess 109. The patterned mask 111 fills a portion of the upper recess 109, and another portion of the upper recess 109 remains empty. In some embodiments, one sidewall of the upper recess 109 is aligned with one sidewall of the patterned mask 111 above it. Some materials and processes for forming the patterned mask 111 may be similar or identical to those used for forming the patterned mask 107, and thus, the description thereof will not be repeated.
Next, referring to fig. 1D and 1E, an etching process 102 is performed to form a lower recess 113 in the aluminum gallium nitride layer 105 through the upper recess 109 using the patterned mask 111 as a mask. The upper recess 109 is adjacent to the lower recess 113. In some embodiments, the upper recess 109 has a sidewall that is aligned with a sidewall of the lower recess 113. Specifically, the lower recess 113 has a width W 1 The upper recess 109 has a width W 2 And a width W 2 Is greater than width W 1 . In some embodiments, the width W 1 And width W 2 Can be adjusted according to the process requirements.
Note that the recess 113 does not penetrate the algan layer 105. In other words, the lower recess 113 does not expose the gallium nitride layer 103. After the formation of the lower recess 113, the patterned mask 111 is removed, and a portion of the aluminum gallium nitride layer 105 underlying the upper recess 109 and the lower recess 113 has a stepped top surface.
In other words, the combination of the upper recess 109 and the lower recess 113 may be divided into a first recess 123 and a second recess 125 (as shown in FIG. 1F). The first recess 123 is laterally adjacent to the second recess 125, and the depth of the second recess 125 is greater than the depth of the first recess 123 (see fig. 1H, depth D of the second recess 125 2 Greater than the depth D of the first recess 123 1 )。
Next, as shown in fig. 1G, a gallium nitride layer 115 (also referred to as a second gallium nitride layer) is filled in the upper recess 109 and the lower recess 113, that is, the gallium nitride layer 115 is filled in the first recess 123 and the second recess 125. In some embodiments, the gallium nitride layer 115 protrudes from the aluminum gallium nitride layer 105. In other words, the top surface of the gallium nitride layer 115 is higher than the top surface of the aluminum gallium nitride layer 105.
In some embodiments, the gallium nitride layer 115 may be formed by a Chemical Vapor Deposition (CVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Molecular Beam Epitaxy (MBE) process, or a combination thereof. In some embodiments, the gallium nitride layer 115 is P-type.
Further, the bottom surface of the gallium nitride layer 115 is stepped, and the gallium nitride layer 103 is separated from the gallium nitride layer 115 by a portion of the aluminum gallium nitride layer 105. In other words, the bottommost surface of the gallium nitride layer 115 is higher than the topmost surface of the gallium nitride layer 103.
Continuing the foregoing, as shown in fig. 1H, a source electrode 117 and a drain electrode 119 are formed on the aluminum gallium nitride layer 105, and a gate structure 121 is formed on the gallium nitride layer 115. In some embodiments, source electrode 117, drain electrode 119, and gate structure 121 are made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or other suitable materials. In some embodiments, the source electrode 117, the drain electrode 119, and the gate structure 121 are formed by a deposition process and a patterning process. The deposition process may be a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a combination thereof.
In one embodiment, after forming the source electrode 117, the drain electrode 119, and the gate structure 121, the semiconductor device 100 is completed and a two-dimensional electron gas (2 DEG) channel 130 is generated. A two-dimensional electron gas channel 130 may be created within the gallium nitride layer 103 and may extend along the interface between the gallium nitride layer 103 and the aluminum gallium nitride layer 105.
Specifically, the source electrode 117 is closer to the recess 113 than the drain electrode 119. That is, the source electrode 117 is closer to the second recess 125 than the drain electrode 119. In some embodiments, the gate structure 121 covers an interface between the first recess 123 and the second recess 125. In addition, the bottom surface of the gate structure 121 is higher than the bottom surfaces of the source electrode 117 and the drain electrode 119.
It is noted that the AlGaN layer 105 has a first thickness T under the first recess 123 1 The AlGaN layer 105 has a second thickness T under the second recess 125 2 And the aluminum gallium nitride layer 105 has a third thickness T under the source electrode 117 3 . Wherein the third thickness T 3 Greater than the first thickness T 1 And a first thickness T 1 Greater than the second thickness T 2 . In some embodiments, the first thickness T 1 And a third thickness T 3 Is in the range of about 0.6 to about 0.8, and a second thickness T 2 And a third thickness T 3 Is in the range of about 0.2 to about 0.4.
Further, in some embodiments, the third thickness T 3 About 25nm, a first thickness T 1 In the range of about 15nm to about 20nm, and a second thickness T 2 In the range of about 5nm to about 10 nm. Overall, the portion of the aluminum gallium nitride layer 105 underlying the gallium nitride layer 115 has two different thicknesses. In other embodiments, the gallium nitride layer 115 may have more than two different thicknesses.
Furthermore, the threshold voltage and the second thickness T of the semiconductor device 100 2 Are in positive correlation with each other. Specifically, when the second thickness T is larger than the first thickness T 2 As the threshold voltage of the semiconductor device 100 increases, the threshold voltage increases. Therefore, the threshold voltage of the semiconductor device 100 can be controlled easily and precisely without affecting the breakdown voltage of the semiconductor device 100. Furthermore, the threshold voltage of the semiconductor device 100 may be controlled without adding an additional doping process.
Fig. 2 is a schematic cross-sectional diagram illustrating a semiconductor device 200, according to some other embodiments. The difference between the semiconductor device 200 and the semiconductor device 100 is the location of the recess.
The semiconductor device 200 includes an aluminum gallium nitride layer 205. Some of the materials and processes used to form the aluminum gallium nitride layer 205 may be similar or identical to the processes used to form the aluminum gallium nitride layer 105, and will not be repeated here. In addition, the semiconductor device 200 includes a first recess 223 and a second recess 225. Some processes for forming the first recess 223 and the second recess 225 may be similar or identical to processes for forming the first recess 123 and the second recess 125 (i.e., the upper recess 109 and the lower recess 113) of the semiconductor device 100, and thus, a description thereof will not be repeated. However, the first recess 223 of the semiconductor device 200 is closer to the source electrode 117 than the second recess 225, which is different from the semiconductor device 100.
First thickness T of AlGaN layer 205 of semiconductor device 200 1 Is smaller than the first thickness T of the AlGaN layer 105 of the semiconductor device 100 1 Adjacent to the source electrode 117.
Embodiments of a semiconductor device, such as an enhanced High Electron Mobility Transistor (HEMT), and embodiments of methods of fabricating the same are provided. In some embodiments, upper and lower recesses are provided in the aluminum gallium nitride layer, and the gallium nitride layer is filled in the upper and lower recesses. Specifically, the upper recess is adjacent to the lower recess, and the width of the upper recess is greater than the width of the lower recess, so that the bottom surface of the GaN layer has a stepped shape. In other words, the gallium nitride layer has at least two different thicknesses, so that the threshold voltage of the semiconductor device can be easily and precisely controlled without affecting the breakdown voltage of the semiconductor device. Furthermore, the threshold voltage of the semiconductor device can be controlled without adding an additional doping process.
The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.
Claims (14)
1. A semiconductor device, comprising:
a first gallium nitride layer disposed on a semiconductor substrate;
the aluminum gallium nitride layer is arranged on the first gallium nitride layer;
an upper recess and a lower recess disposed within the AlGaN layer, wherein the upper recess is adjacent to the lower recess and has a width greater than the lower recess;
a second gallium nitride layer disposed in the upper recess and the lower recess, wherein the second gallium nitride layer is separated from the first gallium nitride layer by a portion of the aluminum gallium nitride layer, and the portion of the aluminum gallium nitride layer has a first thickness located below the upper recess, a second thickness located below the lower recess, and a third thickness located below a source electrode, wherein a first ratio of the first thickness to the third thickness is 0.6 to 0.8, and a second ratio of the second thickness to the third thickness is 0.2 to 0.4;
the grid structure is arranged on the second gallium nitride layer; and
the source electrode and a drain electrode are disposed on the aluminum gallium nitride layer, wherein the aluminum gallium nitride layer extends from the source electrode to the drain electrode and has a flat bottom surface, and the second gallium nitride layer has a first sidewall closest to the drain electrode and a second sidewall closest to the source electrode, wherein a first length of the first sidewall is less than a second length of the second sidewall.
2. The semiconductor device of claim 1, wherein the first gallium nitride layer and the aluminum gallium nitride layer are undoped, and the second gallium nitride layer is P-type.
3. The semiconductor device according to claim 1, wherein a bottom surface of the second gallium nitride layer is stepped.
4. The semiconductor device according to claim 1, wherein the source electrode is closer to the undercut than the drain electrode.
5. The semiconductor device according to claim 1, wherein the drain electrode is closer to the undercut than the source electrode.
6. The semiconductor device of claim 1, wherein a sidewall of the upper recess is aligned with a sidewall of the lower recess.
7. The semiconductor device according to claim 1, wherein the second gallium nitride layer protrudes from the aluminum gallium nitride layer, and wherein a bottom surface of the gate structure is higher than a bottom surface of the source electrode and a bottom surface of the drain electrode.
8. The semiconductor device of claim 1, wherein the second gallium nitride layer does not cover a top surface of the aluminum gallium nitride layer.
9. A manufacturing method of manufacturing the semiconductor device according to claim 1, comprising:
forming the first gallium nitride layer on the semiconductor substrate;
forming the aluminum gallium nitride layer on the first gallium nitride layer;
forming the upper recess in the aluminum gallium nitride layer;
forming the lower recess in the AlGaN layer through the upper recess, wherein the upper recess is adjacent to the lower recess and has a width greater than that of the lower recess;
forming the second gallium nitride layer in the upper recess and the lower recess;
forming the gate structure on the second gallium nitride layer; and
the source electrode and the drain electrode are formed on the aluminum gallium nitride layer.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the first gallium nitride layer and the aluminum gallium nitride layer are undoped, and wherein the second gallium nitride layer is P-type.
11. The method for manufacturing a semiconductor device according to claim 9, wherein the source electrode is located closer to the undercut than the drain electrode.
12. The method for manufacturing a semiconductor device according to claim 9, wherein a bottommost surface of the second gallium nitride layer is higher than a topmost surface of the first gallium nitride layer.
13. The method for manufacturing a semiconductor device according to claim 9, wherein a top surface of the second gallium nitride layer is higher than a top surface of the aluminum gallium nitride layer.
14. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the lower recess in the aluminum gallium nitride layer through the upper recess further comprises:
forming a patterned mask on the AlGaN layer, wherein a portion of the patterned mask fills the upper recess; and
the portion of the AlGaN layer exposed by the patterned mask is removed by performing an etching process to form the recess.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130158A (en) * | 2011-01-05 | 2011-07-20 | 西安电子科技大学 | Step-like groove-grid high electron mobility transistor |
| TW201427000A (en) * | 2012-12-19 | 2014-07-01 | Ind Tech Res Inst | Enhancement mode gallium nitride based transistor device |
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| TW201427000A (en) * | 2012-12-19 | 2014-07-01 | Ind Tech Res Inst | Enhancement mode gallium nitride based transistor device |
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